TWI222715B - Strained channel complementary metal-oxide semiconductor and method of fabricating the same - Google Patents
Strained channel complementary metal-oxide semiconductor and method of fabricating the same Download PDFInfo
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- TWI222715B TWI222715B TW092127405A TW92127405A TWI222715B TW I222715 B TWI222715 B TW I222715B TW 092127405 A TW092127405 A TW 092127405A TW 92127405 A TW92127405 A TW 92127405A TW I222715 B TWI222715 B TW I222715B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 161
- 230000000295 complement effect Effects 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 33
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 119
- 150000004767 nitrides Chemical class 0.000 claims abstract description 80
- 238000002955 isolation Methods 0.000 claims abstract description 64
- 239000010410 layer Substances 0.000 claims description 183
- 108091006146 Channels Proteins 0.000 claims description 131
- 238000000034 method Methods 0.000 claims description 75
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 45
- 229910052710 silicon Inorganic materials 0.000 claims description 44
- 239000010703 silicon Substances 0.000 claims description 44
- 238000005229 chemical vapour deposition Methods 0.000 claims description 33
- 150000002500 ions Chemical class 0.000 claims description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 23
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims description 22
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 claims description 20
- 238000005468 ion implantation Methods 0.000 claims description 18
- 239000004575 stone Substances 0.000 claims description 17
- 241000735576 Felicia Species 0.000 claims description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 15
- 239000002344 surface layer Substances 0.000 claims description 11
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- -1 nitride nitride Chemical class 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052754 neon Inorganic materials 0.000 claims description 4
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims description 4
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052724 xenon Inorganic materials 0.000 claims description 3
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 3
- 230000006835 compression Effects 0.000 claims 5
- 238000007906 compression Methods 0.000 claims 5
- 229910001922 gold oxide Inorganic materials 0.000 claims 2
- 239000000839 emulsion Substances 0.000 claims 1
- 239000000463 material Substances 0.000 description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 229910052814 silicon oxide Inorganic materials 0.000 description 24
- 238000005530 etching Methods 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000000126 substance Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 229910000167 hafnon Inorganic materials 0.000 description 3
- 150000002736 metal compounds Chemical class 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- WFSPUOYRSOLZIS-UHFFFAOYSA-N silane zirconium Chemical compound [SiH4].[Zr] WFSPUOYRSOLZIS-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- DOHZSESQJDLWFY-UHFFFAOYSA-N [SiH4].[Hf] Chemical compound [SiH4].[Hf] DOHZSESQJDLWFY-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910052845 zircon Inorganic materials 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 241000700159 Rattus Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
Description
1222715 五、發明說明(1) 【發明所屬之技術領域】 種包ίϊ::':關於一種場效電晶體,且特別是有關於- 廒六夕Ρ、刑 申應變之Ν型通道電晶體(NMOS)與具有壓縮 道電晶體刪)的互補式金氧半場效電晶艎 (CMOS) το件及其製作方法。 【先前技術】 隨著閘極元件尺寸的縮 (M0SFET)元件能在低操作 速的效能是相當困難的。因 氧半場效電晶體元件之效能 小化’要使金氧半場效電晶體 電壓下’具有高趨動電流和高 此’許多人在努力尋求改善金 的方法。 利用應變引發的能帶結構變型來增加載子的遷移率, 以增加場效電晶體的趨動電流,可改善 效能,i此種方法已被應用於各種元件中。件的牛; 通道係處於雙軸拉伸應變的情況。 已有研究指出利用石夕通道處於雙軸拉伸應變的情況中 來增加電子的遷移率(K· Ismail et al.,"Electron transport properties in Si/SiGe heterostructures: Measurements and device applications", Appl. Phys. Lett· 63,pp· 660,1 993·),及利用矽鍺通道處於雙轴 壓縮應變的情況中來增加電洞的遷移率(D· κ· Nayaket a 1. , "Enhancement-mode quantum-well GeSi PMOS", IEEE Elect· Dev. Lett· 12, pp. 154, 1991·)。然而, 結合具有雙軸拉伸應變之矽通道之NM0SFETs(N型金氧半場
0503-9889TWF(Nl);TSMC2003-0173;Felicia.ptd 頁 第7 1222715 五、發明說明(2) 效電晶體)及具有雙軸壓縮應變之矽鍺通道之PMOSFETs(P 型金氧半場效電晶體)之CMOS製程技術是難以達成的。在 電晶體之製造上有利用厚的缓衝層或複雜多層結構等許多 應變層製造方法(K. Ismail et al·, IBM,Jul· 1 996, Complementary metal-oxide semi conductor transistor logic using strained Si/SiGe heterostructure layers,U.S. Patent No· 553471 3·),此些方法並不易 於整合到傳統之CMOS製程中。
再者,更有研究提出以覆蓋一層應力膜於整個電晶體 上方的方式,以提供適當的應力予電晶體的通道區(A. Shimizu et a 1·, "Local mechanical stress control (LMC): A new technique for CMOS performance enhancement”, pp· 433-436 of the Digest of
Technical Papers of the 2001 International Electron Device Meeting.)
然而,於通道區導入壓縮應力有利於改善電動的遷移 速率,卻會對電子遷移率造成退化。因此,對N型通道電 晶體(NM0S)而言,需要導入拉伸應力以提升電子遷移率, 而對P型通道電晶體(PM0S)而言,需要導入壓縮應力以提 升電洞遷移率。但是在同一晶片上欲製作出同時具^有拉伸 應力通道區的N型通道電晶體(NM0S)與壓縮應力通道區 型通道電晶體(PM0S)之互補式金氧半導體(CM〇s),卻有相 當的困難。 有鑑於此,本發明提出一種可同時具拉伸應力通道區
1222715
與壓縮應力通道區的半導體基底及其製作方法 製作互補式金氧半導體。 可適用於 【發明内容】 艏月ίϊ:之目的在於一種具應變通道之互補式金氧半導 ί L ,則型通道電晶體的通道區具有拉伸庫 力,而Ρ型通道電晶體的通道區具有壓縮應力,整人 於同一晶片’以提升元件的操作速度。 本發明之主要特徵之一係在於N型通道電晶體兩 ^溝槽隔離區内順應性形成一氮化物襯墊層,帛以阻 於淺溝槽隔離區的氧化物擴散,以避免隔離氧:物 體積膨脹,並且氮化物襯墊層本身可提供N型電晶體的 導體基底通道區形成一拉伸應力。另外,將p型通道電曰 體兩侧的淺溝槽隔離區内的氮化物襯墊層施以離子佈植曰 以造成氮化物襯墊層内的缺陷形成,有利於後續填充於丄 溝槽隔離區的氧化物擴散,以於p型電晶體的半導體基、底、 通道區形成一壓縮應力。 -、為獲致上述之目的,本發明提出一種具應變通道之互 補式金氧半導體,主要係包括··一半導體基底、設置於上 述半導體基底内之複數溝槽隔離區、一氮化物襯墊層、 離子佈植氮化物襯墊層、一N型通道電晶體以及一p型通道 電晶體。其中,相鄰兩上述溝槽隔離區之間各定義出一主 動區,上述主動區包括一 N型主動區與一 P型主動區。另 外,上述氮化物襯墊層,順應性設置於上述N型主動區兩
1222715 五、發明說明(4) 側之上述溝槽隔離區與上述半導體基底之間。再者,上述 離子佈植氮化物襯墊層,順應性設置於上述p型主動區兩 側之上述溝槽隔離區與上述半導體基底之間。並且,上述 N型通道電晶體’設置於上述n型主動區上方。以及,上述 P型通道電晶體,設置於上述p型主動區上方。 如前所述,上述半導體基底包括:一矽基底、堆疊之 一矽層與一碎鍺層或堆疊之一第一矽基底、一埋入絕緣層 與一第二矽基底。 如前所述,上述溝槽隔離區之厚度大體為2〇〇〇〜6〇〇〇 A 〇 如刖所述,丄述溝槽隔離區係由一氧化物所構成。 如前所述,本發明之結構更包括:一氧化物襯墊層, 順應性設置於上述氮化物襯墊層與上述半導體基底之間。 如前所述,本#明之結構更包括:一氧化物襯墊層, 順應性設置於上述離子佈植氮化物襯墊層與上述半導體基 底之間。 土 如前所述,上述氮化物襯墊層係由氮化矽所構成,而 上述離子佈植氮化物襯墊層係由被施以離子佈植的氮化石夕 所構成。 如前所述’上述離子佈植氮化物襯墊層所被施加的離 子包括··矽(Si)離子、氮(N)離子、氦(He)離子、氖(Ne)離 子、鼠(Ar)、iS^(Xe)或錯離子。 根據本發明,上述N型主動區之上述半導體基底表層 具有一拉伸應變通道區。上述拉伸應變通道區之拉伸應變 0503-9889TW(Nl);TSMC2003.0173;Felicia.ptd 第10頁 1222715 五、發明說明(5) ' 量大體為0· 1%〜2%。 根據本發明’上述P型主動區之上述半導體基底表声 具有一壓縮應變通道區。上述壓縮應變通道區之拉伸應變 量大體為0· 1%〜2%。 … 根據前述之具應變通道之互補式金氧半導體,本發明 又提出·一種具應變通道之互補式金氧半導體的製作方 法,包括: 首先,供一半導體基底。接著,形成複數溝槽於上述 基底内,使得相鄰兩上述溝槽之間各定義出一主動區,其 中上述主動區包括一 N型主動區與一 P型主動區。接著,^ 應性形成一氮化物襯墊層,於各上述溝槽之側壁與底部。 接著,實施一離子佈植於上述P型主動區兩側之上述氮化 物襯墊層内。然後,形成複數溝槽隔離物,以填滿各上述 溝槽。接著,形成一 N型通道電晶體於上述n型主動區上 方。最後,形成一 P型通道電晶體於上述P型主動區上方。 如前所述,形成上述N型通道電晶體與上述p型通道電 晶體之後更包括:分別形成一應力膜,覆蓋於上述N型通道 電晶體與上述P型通道電晶體表面。上述應力膜係由化學 氣相沉積法(chemical vapor deposition ;CVD)所形成。 本發明之主要特徵之二係在於N型通道電晶體兩側的 淺溝槽隔離區内順應性形成一氮化物襯墊層,用以阻擋後 續填充於淺溝槽隔離區的氧化物擴散,以避免隔離氧化物 體積膨脹,並且氮化物襯墊層本身可提供N型電晶體的半 導體基底通道區形成一拉伸應力。另外,P型通道電晶體
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兩側的淺溝槽隔離區内並無氮化物襯墊層,後續填充於淺 溝槽隔離區的氧化物會體積膨脹,導致於p型電晶體的半 導體基底通道區形成一壓縮應力。 為獲致上述之目的’本發明提出一種具應變通道之互 補式金氧半導體’主要係包括:一半導體基底、複數溝槽 隔離區、一氮化物襯墊層、一N型通道電晶體、一P型通道 電晶體。其中,上述溝槽隔離區,設置於上述半導體基底 内,使得相鄰兩上述溝槽隔離區之間各定義出一主動區, 上述主動區包括一 N型主動區與一 p型主動區。並且,上述 氮化物襯墊層,順應性設置於上述N型主動區兩側之上述 溝槽隔離區與上述半導體基底之間。再者,上述N型通道 電晶體’設置於上述N型主動區上方。以及,上述p型通道 電晶體,設置於上述P型主動區上方。 如前所述,上述半導體基底包括:一矽基底、堆疊之 一矽層與一矽鍺層或堆疊之一第一矽基底、一埋入絕緣層 與一第二矽基底。 曰 如前所述,上述溝槽隔離區之厚度大體為2〇〇〇〜6〇〇() A 〇 如前所述,上述溝槽隔離區係由一氧化物所構成。 如前所述’本發明之結構更包括:一氧化物襯塾層, 順應性設置於上述氮化物襯墊層與上述半導體基底之間。 如前所述,上述氮化物襯墊層係由氮化矽所構成。 根據本發明’上述N型主動區之上述半導體基底表層 具有一拉伸應變通道區,上述拉伸應變通道區之拉伸應變
1222715 五、發明說明(7) 量大艘為0. 1%〜2%。 根據本發明,上述p切 - m m m m ^ ^ 生動£之上述半導體基底表層 量大體為0· 1%〜2%。 _應隻通道區之拉伸應變 根據前述之具應變通道之 更提出一種具應變通s ^ ^式金乳丰導體,本發明 包括:禋具應變通道之互補式金氧半導體的製作方法, 述基:ί’ί供一半導體基底。接著,形成複數溝槽於上 ΐΐίϊ主Γ3:兩上述溝槽之間各定義出-主動區 其I上述主動區包括一 Ν型主動區與一 ρ型主動區。 成-氮化物襯塾層,於上則型主動區各 ίίί?1壁與底部。接著,形成複數溝槽隔離物以 真滿各上述溝槽》形成一 Ν型通道電晶體於上述Ν型主 ^方。最後,形成一Ρ型通道電晶體於上述ρ型主動區上品 為使本發明之上述目的、特徵和優點能更明顯易僅, ^文特舉較佳實施例,並配合所附圖式,作詳細說明如 【實施方式】 實施例1 以下請參照第1 G圖,說明根據本發明之具應變通道 互補式金氧半導體之一較佳實施例。 其主要係包括:一半導體基底100、複數溝槽隔離區 0503-9889TW(Nl);TSMC2003-0173;Felicia.ptd 第13頁 1222715 五、發明說明(8) 104a、104b、一氮化物襯墊層1〇8、一離子佈植氮化物襯 墊層108a、一N型通道電晶體117以及一p型通道電晶體 116 〇 内 區 井) 其中,溝槽隔離區104a、104b設置於半導體基底1〇〇 且相鄰兩溝槽隔離區l〇4a、104b之間各定義出一主動 而主動區包括一 N型主動區(η-井)與一 p型主動區(p->溝槽隔離區104a、104b内填滿隔離氧化物112。 另外,氮化物襯墊層1 0 8順應性設置於N型主動區(n-井)兩侧之溝槽隔離區104b與半導體基底1〇〇之間。氮化物 襯塾層108的設置為本發明的特徵之一。氮化物襯墊層 可用以阻擋後續填充於淺溝槽隔離區的氧化物1丨2擴散, 進而避免隔離氧化物112體積膨脹,並且氮化物襯墊層本 身具有拉伸應力(intrinsic tensile stress),導致對溝 槽104b的側壁施加一垂直壓縮應力(vert icai compressive stress)以及可提供N型電晶體117的半導體 基底100通道區形成一拉伸應力。 再者,離子佈植氮化物襯墊層1 〇 8 a順應性設置於P型 主動區(ρ-井)兩側之溝槽隔離區l〇4a與半導體基底1〇〇之 間。離子佈植氮化物襯墊層1 〇 8 a内具有缺陷,有利於後續 填充於淺溝槽隔離區的氧化物擴散,造成體積膨脹,以於 P型電晶體116的半導體基底1〇〇通道區形成一壓縮應力。 並且,N型通道電晶體117設置於N型主動區(η-井)上 方。以及,Ρ型通道電晶體116,設置於ρ型主動區(Ρ—井) 上方。如此一來,Ν型通道電晶體117下方的通道區具有一
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拉伸應力,可提升電子遷移率❶p型通道電晶體116下方的 通道區具有一慶縮應力,可提升電洞遷移率。 實施例2 以下請配合參考第1A圖至第11{圖之製程剖面圖,說明 根據本發明之實施例1之具應變通道之互補式金 之製作方法。 首先,請參照第1A圖,提供一半導體基底1〇〇,其包 括:一矽基底、堆疊之一矽層與一矽鍺層或是堆疊之一第 一矽基底、一埋入絕緣層與一第二矽基底,即所謂的絕緣 層上覆矽(si 1 icon-on-insula tor ; SOI),甚至可以县 a 含碎化鎵或磷化銦的化合物。 接著,凊參照第1 B圖,形成複數溝槽1 〇 4 a、1 q 4匕於半 導體基底100内。例如先形成一圖案化罩幕層1〇2於半導體 基底1 00表面,然後利用適當蝕刻法,例如:非等向性電漿 蝕刻法(anisotropic plasma etching),該電漿可以為含 氟化學物質,較佳為CF4,透過圖案化罩幕層102以形成複 數溝槽104a、l〇4b,使得相鄰兩溝槽丨04a、1041)之間各定 義出一主動區。本發明係強調應用kCM0S元件,所以圖式 中主動區包括一N型主動區(11-井)與一p型主動區㈧一井)二 N型主動區(η-井)與p型主動區㈧—井)係分別以摻雜不同導 電型態的摻雜物於半導體基底丨00内所形成。溝槽隔離區 104a、104b之厚度大體為2〇〇〇〜6〇〇〇 Α。圖案化^幕層1〇2 之材質可包括··氧化矽、氮化矽或是堆疊之氧化矽與&化
1222715 五、發明說明(ίο) 矽,其中以堆疊之氧化矽與氮化矽為較佳。 接著’請參照第1C圖,先例如以熱氧化法(the rma 1 oxidation)於溫度約600〜l〇〇(Tc下通入水氣與氧氣,或是· 直接以化學氣相沉積法(CVD),順應性形成一氧化物襯墊 _ 層106於溝槽104a、104b的側壁與底部表面。接著,在例 如以適當之化學氣相沉積法(Chemicai vap〇r d e p o s i t i ο η,C V D )順應性形成一氣化物襯墊層1 q 8於氧化 物襯墊層1 0 6表面,使得氧化物襯墊層1 〇 6在溝槽1 〇 4 a、 10 4b内夾設於氮化物襯墊層1〇8與半導體基底1〇〇之間。氧 化物襯墊層106不僅可以增加氮化物襯墊層1〇8的附著力, 更可以緩衝以化學氣相沉積(CVD)形成氮化物襯墊層1〇8時 對半導體基底100所造成的損傷。其中,形成氮化物襯墊 層108之反應性氣體可包括氨(ammonia)與烧類(si iane)。 接著,請再參照第1 D圖,形成一離子佈植罩幕丨丨〇於 整個N型主動區(η-井)上方,其材質例如為光阻 (photoresist)。然後,以離子佈植罩幕HQ為遮蔽,實施 一離子佈植程序S1 00於P型主動區(p—井)兩側之氮化物襯 塾層108内,也就是溝槽l〇4b中之氮化物襯墊層1〇8内。離 子佈植程序S1 0 0可以為傳統的束線離子佈植程序 (beam-line ion implantation process),也可以是電衆· 入浸離子佈植(plasma immersion ion implantation ; PIII),或是任何其他習知的離子佈植程序,離子佈植 sioo可包括:矽(Si)離子、氮(N)離子、氦(He)離子、氖 (Ne)離子、氬(Ar)、氙(Xe)或鍺離子,其劑量約為每平方
0503-9889TW(Nl);TSMC2003-0173;Felicia.ptd 第16頁 1222715 五、發明說明 公分下1E13〜1E16個離子量,施加能量約為ι〇6ν〜ι〇〇|^ν。 氮化物襯墊層1 08被施加離子佈植之後會增加其内部的缺 陷,使得不僅其本身的應例會降低,更可使後續填充於溝 槽的隔離物容易擴散,進而造成體積膨脹,以至於對Ρ型 主動區(Ρ-井)的半導體基底10〇表層(即通道區)形成一壓 縮應力。 接著,請再參照第1 Ε圖,先以適當腐蝕溶液將離子佈 植罩幕11 0移除,再形成隔離物11 2以填滿溝槽1 〇4a、 10 4b。隔離物112之材質可以包括氧化物,例如氧化石夕, 或是由氧化石夕與多晶石夕之組合所構成。然後再以化學機械 研磨法(chemical mechanical polishing ;CMP)使隔離物 112表面平坦化,以完成淺溝槽隔離區(以&11(^ treneh isolation ;STI)的製作。 接著’請參照第1 F圖,再以適當腐蝕溶液移除圖案化 罩幕層102,當圖案化罩幕層102之材質包括氧化矽與^化 矽時,較佳實施例為先以熱磷酸溶液去除氮化矽, 接 釋氫氟酸去除氧化矽。 接著,請參照第1 G圖,分別形成一 N型通道電晶體11 7 於N型主動區(η-井)上方以及形成一p型通道電晶體丨16於p 型主動區(Ρ-井)上方。先於Ν型主動區(η-井)與ρ型主動區 (Ρ-井)之半導體基底1〇〇表面形成閘極介電層丨14,閑極介 電層11 4例如為氧化石夕層’其形成方法例如是利用化學°氣 相沈積法(CVD)、熱氧化法(thermal oxidation)、氣化法 (nitridation)、濺鍍法(sputtering)或是任何習知形成
1222715 五、發明說明(12) 〜 閘極介電層的方法,其材質可包括氧化矽、氮化矽、氮氧 化矽,其厚度約為3〜100 A,或是其他高介電常數(high permittivity ;high_k)材質,包括:氧化鋁(Al2〇3)、氧化 铪(Ηί〇2)、氮氧化铪(Hf0N)、矽烷化铪(HfSi〇4)、矽烷化 锆(ZrSi〇4)、氧化鑭(LaJ3)等,其等效氧化物厚度 (equivalent oxide thickness ; EOT)約為3〜100 A ,其 中閘極介電層114之材質以氮氧化矽為較佳。然後,再於 閘極介電層1 1 4表面形成一閘極層丨丨5,閘極層丨丨5知材質 包括:多晶矽、多晶矽鍺、金屬化合物包含:鉬(M〇)、鎢 (W)或氮化鈦(TiN),抑或者是其他導電材質,以多晶矽為 較佳。閘極介電層1 1 4與閘極層11 5共同構成一閘極結構 11 6、11 7。然後再利用一罩幕採用選擇性蝕刻,圖案化閘 極介電層1 1 4與閘極層π 5,以定義出閘極結構丨丨6、丨丨7的 圖案。並分別於閘極結構116、117兩側之[^型主動區(n — 井)與P型主動區(p-井)進行n型和p型離子摻雜,以及於閘 極結構116、117的側壁形成間隙壁118,間隙壁118的材質 例如為氮化矽或氧化矽。然後再例如利用離子佈植法於間 ,壁11 8外側的半導體基底丨〇 〇内形成汲極/源極。這些電 晶體的製成可以根據任何習知半導體電晶體製造技術加以 被製,在此並不加限制與贅述。 如此,在半導體基底1〇〇上,便形成N型通道電晶體 117於具有拉伸應力的通道區上方,拉伸應變通道區之拉 伸應變量大體為0· 1%〜2%,且形成p型通道電晶體116於具 有壓縮應力的通道區上方,壓縮應變通道區之拉伸應變量
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〜2%。如此一來’ N型通道電晶趙"7下方的通 拉伸應力,可提升電子遷移率型通道電晶 16下方的通道區具有一壓縮應力,可提升電洞遷移 請參照第1 Η圖,N型通道電晶體丨〗7與p型通道電晶體 11 6表面更可以分別以化學氣相沉積法(^^丨ca夏vap〇r deposition ; CVD)覆蓋一應力膜122、丨2(),加以提供適當 實施例3 、以下請參照第2G圖,說明根據本發明之具應變通道之 互補式金氧半導體之一較佳實施例。 其主要係包括:一半導體基底2〇〇、複數溝槽隔離區 20 4a、204b、一氮化物襯墊層2〇8、—N型通道電晶體217 以及一P型通道電晶體216。 其中’溝槽隔離區204a、204b設置於半導體基底200 内’且相鄰兩溝槽隔離區204a、20 4b之間各定義出一主動 區,而主動區包括一N型主動區(n-井)與一p型主動區(p一 井)。溝槽隔離區204a、204b内填滿隔離氧化物212。 另外,氣化物襯墊層2 〇 8順應性設置於N型主動區(η-井)兩側之溝槽隔離區2〇4b與半導體基底20 0之間。氮化物 概塾層208的設置為本發明的特徵之一。氡化物襯墊層2〇8 可用以阻擂後續填充於淺溝槽隔離區的氧化物2丨2擴散, 進而避免隔離氧化物212體積膨脹,並且氮化物襯墊層2〇8
0503-9889TWF(Nl);TSMC2003-0173;Felicia.ptd 第19頁 1222715 發明說明(14) 本身具有拉伸應力(intrinsic tensile stress),導致對 溝槽204b的側壁施加一垂直壓縮應力(verticai compressive stress)以及可提供N型電晶體217的半導體 基底200通道區形成一拉伸應力。 然而’溝槽2 〇 4 a内並無氮化物襯墊層,後續填充於淺 溝槽隔離區的氧化物會發生擴散,造成體積膨脹,以於p 型電晶體216的半導體基底2〇〇通道區形成一壓縮應力。
並且’N型通道電晶體217設置於N型主動區(n-井)上 方。以及,Ρ型通道電晶體216,設置於ρ型主動區(1)一井) 上方。如此一來,Ν型通道電晶體2 17下方的通道區具有一 拉伸應力,可提升電子遷移率。ρ型通道電晶體216下方的 通道區具有一壓縮應力,可提升電洞遷移率。 實施例4 以下請配合參考第2Α圖至第2Η圖之製程剖面圖,說明 根據本發明之實施例3之具應變通道之互補式金氧半導體 之製作方法之一。 首先,請參照第2A圖,提供一半導體基底2〇〇,其包 括··一矽基底、堆疊之一矽層與一矽錯層或是堆最 _
-石夕基底、-埋入絕緣層與一第二石夕基底戈疋二 層上覆矽(silicon-on-insulator ;S0I),甚至可以是包 含砷化鎵或磷化銦的化合物。 接著’清參照第2B圖’形成複數溝槽2〇4a、204b於半 導體基底200内。例如先形成一圖案化罩幕層2〇2於半導體
1222715 五、發明說明(15) -------- 二表面,然後利用適當蝕刻法,例如: 蝕刻法(aniS〇tropic plasma etching),該電漿 氟化學物質,較佳為CF4,透過圖案化罩幕層2 成3 數溝槽204a、204b,使得相鄰兩溝槽2〇“、2〇4b之間^ 義出一主動區。本發明係強調應用KCM0S元件, = 中主動區包括一N型主動區(n-井)與一P型主動區 井, Ν型主動區(η-井)與ρ型主動_—井)係分別以摻雜不同導 電型態的摻雜物於半導體基底200内所形成。溝槽隔離區 204a、204b之厚度大體為2000〜600 0 Α。圖案化^幕層&2 之材質可包括··氧化矽、氮化矽或是堆疊之氧化矽與氮化 石夕’其中以堆疊之氧化矽與氮化矽為較佳。 接著,請參照第2C圖,先例如以熱氧化法(thermal oxidation)於溫度約600〜100{rc下通入水氣與氧氣,或是 直接以化學氣相沉積法(CVD),順應性形成一氧化物襯墊 層206於溝槽204a、204b的側壁與底部表面。接著,在例 如以適當之化學氣相沉積法(c h e m i c a 1 v a ρ 〇 r deposition ;CVD)順應性形成一氮化物襯墊層2〇8於氧化 物襯墊層206表面,使得氧化物襯墊層206在溝槽204a、 204b内夾設於氮化物襯墊層2〇8與半導體基底200之間。氧 化物襯墊層206不僅可以增加氮化物襯墊層208的附著力, 更可以緩衝以化學氣相沉積(CVD)形成氮化物襯墊層208時 對半導體基底200所造成的損傷。其中,形成氮化物襯墊 層208之反應性氣體可包括氨(ammonia)與烧類(siiane)。 接著,請再參照第2D圖,形成一材質例如為光阻之罩
1222715 五、發明說明(16) 幕層210於整個主動區(n—井),然後以適當溶液例 如:熱磷酸溶液,去除位於P型主動區(p_井)兩側溝槽2〇切 内之氮化物襯墊層2 〇 8。
接著,凊再參照第2E圖,先以適當腐蝕溶液將罩幕層 210移除,再形成隔離物212以填滿溝槽2〇紅、2〇仂。隔離 物212之材質可以包括氧化物,例如氧化#,或是由氧化 石夕與多晶石夕之組合所構成。然後再以化學機械研磨法 (chenncal mechanical p〇iishing ;CMp)使隔離物 212 表 面平坦化,以完成淺溝槽隔離區(shaU〇w tfeneh isolation ; STI )的製作。 接著,請參照第2F圖,再以適當腐蝕溶液移除圖案化 罩幕層202,當圖案化罩幕層202之材質包括氧化矽與氮化 矽時,較佳實施例為先以熱磷酸溶液去除氮化矽, 釋氫氟酸去除氧化石夕。 ^
接著,研參照第2 G圖,分別形成一 n型通道電晶體2 1 γ 於Ν型主動區(η-井)上方以及形成一ρ型通道電晶體216於? 型主動區(Ρ-井)上方。先於Ν型主動區(11—井)與?型主動區 (Ρ-井)之半導體基底2〇〇表面形成閘極介電層214,閘極介 電層214例如為氧化矽層,其形成方法例如是利用化學氣1 相沈積法(CVD)、熱氧化法(thermal 〇xidati〇n)、氮化法 (nitridation)、濺鍍法(sputtering)或是任何習知形 閘極介電層的方法,其材質可包括氧化矽、氮化矽、氮氧 化石夕,其厚度約為3〜ΐοοΑ,或是其他高介電常數 permittivity ; high-k)材質,包括:氧化鋁(Al2〇3)、氧化
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給(HfOO、氮氧化铪(Hf0N)、矽烷化給(HfSi〇4)、矽烷化 锆(ZrSi〇4)、氧化鑭等,其等效氧化物厚度 (equivalent oxide thickness ; EOT)約為3〜100 A ,其 中閘極介電層214之材質以氮氧化矽為較佳。然後,再於 閘極介電層214表面形成一閘極層215,閘極層215知材質 包括:多晶矽、多晶矽鍺、金屬化合物包含··鉬(M〇)、鎢、 (W)或氮化鈦(TiN),抑或者是其他導電材質,以多晶矽為 較佳。閘極介電層214與閘極層215共同構成一閘極結構 216、217。然後再利用一罩幕採用選擇性蝕刻,圖案化閘 極w電層214與閘極層215,以定義出閘極結構216、217的 圖案。並分別於閘極結構216、217兩側之主動區(n — 井)與P型主動區(p-井)進行n型和p型離子摻雜,以及於閘 極結構216、217的側壁形成間隙壁218,間隙壁218的材質 例如為氮化矽或氧化矽。然後再例如利用離子佈植法於間 隙壁218外側的半導體基底2〇〇内形成汲極/源極。這些電 晶體的製成可以根據任何習知半導體電晶體製造技術加以 被製,在此並不加限制與贅述。 如此,在半導體基底200上,便形成N型通道電晶體 217於具有拉伸應力的通道區上方,拉伸應變通道區之拉 伸應變量大體為0· 1%〜2%,且形成p型通道電晶體216於具 有壓縮應力的通道區上方,壓縮應變通道區之拉伸應變量 大體為0· 1%〜2%。如此一來,N型通道電晶體217下方的通 道區具有一拉伸應力,可提升電子遷移率。P型通道電晶 體216下方的通道區具有一壓縮應力,可提升電洞遷移
1222715 五、發明說明(18) 率〇 請參照第2H圖’ N型通道電晶體217與P型通道電晶體 216表面更可以分別以化學氣相沉積法(chemical vap〇r deposition ;CVD)覆蓋一應力膜222、220,加以提供適當 的應力。 實施例5 以下請配合參考第3A圖至第3H圖之製程剖面圖,說明 根據本發明之實施例3之具應變通道之互補式金氧半導體 之製作方法之二。 首先,請參照第3A圖’提供一半導體基底3〇〇,其包 括:一矽基底、堆疊之一矽層與一矽鍺層或是堆疊之一第 一石夕基底、一埋入絕緣層與一第二石夕基底,即所謂的絕緣 層上覆石夕(silicon-on-insulator ;S0I),甚至可以是包 含砷化鎵或磷化銦的化合物。 接者,請參照第3B圖,形成複數溝槽3〇4a、3〇41)於半 導體基底300内。例如先形成一圖案化罩幕層3〇2於半導體 基底300表面,然後利用適當蝕刻法,例如:非等向性電漿 蝕刻法(anisotropic Plasma etching),該電 氟化學物質,較佳為cf4,透過圖案化罩幕層3〇2以忐3 數溝槽304a、304b ’使得相鄰兩溝槽3〇4a、3〇乜之^ \ 義出-主動區。本發明係強調應用於CM〇s元二: 中主動區包括-N型主動區(n_井)與一p 所二圖式 _主動區(η—井)與P型主動區…井)係分別以摻雜Λ導
1222715 五、發明說明(19) "~" 電型態的摻雜物於半導體基底3〇〇内所形成。溝槽隔離區 304a、304b之厚度大體為2〇〇〇〜6〇〇()a。圖案化罩幕層3〇2 之材質可包括:氧化矽、氮化矽或是堆疊之氧化矽與氮化 梦’其中以堆疊之氧化矽與氮化矽為較佳。 接著’請參照第3C圖,先例如以熱氧化法(thermal oxidation)於溫度約600〜1〇〇〇〇c下通入水氣與氧氣,或是 直接以化學氣相沉積法(CVD),順應性形成一氧化物襯墊 層306於溝槽304a、304b的側壁與底部表面。 接著,请再參照第3 D圖,進行形成氮化物襯塾層3 〇 8 步驟S300。此步驟是本發明之實施例3的結構之製作方法 中與前述實施例4主要差異的步驟。先形成一罩幕311於整 個P型主動區(p-井)上方,例如以適當之化學氣相沉積法 (chemical vapor deposition ;CVD)、含氮離子佈植法或 是在含氮氣氛下進行退火,抑或是施以含氮電漿處理,順 應性形成一氮化物襯墊層3〇8於N型主動區(n-井)之兩側溝 槽304b的氧化物襯墊層306表面,使得氧化物襯墊層3〇6在 溝槽3 0 4 a内夾設於氮化物襯墊層3 〇 8與半導體基底3 0 0之 間。氧化物襯墊層306不僅可以增加氮化物襯墊層3〇8的附 著力,更可以緩衝以化學氣相沉積(CVD)形成氮化物襯墊 層308時對半導體基底300所造成的損傷。其中,形成氮化 物襯塾層308之反應性氣體可包括氨(ammon丨a)與烧類 (silane) 〇 接著,請再參照第3E圖,先以適當腐蝕溶液將罩幕層 3 11移除,再形成隔離物3 1 2以填滿溝槽3 〇 4 a、3 0 4 b。隔離
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物31 2之材質可以包括氧化物,例如氧化矽,《是由氧化 石夕與多晶③之組合所構成。然後再以化學機械研磨法 (chemical mechanical p〇Hshing ;CMp)使隔離物312 表 面平坦化’以完成淺溝槽隔離區(shall〇w trench isolation ; STI)的製作。 接著,清參照第3F圖,再以適當腐蝕溶液移除圖案化 罩幕層302 ’當圖案化罩幕層3〇2之材質包括氧化矽與氮化 矽時,較佳實施例為先以熱磷酸溶液去除氮化矽,再以 釋氫氟酸去除氧化石夕。
接著,凊參照第3 G圖,分別形成一 n型通道電晶體3 i 7 於N型主動區(n-井)上方以及形成型通道電晶體216於? 51主動區(P井)上方。先於N型主動區。—井)與p型主動區 (P-井)之半導體基底300表面形成閘極介電層314,閘極介 電層3 1 4例如為氧化矽層,其形成方法例如是利用化學氣
相沈積法(CVD)、熱氧化法(thermal oxidation)、氮化法 (nitridation)、濺鍍法(sputtering)或是任何習知形成 閘極介電層的方法,其材質可包括氡化矽、氮化矽、氮氧 化矽,其厚度約為3〜100 A,或是其他高介電常數(high permittivity ;high-k)材質,包括:氧化鋁(a%)、氧化 铪(Hf02)、氮氧化铪(Hf0N)、矽烷化铪(HfSi〇4)、矽烷化 锆(ZrSiOJ、氧化鑭(1^〇3)等,其等效氧化物厚度 (equivalent oxide thickness ;E0T)約為3〜1〇〇 A ,盆 中閘極介電層314之材質以氮氧化矽為較佳。然後,再ς 閘極;I電層3 1 4表面形成一閘極層3丨5,閘極層3丨5知材質
1222715 五、發明說明(21) 一"一"—--— 包括:多晶矽、多晶矽鍺、金屬化合物包含:鉬(M〇)、 (W)或氮化鈦(TiN),抑或者是其他導電材質,以多晶石夕 較佳。閘極介電層314與閘極層315共同構成一閘極結構… 316、317。然後再利用一單幕採用選擇性蝕刻,圖案化 極介電層314與閘極層315,以定義出閘極結構316、31?的 圖案。並为別於閘極結構31 6、31 7兩側之n型主動區(n 一 井)與P型主動區(P-井)進行n型和p型離子摻雜,以及於閘 極結構316、317的側壁形成間隙壁318,間隙壁318的材質 例如為氮化矽或氧化矽。然後再例如利用離子佈植法於間 隙壁318外側的半導體基底3〇〇内形成汲極/源極。這些電 晶體的製成可以根據任何習知半導體電晶體製造技術加以 被製,在此並不加限制與贅述。 如此’在半導體基底3〇〇上,便形成n型通道電晶體 317於具有拉伸應力的通道區上方,拉伸應變通道區之拉 伸應變量大體為0 · 1 %〜2 %,且形成p型通道電晶體3丨6於具 有壓縮應力的通道區上方,壓縮應變通道區之拉伸應變量 大體為0.1%〜2%。如此一來,N型通道電晶體317下方的通 道區具有一拉伸應力,可提升電子遷移率。p型通道電晶 體316下方的通道區具有一壓縮應力,可提升電洞遷移 請參照第3 Η圖’ Ν型通道電晶體3 1 7與Ρ型填道電晶體 316表面更可以分別以化學氣相沉積法(chemical vapor deposition ;CVD)覆蓋一應力膜32 2、320,加以提供適當 的應力。
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發明優點: 1 ·根據本發明之N型通道電晶體具有拉伸應力而p型通 、電晶體具有壓縮應力,因此可同時提升N型通道的電子 ,移率以及P型通道的電洞遷移率,有效提升元件操作速 ,2·、根據本發明之互補式金氧半電晶體(CM〇s),以簡箪 的製成方式整合N型通道電晶體與p型通道電晶體於同一晶 片,分:別有適當可提升操作速度之應力。
本發明雖以較佳實施例揭露如上,然其·並非用以限定 扯發明的範圍’任何熟習此項技藝者,在不脫離本發明之 精神和範圍内,當可做各種的更動與潤飾,因此本發明之 呆”蔓範圍當視後附之申請專利範圍所界定者為準。
第28頁 1222715 圖式簡單說明 第1A圖至第1H圖係顯示根據本發明之具應變通道之互 補式金氧半導體之一較佳實施例之製程剖面圖。 第2 A圖至第2H圖係顯示根據本發明之具應變通道之互 補式金氧半導體之另一較佳實施例之製程剖面圖。 第3 A圖至第3H圖係顯示根據本發明之具應變通道之互 補式金氧半導體之又一較佳實施例之製程剖面圖。 【符號說明】 100、200、300〜半導體基底; 102、202、302〜圖案化罩幕層; . 104a、104b、204a、204b、304a、304b 〜溝槽隔離 區, 106、206、306〜氧化物襯墊層; 108、208、308〜氮化物襯墊層; 108a〜離子佈植氮化物襯墊層; 112、212、312〜隔離氧化物; 117、 217、317〜N型通道電晶體; 116、216、316〜P型通道電晶體; S1 0 0〜離子佈植程序; 11 4、2 1 4、3 1 4〜閘極介電層; 115、215、31 5〜閘極層; 118、 218、318〜間隙壁; 122、120、220、222、320、322 〜應力膜; 210、311〜罩幕層;
0503-9889TWF(Nl);TSMC2003-0173;Felicia.ptd 第 29 頁 1222715 圖式簡單說明 S1 0 0〜形成氮化物襯塾層程序 0503-9889TWF(Nl);TSMC2003-0173;Felicia.ptd 第 30 頁 1··
Claims (1)
1222715 六、申請專利範圍 ------ !· 一種具應變通道之互補式金氧半導體,包括: 一半導體基底; 複數溝槽隔離區,設置於上述半導體基底内,使得相 叙兩上述溝槽隔離區之間各定義出一主動區,其中上述主 動區包括一 N型主動區與一 P型主動區; 一氮化物襯墊層,順應性設置於上述N型主動區兩側 之上述溝槽隔離區與上述半導體基底之間; 一離子佈植氮化物襯墊層,順應性設置於上述p型主 動區兩側之上述溝槽隔離區與上述半導體基底之間; N型通道電晶體’設置於上述n型主動區上方;以及 一 P型通道電晶體,設置於上述p型主動區上方。 一 2 ·如申請專利範圍第1項所述之具應變通道之互補式 金氧半導體’其中上述溝槽隔離區係由一氧化物所構成。 3 ·如申請專利範圍第1項所述之具應變通道之互補式 金氧半導體,其中更包括:一氧化物襯墊層,順應性設置 於上述氮化物襯墊層與上述半導體基底之間。 4·如申請專利範圍第1項所述之具應變通道之互補式 金氧半導體’其中更包括:一氧化物襯墊層,順應性設置 於上述離子佈植氮化物襯墊層與上述半導體基底之間。 5 ·如申請專利範圍第1項所述之具應變通道之互補式 金氧半導體’其中上述氮化物襯墊層係由氮化石夕所構成。 6 ·如申請專利範圍第1項所述之具應變通道之互補式 金氧半導體,其中上述離子佈植氮化物襯墊層係由被施以 離子佈植的氮化矽所構成。
0503-9889TW(Nl);TSMC2003-0173;Felicia.ptd 第31頁 I 1222715 六、申請專利範圍 7·如申請專利範圍第1項所述之具應變通道之互補式 金氧半導體,其中上述離子佈植氮化物襯墊層所被施加的 離子包括:矽(si)離子、氮(Ν)離子、氦(He)離子、氖(Ne) 離子、氬(Ar)、氙(Xe)或鍺離子。 8·如申請專利範圍第1項所述之具應變通道之互補式 金氧半導體,其中上述N型主動區之上述半導體基底表層 具有一拉伸應變通道區。 9·如申請專利範圍第8項所述之具應變通道之互補式 金氧半導體,其中上述拉伸應變通道區之拉伸應變量大體 為〇· U〜2% 〇 , " _ 10 ·如申請專利範圍第1項所述之具應變通道之互補式 金氧半導體,其中上述P型主動區之上述半導體基底表層 具有一壓縮應變通道區。 ·、如申請專利範圍第1 0項所述之具應變通道之互補 式金氧半導體,其中上述壓縮應變通道區之拉伸應變量大 體為0.1%〜2%。 I2·如申請專利範圍第1項所述之具應變通道之互補式 金氧半導體’其中上述半導體基底包括:一矽基底、堆疊 石夕層與-石夕鍺層或堆疊之一第一石夕基底、一埋入絕緣 層與一第二矽基底。, 金氧導如/請範圍第1項所述之具應變通道之互補式 述溝槽隔離區之厚度大體為 2000〜6000 A。 14· 一種具應變通道之互補式金氧半導體,包括:
1222715
一半導體基底; 複數溝槽隔離區,設置於上述半導體基底内,使得相 ^述溝槽隔離區之間各定義出一主動區,其中上述主 區匕括一N型主動區與一 p型主動區; =氮化物襯墊層,順應性設置於上述N型主動區兩側 之上述溝槽隔離區與上述半導體基底之間; 一 N型通道電晶體,設置於上述n型主動區上方;以及 P型通道電晶體,設置於上述p型主動區上方。 1 5 ·、如申請專利範圍第14項所述之具應變通道之互補 式金氧半導體,其中上述溝槽隔離區係由一氧化物所構 成。 、1 6·如申請專利範圍第1 4項所述之具應變通道之互補 式金氧半導體’其中更包括:一氧化物襯塾層,順應性設 置於上述氮化物襯墊層與上述半導體基底之間。 1 7 ·如申請專利範圍第1 4項所述之具應變通道之互補 式金氧半導體’其中上述氮化物襯墊層係由氮化矽所構 成。 1 8·如申請專利範圍第14項所述之具應變通道之互補 式金氧半導體,其中上述N型主動區之上述半導體基底表 層具有一拉伸應變通道區。 1 9·如申請專利範圍第1 8項所述之具應變通道之互補 式金氧半導體,其中上述拉伸應變通道區之拉伸應變量大 體為0· Γ/。〜2% 〇 20·如申請專利範圍第14項所述之具應變通道之互補
0503-9889TW(Nl);TSMC2003-0173;Felicia.ptd 第33頁 1222715 /、、申請專利範圍 式金氧半導體,其令上述P型主動區之上述半導體基底表 層具有一壓縮應變通道區。 .21·如申請專利範圍第20項所述之具應變通道之互補 式金氧半導艘,其中上述拉伸應變通道區之拉伸應變量大 體為0. 1%〜2%。 、22·如申請專利範圍第14項所述之具應變通道之互補 式金氧半導體,其中上述半導體基底包括:一矽基底、堆 叠之一石夕層與一石夕錯層或堆疊之一第一石夕基底、一埋入絕 緣層與一第二矽基底。 , 、23·如申請專利範圍第14項所述之具應變通道之互補 式金氧半導體’其中上述溝槽隔離區之厚度大體為 2000〜6000 A 〇 24· —種具應變通道之互補式金氧半導體的製作方 法,包括: 提供一半導體基底; 形成複數溝槽於上述基底内,使得相鄰兩上述溝槽之 間各疋義出一主動區’其中上述主動區包括一N型主動區 與一 P型主動區; 順應性形成一氮化物襯墊層,於各上述溝槽之側壁與 底部; ~ 實施一離子佈植於上述P型主動區兩側之上述氮化物 襯塾層内; 形成複數溝槽隔離物,以填滿各上述溝样· 形成一 N型通道電晶體於上述N型主動區I方;以及 1 第34頁 1222715 六、申請專利範圍 形成一 P型通道電晶體於上述P型主動區上方。 25·如申請專利範圍第24項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述溝槽隔離物係由一氧 化物所構成。 26·如申請專利範圍第24項所述之具應變通道之互補 式金氧半導體的製作方法,其中形成上述氮化物襯塾層之 前更包括:順應性形成一氧化物襯墊層於各上述氮化物襯 塾層與上述半導體基底之間。 2 7·如申請專利範圍第24項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述氮化物襯墊層係由氮 化矽所構成。 28·如申請專利範圍第24項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述離子佈植所施加的離 子包括:矽(Si)離子、氮(n)離子、氦(He)離子、氖(Ne)離 子、氬(Ar)、氙(Xe)或鍺離子。 2 9 ·如申請專利範圍第2 4項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述N型主動區之上述半 導體基底表層具有一拉伸應變通道區。 3 0 ·如申請專利範圍第2 9項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述拉伸應變通道區之拉 伸應變量大體為〇· 1%〜2%。 3 1 ·如申請專利範圍第2 4項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述P型主動區之上述半 導體基底表層具有一壓縮應變通道區。
〇503.9889TW(Nl);TSMC2003-0173;Felicia.ptd 第35 K 1222715 六、申請專利範圍 、32·如申請專利範圍第31項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述壓縮應變通道區之拉 伸應變量大體為〇· 1%〜2% 〇 33.如申請專利範圍第24項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述半導體基底包括:一 石夕基底、堆疊之一矽層與一矽鍺層或堆疊之一第一矽基 底、一埋入絕緣層與一第二矽基底。 34·如申請專利範圍第24項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述溝槽之厚度大體為 2000~6000A 。 、35·如申請專利範圍第24項所述之具應變通道之互補 式金氧半導體的製作方法,其中形成上述N型通道電晶體 f上述P型通道電晶體之後更包括:分別形成一應力膜,覆 蓋於上述N型通道電晶體與上述p型通道電晶體表面。 3 6 ·如申請專利範圍第2 4項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述應力膜係由化學氣相 >儿積法(chemical vapor deposition ;CVD)所形成。 37· —種具應變通道之互補式金氧半導體的製作方 法,包括: 提供一半導體基底; 形成複數溝槽於上述基底内,使得相鄰兩上述溝槽之 間各定義出一主動區,其中上述主動區包括一主動區 與一Ρ型主動區; 順應性形成一氮化物襯墊層,於上述Ν型主動區兩側
0503-9889TW(Ni);TSMC2003-0173;Felicia.ptd 第 36 頁 1222715 六、申請專利範圍 之各上述溝槽之側壁與底部; 形成複數溝槽隔離物,以填滿各上述溝槽; 形成一 N型通道電晶體於上述n型主動區上方;以及 形成一 P型通道電晶體於上述P型主動區上方。 、3 8 ·如申請專利範圍第3 7項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述溝槽隔離物係由一氧 化物所構成。 、3 9 ·如申請專利範圍第3 7項所述之具應變通道之互補 式金氧半導體的製作方法,其中形成上述氮化物襯墊層之 前更包括:順應性形成一氧化物襯墊層於各上述氮化物襯 塾層與上述半導體基底之間。 4 〇 ·如申請專利範圍第3 7項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述氮化物襯塾層係由氮 化矽所構成。 41 ·如申請專利範圍第3 7項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述N型主動區之上述半 導體基底表層具有一拉伸應變通道區。 42·如申請專利範圍第41項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述拉伸應變通道區之拉 伸應變量大體為0.1%〜2%。、 43·如申請專利範圍第37項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述P型主動區之上述半 導體基底表層具有一壓縮應變通道區。 44·如申請專利範圍第43項所述之具應變通道之互補
1222715 六、申請專利範圍 ^金氧半導體的製作方法,直中上述壓縮應變通道區之拉 伸應變量大體為〇.1%〜2%。 /、 4 5 ·、如申請專利範圍第3 7項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述半導體基底包括:一 矽基底、堆疊之一矽層與一矽鍺層或堆疊之一第一矽基 底、一埋入絕緣層與一第二矽基底。 、46·如申請專利範圍第37項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述溝槽之厚度大體為 2000-6000 A 〇 ’
4 7 ·如申請專利範圍第3 7項所述之具應變通道之互補 式金乳半導體的製作方法,其中形成上述N型通道電晶體 與上述P型通道電晶體之後更包括:分別形成一應力膜,覆 蓋於上述N型通道電晶體與上述p型通道電晶體表面。 4 8 ·如申請專利範圍第3 7項所述之具應變通道之互補 式金氧半導體的製作方法,其中上述應力膜係由化學氣相 沉積法(chemical vapor deposition ;CVD)所形成。
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- 2003-10-03 TW TW092127405A patent/TWI222715B/zh not_active IP Right Cessation
- 2003-10-17 CN CNB2003101019562A patent/CN1293637C/zh not_active Expired - Fee Related
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2004
- 2004-04-23 CN CNU2004200483776U patent/CN2751444Y/zh not_active Expired - Lifetime
- 2004-04-23 SG SG200402719A patent/SG115690A1/en unknown
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2005
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI782553B (zh) * | 2021-05-31 | 2022-11-01 | 力晶積成電子製造股份有限公司 | 半導體元件 |
Also Published As
Publication number | Publication date |
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US7052964B2 (en) | 2006-05-30 |
SG115690A1 (en) | 2005-10-28 |
CN1540757A (zh) | 2004-10-27 |
US6882025B2 (en) | 2005-04-19 |
CN1293637C (zh) | 2007-01-03 |
US20040212035A1 (en) | 2004-10-28 |
US20050156274A1 (en) | 2005-07-21 |
CN2751444Y (zh) | 2006-01-11 |
TW200423306A (en) | 2004-11-01 |
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