CN105321943B - 非平面器件和应变产生沟道电介质 - Google Patents

非平面器件和应变产生沟道电介质 Download PDF

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CN105321943B
CN105321943B CN201410784304.1A CN201410784304A CN105321943B CN 105321943 B CN105321943 B CN 105321943B CN 201410784304 A CN201410784304 A CN 201410784304A CN 105321943 B CN105321943 B CN 105321943B
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fin
fin structure
strain
substrate
layer
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CN105321943A (zh
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江国诚
冯家馨
吴志强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

本发明提供了一种具有设置在沟道区下面的应变产生结构的非平面电路器件。在示例性实施例中，集成电路器件包括衬底，第一鳍结构和第二鳍结构设置在衬底上。隔离部件沟槽限定在第一鳍结构和第二鳍结构之间。该电路器件还包括设置在隔离部件沟槽内的衬底的水平面上的应变部件。应变部件可以配置成对在第一鳍结构上形成的晶体管的沟道区产生应变。电路器件还包括设置在隔离部件沟槽内的应变部件上的填充电介质。在一些这种实施例中，应变部件还设置在第一鳍结构的垂直面上以及第二鳍结构的垂直面上。本发明还涉及非平面器件和应变产生沟道电介质。

Description

非平面器件和应变产生沟道电介质
技术领域
本发明涉及非平面器件和应变产生沟道电介质。
背景技术
在追求更高的器件密度、更高的性能和更低的成本中半导体产业已经发展进入纳米技术工艺节点。尽管材料和制造中的突破性进步，按比例缩放诸如传统的MOSFET的平面器件已证实具有挑战性。为了克服这些挑战，电路设计者们寻求新颖的结构以实现改进的性能。探究的一个途径是诸如鳍式场效应晶体管(FinFET)的三维设计的发展。FinFET可以认为是一种从衬底突出并且伸入栅极内的典型平面器件。利用从衬底向上延伸的薄“鳍”(或鳍结构)制造典型的FinFET。在该垂直鳍中形成FET的沟道，并且在鳍的沟道区的上方(例如，包裹)提供栅极。用栅极包裹鳍增加了沟道区和栅极之间的接触面积并且允许栅极从多侧控制沟道。这可以以多种途径平衡，并且在一些应用中，FinFET提供降低的短沟道效应，降低的泄露以及更高的电流。换句话说，它们可以比平面器件更快、更小和更有效。
然而，FinFET和其他非平面器件是发展中的技术，意味着在许多方面，还未实现它们的全部潜力。仅作为一个实例，已经在平面器件中使用沟道应变(内在化沟道区内的压力)以改进电荷载流子流动穿过沟道区。然而，在非平面器件中，已经证实产生沟道应变困难得多，并且当产生沟道应变时，已经证实很难获得期望的改进的载流子迁移率。因此，虽然用于在非平面器件内形成应变的沟道的传统技术在一些方面已经足够，但是它们在其他方面不令人满意。为了继续满足不断增加的设计需求，在该领域及其他领域需要进一步的进步。
发明内容
为了解决现有技术中的问题，本发明提供了一种集成电路器件，包括：衬底；第一鳍结构和第二鳍结构，所述第一鳍结构和所述第二鳍结构均设置在所述衬底上并且具有限定在所述第一鳍结构和所述第二鳍结构之间的隔离部件沟槽；应变部件，设置在所述隔离部件沟槽内的所述衬底的水平面上；以及填充电介质，设置在所述隔离部件沟槽内的所述应变部件上。
在上述集成电路器件中，其中，所述应变部件还设置在所述第一鳍结构的垂直面上以及所述第二鳍结构的垂直面上。
在上述集成电路器件中，其中，所述应变部件配置为在所述第一鳍结构上形成的晶体管的沟道区上产生应变。
在上述集成电路器件中，还包括设置在所述应变部件和所述填充电介质之间的衬垫。
在上述集成电路器件中，还包括设置在所述应变部件和所述填充电介质之间的衬垫；其中，所述衬垫与所述填充电介质的最顶面间隔开。
在上述集成电路器件中，还包括设置在所述应变部件和所述填充电介质之间的衬垫；其中，所述隔离部件沟槽内的隔离部件包括位于所述隔离部件的最顶面和所述衬垫的最顶面之间的介电材料。
在上述集成电路器件中，还包括第三鳍结构，所述第三鳍结构设置在所述衬底上并且具有设置在所述第三鳍结构上的p-沟道器件，其中，所述第三鳍结构具有设置在所述衬底上的第一层、设置在所述第一层上的第二层以及设置在所述第二层的至少三个表面上的第三层。
在上述集成电路器件中，还包括第三鳍结构，所述第三鳍结构设置在所述衬底上并且具有设置在所述第三鳍结构上的p-沟道器件，其中，所述第三鳍结构具有设置在所述衬底上的第一层、设置在所述第一层上的第二层以及设置在所述第二层的至少三个表面上的第三层；其中，所述第一层包括SiGe，其中，所述第二层包括元素Si，并且其中，所述第三层包括SiGe。
根据本发明的另一个方面，提供了一种半导体器件，包括：衬底；鳍，所述鳍从所述衬底垂直地延伸出，并且包括两个或多个源极/漏极区和设置在所述两个或多个源极/漏极区之间的沟道区；以及隔离部件，设置在与所述鳍相邻的所述衬底上，其中，所述隔离部件包括：衬垫，设置在所述鳍的侧面上和所述衬底的顶面上；以及填充材料，设置在所述衬垫上并且具有与所述衬底相对的最顶面，其中，所述衬垫远离所述填充材料的最顶面设置。
在上述半导体器件中，其中，所述衬垫包括SiN，并且其中，所述填充材料包括SiOx。
在上述半导体器件中，还包括应变部件，设置在所述鳍的所述侧面上，并且介于所述鳍的半导体材料和所述衬垫之间。
在上述半导体器件中，还包括应变部件，设置在所述鳍的所述侧面上，并且介于所述鳍的半导体材料和所述衬垫之间；其中，所述应变部件还设置在所述衬底的所述顶面上介于所述衬底的半导体材料和所述衬垫之间。
在上述半导体器件中，还包括应变部件，设置在所述鳍的所述侧面上，并且介于所述鳍的半导体材料和所述衬垫之间；其中，将所述应变部件配置成在所述鳍的所述沟道区中产生沟道应变。
在上述半导体器件中，还包括应变部件，设置在所述鳍的所述侧面上，并且介于所述鳍的半导体材料和所述衬垫之间；其中，将所述应变部件配置成在所述鳍的所述沟道区中产生沟道应变；其中，所述沟道应变是拉伸应变，其中，所述鳍包括在所述鳍上形成的n-沟道器件，以及其中，所述n-沟道器件包括所述沟道区和两个或多个所述源极/漏极区。
在上述半导体器件中，其中，所述鳍包括设置在所述衬底上的第一半导体层、设置在所述第一半导体层上的第二半导体层以及设置在所述第二半导体层的至少三个表面上的第三半导体层，并且其中，所述第二半导体层具有与所述第一半导体层和所述第三半导体层不同的组成。
根据本发明的又一个方面，提供了一种形成半导体器件的方法，所述方法包括：接收工件，所述工件具有在所述工件上形成的鳍结构，其中，所述鳍结构包括第一半导体部分和在组成上与所述第一半导体部分不同的第二半导体部分；在所述鳍结构的沟道区内的所述第一半导体部分上选择性地形成应变结构；在所述应变结构上形成隔离部件；在邻近所述沟道区的一对源极/漏极区中使所述第二半导体部分凹进；以及在所述一对源极/漏极区中的凹进的所述第二半导体部分上外延生长源极/漏极结构。
在上述方法中，其中，选择性地形成所述应变结构包括在暴露所述沟道区的所述鳍结构上形成硬掩模层。
在上述方法中，其中，选择性地形成所述应变结构包括在暴露所述沟道区的所述鳍结构上形成硬掩模层；其中，选择性地形成所述应变结构还包括氧化所述鳍结构的所述沟道区内的所述第一半导体部分以形成包括半导体氧化物的所述应变结构。
在上述方法中，其中，基于作为NMOS鳍结构的所述鳍结构实施在所述鳍结构的所述第一半导体部分上选择性地形成所述应变结构。
在上述方法中，其中，选择性地形成所述应变结构还包括沿着水平面形成所述应变结构的部分并且在所述鳍结构和另一鳍结构之间延伸。
附图说明
当结合附图进行阅读时，从下面详细的描述可以最佳地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1是根据本发明的各个方面的工件的一部分的透视图。
图2A和图2B是根据本发明的各个方面的用于在工件上制造鳍基器件的方法的流程图。
图3和图4是根据本发明的各个方面的经历用于形成鳍基器件的方法的工件的一部分的截面图。
图5A、图6A、图7A、图8A、图9A、图10A、图11A和图12A是根据本发明的各个方面的经历用于形成示出工件的沟道区的鳍基器件的方法的工件的一部分的截面图。
图5B、图6B、图7B、图8B、图9B、图10B、图11B和图12B是根据本发明的各个方面的经历用于形成示出工件的源极/漏极区的鳍基器件的方法的工件的一部分的截面图。
图13是根据本发明的各个方面的经历用于形成鳍基器件的方法的工件的一部分的透视图。
图14A、图15A、图16A和图17A是根据本发明的各个方面的经历用于形成示出工件的沟道区的鳍基器件的方法的工件的一部分的截面图。
图14B、图15B、图16B和图17B是根据本发明的各个方面的经历用于形成示出工件的源极/漏极区的鳍基器件的方法的工件的一部分的截面图。
具体实施方式
本发明大体上涉及IC器件制造以及，更具体地，涉及具有设置在STI沟槽内的鳍上并且向下延伸至衬底的应变产生部件的FinFET。
本发明提供了许多不同的实施例或实例，用以实现本发明的不同特征。以下描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不旨在限定。例如，以下描述中在第二部件上方或上形成第一部件可以包括第一和第二部件以直接接触形成的实施例，并且也可以包括其中在第一和第二部件之间形成额外的部件使得第一和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参照标号和/或字符。该重复是为了简明和清楚的目的，而且其本身没有规定所述各种实施例和/或结构之间的关系。
而且，为了便于描述，可以在本文中使用诸如“下面”、“在…之下”、“下部”、“在…之上”、“上部”等的空间相对术语以描述附如图所示的一个元件或部件与另一个(些)元件或部件的关系。除了附图中示出的方位之外，空间相对术语旨在包括器件在使用或操作中的不同方位。例如，如果翻转附图中的器件，描述为位于其他元件或部件“之下”或“下面”的元件则可以被定向成位于其他元件或部件“之上”。因此，示例性术语“之下”可以包括之上和之下两个方位。装置可以以其他方位定向(旋转90度或处于其他方位)并且本文使用的空间相对描述符可以同样地以作出相应的解释。
图1是根据本发明的各个方面的工件100的一部分的透视图。为了清楚和更好地说明本发明的构思简化了图1。额外的部件可以合并到工件100内，并且对于工件100的其他实施例，可以替换或删除以下描述的一些部件。
工件100包括衬底102或晶圆，衬底102或晶圆具有在其上形成的一个或多个鳍结构104。鳍结构104代表任何凸起的部件，并且虽然示出的实施例包括FinFET鳍结构104，但是进一步实施例也包括其他在衬底102上形成的凸起的有源器件和无源器件。示出的鳍结构104包括n-沟道(NMOS)FinFET 106和p-沟道(PMOS)FinFET 108。依次地，每个FinFET106和108包括一对相对的源极/漏极区110，其可以包括各种掺杂的半导体材料以及设置在源极/漏极区110之间的沟道区112。通过对邻近和外包沟道区112的栅极堆叠件114施加的电压控制载流子(对于n-沟道器件的电子和对于p-沟道器件的空穴)流动穿过沟道区112。将栅极堆叠件114示出为半透明的以更好地示出下面的沟道区112。在示出的实施例中，沟道区112升到衬底102的平面之上，在衬底102的该平面上形成沟道区112，并且因此，可以将鳍结构104称为“非平面”器件。凸起的沟道区112提供比可比较的平面器件更大的接近栅极堆叠件114的表面面积。这增强了栅极堆叠件114和沟道区112之间的电磁场相互作用，其可以降低与更小的器件的相关的泄露和短沟道效应。因此，在许多实施例中，FinFET 106和108以及其他非平面器件比它们的平面相对物在更小的占用空间(footprint)内实现更好的性能。
如以下更详细地描述，为了使相应的FinFET 106和108彼此电隔离，在鳍结构104之间的衬底102上形成隔离部件116。示例性隔离部件116包括在衬底102上形成的衬垫118以及在衬垫118上形成的填充材料120。隔离部件116也可以包括设置在填充材料120和衬底102之间的沟槽内的应变产生结构122。在图1的图解中，将填充材料120示出为部分去除以显露下面的衬垫118，并且将下面的衬垫118示出为部分去除以显露应变产生结构122。顾名思义，应变产生结构122对包括直接位于结构122之上的部分的鳍结构104的围绕部分产生应变。适当地配置，增加的应变改进载流子流动穿过这些应变部分。通常，沟道区112上的压缩应变改进PMOS器件的载流子迁移率，同时拉伸应变改进NMOS器件的载流子迁移率。因此，在一些实施例中，将应变产生结构122配置成提供拉伸应变并且只在NMOS FinFET 106的沟道区112的下面形成。
现参照图2A至图17B描述形成FinFET器件106和108以及应变产生结构122的示例性方法。下面的附图指的是穿过沟道区112(例如，沿着平面124)和/或穿过FinFET器件106和108的源极/漏极区110(例如，沿着平面126)截取的横截面。为了参照，在图1中示出这些横截面124和126。
图2A和2B是根据本发明的各个方面的用于在工件100上制造鳍基器件的方法200的流程图。应该理解，可以在方法200之前、期间和之后提供额外的步骤并且对于该方法的其他实施例可以替换或删除描述的一些步骤。图3和4是经历方法200的工件100的一部分的截面图，其中，穿过沟道区112(沿着平面124)截取截面。贯穿框202和204的相应工艺，源极/漏极区110和沟道区112经历基本上相似的工艺。为了避免不必要的重复，省略了表示沿着源极/漏极区110截取的截面的基本上相似的截面图。然而，对于随后的工艺，提供了沟道区112和源极/漏极区110截面。在这方面，图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A、图14A、图15A、图16A和图17A是根据本发明的各个方面的工件100的一部分的截面图，其中穿过沟道区112(沿着平面124)截取截面。图5B、6B、7B、8B、9B、10B、11B、12B、14B、15B、16B和17B是根据本发明的各个方面的工件100的一部分的截面图，其中穿过源极/漏极区110(沿着平面126)截取截面。图13是根据本发明的各个方面的经历方法200的工件100的一部分的透视图。为了清楚和更好地示出本发明的构思已经简化了图图3至图17B。
首先参照图2A的框202以及图3，接收包括衬底102的工件100。可以将衬底102分割成用于形成一个或多个NMOS FinFET的称为NMOS区302的第一区和用于形成一个或多个PMOS FinFET的称为PMOS区304的第二区。NMOS区302可以邻近PMOS区304或与PMOS区304分隔，并且在这些区之间可以形成包括沟槽隔离部件116和/或伪器件的多种隔离部件。在以下详细描述的实施例中，在NMOS区302和PMOS区304中形成FinFET。然而，应该理解，这些FinFET代表任何凸起的结构，并且进一步实施例包括在衬底102上形成的其他凸起的有源和无源器件。
在一些实施例中，衬底102可以包括两层或更多层，示出了衬底层306和308。适用于衬底层306和/或308的材料包括块状硅。可选地，衬底层306和308可以包括诸如晶体结构中的硅或锗的元素(单元素)半导体；诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；或它们的组合。衬底102还可以包括绝缘体上硅(SOI)结构。因此，衬底层306和/或308可以包括诸如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物和/或其他合适的绝缘体材料的绝缘体。使用注氧分离(SIMOX)、晶圆接合、和/或其他合适的方法制造SOI衬底。在示例性实施例中，第一衬底层306包括SiGe，而第二衬底层308包括元素Si(即，不具有Ge或其他半导体的掺杂或未掺杂的Si)。
衬底层306和308可以具有非均匀的组成。例如，在图3中，第一衬底层306包括组成上与底部312不同的顶部310。在实例中，底部312包括Ge浓度在约10原子百分比和约30原子百分比之间选择的SiGe，而顶部310包括Ge浓度大于底部312并且在约15原子百分比和约60原子百分比之间选择的SiGe。这些部分可以具有任何相关的厚度，并且在实例中，顶部310具有在约30nm和约100nm之间的厚度(由箭头314表示)并且底部312具有在约1μm和约3μm约之间的厚度(由箭头316表示)。衬底层306和308的组成可以用于调整由层306和308之间的界面产生的应变以及平衡相关器件的其他特性。例如，由于锗原子的存在，SiGe半导体晶体具有比元素Si半导体晶体更大的内在间距。SiGe中的Ge的浓度越大，相应的间距越大。部分由于该不同的间距，Si晶体结构和SiGe晶体结构之间的界面(诸如衬底层306和308之间的界面)可以用于产生在衬底102中和围绕结构中的内部应变。
可以看出，在NMOS区302和PMOS区304之间衬底层306和308的组成也可以不同。在之前的实施例中，在NMOS区302中第一衬底层306具有上述提及的不同的顶部310和底部312，而在PMOS区中第一衬底层306具有均匀的组成，其包括Ge浓度在约10原子百分比和约30原子百分比之间的SiGe。
为了有助于制造和避免对衬底层的损坏，可以在衬底102上形成一层或多层硬掩模层318。硬掩模层318可以包括诸如半导体氧化物、半导体氮化物、半导体氮氧化物和/或半导体碳化物的电介质，并且在示例性实施例中，硬掩模层318包括氧化硅层和氮化硅层。可以通过热生长、原子层沉积(ALD)、化学汽相沉积(CVD)、高密度等离子体CVD(HDP-CVD)、物理汽相沉积(PVD)和/或其他合适的沉积工艺形成硬掩模层318。
可以在硬掩模层318上形成光刻胶层320并且用光刻胶层320在方法200的随后步骤中限定鳍结构104。示例性光刻胶层320包括导致层在置于光中时经历性质改变的光敏材料。可以用该性质改变在称作为光刻图案化的工艺中选择性地去除光刻胶层的暴露或未暴露部分。
参照图2A的框204以及图4，蚀刻部分衬底102以限定鳍结构104。在一些实施例中，这包括图案化光刻胶层320的光刻技术。例如，在一个这种实施例中，光刻系统将光刻胶层320暴露于由掩模确定的具体图案中的辐射。经过或从掩模反射出的光撞击光刻胶层320从而将掩模上形成的图案转移至光刻胶320。在其他这种实施例中，使用直接写入或诸如激光图案化、电子束图案化和/或离子束图案化的无掩模光刻技术图案化光刻胶层320。一旦暴露，显影光刻胶层320，只剩下光刻胶的暴露部分，或在可选实施例中，只留下光刻胶的未暴露部分。示例性图案化工艺包括光刻胶层320的软烘、掩模对准、曝光、曝光后烘烤、显影光刻胶层320、冲洗和干燥(例如，硬烘)。
在图4的实施例中，图案化工艺只保留直接位于鳍结构104区域之上的光刻胶层320的那些部分。去除光刻胶层320的剩余部分以显露衬底102的打算被蚀刻的部分。因此，在图案化光刻胶320之后，可以对工件100实施一个或多个蚀刻工艺以打开硬掩模层318并且蚀刻未被光刻胶层320覆盖的衬底102和/或衬底层306和308的部分。该蚀刻工艺可以包括诸如干蚀刻、湿蚀刻、和/或其他蚀刻方法(例如，反应离子蚀刻(RIE))的任何合适的蚀刻技术。在一些实施例中，蚀刻包括利用不同的蚀刻化学物质的多个蚀刻步骤，每个步骤针对工件100的特定材料。例如，在一实施例中，通过使用基于氟的蚀刻剂的干蚀刻工艺蚀刻衬底102。
将蚀刻配置成产生在衬底102的剩余物之上延伸的具有任何合适的高度和宽度的鳍结构104。在示出的实施例中，该工艺蚀刻完全地穿过第二衬底层308并且穿过第一衬底层306的顶部310(在NMOS区302中)但是不蚀刻穿过NMOS区302中的第一衬底层的底部312。当然，这些深度仅仅是示例。除了限定鳍结构104，框204的蚀刻也可以限定鳍结构104之间的一个或多个隔离部件沟槽402。随后可以用介电材料填充沟槽402以形成诸如浅沟槽隔离部件(STI)的隔离部件116。在蚀刻之后，可以去除剩余的光刻胶层320和硬掩模层318。
参照图2A的框206以及图5A和图5B，在鳍结构104的上方形成第二硬掩模502。第二硬掩模502覆盖PMOS区304和NMOS区302的源极/漏极区110，但是暴露NMOS区302的沟道区112。这允许在NMOS器件的沟道区112的下面形成随后的应变产生结构122而不在其他位置形成。第二硬掩模502可以包括任何合适的介电材料，并且示例性第二硬掩模502包括半导体氮化物。为了只暴露NMOS沟道区112，可以横跨NMOS区302和PMOS区304的鳍结构104形成第二硬掩模502，然后选择性地蚀刻或否则从NMOS沟道区112去除。在一个这种实施例中，在区302和304上方已经沉积第二硬掩模502之后在第二硬掩模502上沉积光刻胶层。光刻图案化光刻胶层以暴露在NMOS沟道区112内设置的第二硬掩模502的部分用于蚀刻。然后，从NMOS沟道区112去除第二硬掩模502，并且可以剥离剩余的光刻胶。
参照图2A的框208以及图6A和图6B，在由第二硬掩模502暴露的衬底102的部分上形成介电材料以产生应变产生结构122。介电材料可以包括任何合适的电介质，并且在一些示例性实施例中包括半导体氧化物。因此，在一个这种实施例中，氧化NMOS区302的沟道区112内的第一衬底层306的暴露部分以形成应变产生结构122。氧化和其他电介质形成技术可以改变衬底102的晶格结构和/或间距并且可以用于对鳍结构104产生或解除应变。具体地，对于包含SiGe的第一衬底层306和包含元素Si的第二衬底层308，第一层306的选择氧化对鳍结构104的相邻区域施加拉伸应变。这可以使得鳍104更适合NMOS FinFET。由于该原因及其他原因，电介质形成工艺可以被第二硬掩模502局限于NMOS区302的沟道区112。在这些实施例中，在第一衬底层306的垂直表面上形成应变产生结构122并且也可以在鳍结构104之间的第一衬底层306的水平表面上形成。
可以使用任何合适的氧化工艺氧化衬底102，并且在示例性实施例中，使用湿氧化工艺，因为其趋向于选择性地氧化第一衬底层306内的Ge而不氧化第二衬底层308内的Si。例如，可以将工件100加热至并且保持在约400℃和约500℃之间同时在保持在约1Atm大气压的环境中对衬底102供应纯水(蒸汽)约30分钟至约1小时之间。氧化技术在NMOS区302的沟道区112中的隔离部件沟槽内形成SiGe氧化物应变产生结构122。在别处，第二硬掩模502防止第一衬底层306的氧化，从而使得在NMOS区302的源极/漏极区110或PMOS区304内的任何位置中不形成应变产生结构。应变产生结构122可以形成为任何合适的厚度，并且在各个示例性实施例中，垂直于衬底102的水平或垂直表面测量，应变产生结构122具有其最厚点在约3nm和约10nm之间的厚度。在形成应变产生结构122之后，可以去除第二硬掩模502。
参照图2A的框210以及图7A和图7B，可以在衬底102上，包括在鳍结构104和应变产生结构122上，形成衬垫118。衬垫118降低衬底102和介电填充材料之间的界面处的晶体缺陷并且衬垫118可以包括任何合适的材料，包括半导体氮化物、半导体氧化物、热半导体氧化物、半导体氮氧化物、聚合物电介质和/或其他合适的材料，并且可以使用包括热生长、ALD、CVD、HDP-CVD、PVD和/或其他合适的沉积工艺的任何合适的沉积工艺形成衬垫118。在一些实施例中，衬垫118包括通过热氧化工艺形成的传统热氧化物衬垫。在一些示例性实施例中，衬垫118包括通过HDP-CVD形成的半导体氮化物。
参照图2A的框212以及图8A和图8B，然后在隔离部件沟槽402内沉积STI填充材料120或填充电介质以进一步限定隔离部件116。合适的填充材料120包括半导体氧化物、半导体氮化物、半导体氮氧化物、FSG、低K介电材料和/或它们的组合。在各个示例性实施例中，使用HDP-CVD工艺、次常压CVD(SACVD)工艺、高纵横比工艺(HARP)和/或旋涂工艺沉积填充材料120。在一个这种实施例中，使用CVD工艺沉积包括介电填充材料120和液体或半液体状态的溶剂的可流动的介电材料。使用固化工艺去除溶剂，留下固体状态的介电填充材料120。
填充材料120的沉积之后可以是化学机械抛光/平坦化(CMP)工艺。在示出的实施例中，CMP工艺从鳍结构104完全去除衬垫118的最顶部，尽管在进一步实施例中，在CMP工艺之后衬垫118的部分保留在鳍结构104的顶部上。
参照图2A的框214以及图9A和图9B，在NMOS区302的上方形成第三硬掩模层902以允许选择性地加工PMOS区304。示例性第三硬掩模层902材料包括诸如半导体氧化物、半导体氮化物、半导体氮氧化物和/或半导体碳化物的电介质，并且在示例性实施例中，第三硬掩模层902包括氧化硅层和氮化硅层。可以通过热生长、ALD、化学汽相沉积(CVD)、高密度等离子体CVD(HDP-CVD)、物理汽相沉积(PVD)和/或其他合适的沉积工艺形成第三硬掩模层902。在一些实施例中，在NMOS区302和PMOS区304的上方沉积第三硬掩模层902然后从PMOS区304选择性地去除第三硬掩模层902。
参照图2A的框216并且仍然参照图9A和图9B，衬底102在PMOS区304中部分地凹进，而第三硬掩模层902保护在NMOS区302内的衬底102。可以使用任何合适的蚀刻技术以凹进PMOS区304中的第二衬底层308，包括干蚀刻、湿蚀刻、RIE和/或其他蚀刻方法，并且在示例性实施例中，利用含氟气体(例如，CF2)的干蚀刻技术选择性地蚀刻第二衬底层308而不蚀刻围绕的结构。在蚀刻之后，一些量的第二衬底层308可以保留，并且在各个实施例中，剩余的第二衬底层308具有在约5nm和约25nm之间的厚度。
框216中的凹进衬底102还可以包括凹进在PMOS区304中衬垫118的部分。通过凹进衬垫118，增加了可用于外延生长的第二衬底层308的表面积，从而在第二衬底层308和任何随后形成的层之间提供更好的接合。可以使用任何合适的蚀刻技术凹进衬垫118，包括干蚀刻、湿蚀刻、RIE和/或其他蚀刻方法，并且在示例性实施例中，利用HF的湿蚀刻技术选择性地蚀刻衬垫118而不蚀刻围绕的结构。可以比第二衬底层308更进一步地凹进衬垫118，并且在示出的实施例中，在蚀刻之后，衬垫118的顶面在第二衬底层308的顶面之下。
参照图2B的框218并且参照图10A和图10B，在PMOS区304中的第二衬底层308上形成第三衬底层1002。正如第一和第二衬底层，第三衬底层1002可以包括元素(单元素)半导体、化合物半导体、电介质或它们的组合。在各个示例性实施例中，第三衬底层1002包括具有在约45原子百分比和约100原子百分比之间的Ge浓度的SiGe。在进一步示例性实施例中，第三衬底层1002包括不具有Si的掺杂或未掺杂的Ge(即，元素Ge半导体)。可以通过包括外延生长、ALD、CVD和/或PVD的任何合适的技术沉积第三衬底层1002，并且第三衬底层1002可以形成为任何合适的厚度。在一些示例性实施例中，第三衬底层1002可以形成为在约20nm和约40nm之间的厚度。
在比第二衬底层308更进一步地凹进衬垫118的实施例中，可以在第二衬底层308的三个或更多个表面上(水平顶面和两个垂直侧面)沉积第三衬底层1002。该增加的接合面积可以降低在第二衬底层308和第三衬底层1002之间的界面处的空隙和其他界面缺陷的发生。第三衬底层1002的沉积之后可以进行CMP工艺以去除在填充电介质之上延伸的材料。在沉积第三衬底层1002之后，可以从NMOS区302去除第三硬掩模层902，并且这可以作为CMP工艺的一部分或通过另一合适的技术实施。
参照图2B的框220并且参照图11A和图11B，凹进填充材料120。在NMOS区内，凹进工艺也可以包括凹进衬垫118的一部分。在示出的实施例中，比填充材料120更进一步地凹进NMOS区302中的衬垫118从而使得NMOS区302中的衬垫118的顶面位于该区域中的填充材料120的顶面之下。通过调整蚀刻技术可以控制填充材料120的顶面和衬垫118的顶面之间的间隙，并且在各个实施例中，该间隙在约3nm和约10nm之间的范围内。可以使用任何合适的蚀刻技术凹进填充材料120和/或衬垫118，包括干蚀刻、湿蚀刻、RIE和/或其他蚀刻方法，并且在示例性实施例中，使用各向异性干蚀刻选择性地去除填充材料120而不蚀刻衬底层。
参照图2B的框222以及图12A和图12B，在鳍结构104和填充材料120上方形成介电层1202。介电层1202可以提供包括填充由NMOS区中的衬垫118的凹进留下的间隙的多种用途。介电层1202也可以用作伪栅极结构的一部分。在这方面，在源极/漏极部件1502的形成期间为了保护鳍结构104的沟道区112，可以在NMOS区302和/或PMOS区304的沟道区112的上方形成伪栅极。因此在实施例中，设置在沟道区112中的介电层1202的部分是伪栅极电介质。介电层1202可以包括诸如半导体氧化物、半导体氮化物、半导体碳化物、半导体氮氧化物、其他合适的材料和/或它们的组合的任何合适的介电材料，并且在示例性实施例中，包括与填充材料120相同的介电材料和组分。
参照图2B的框224以及图13，在介电层1202上形成诸如伪栅极层1304的伪栅极1302的剩余结构、伪栅极硬掩模层1306和/或栅极间隔件1308。更详细地，形成伪栅极1302可以包括沉积包含多晶硅或其他合适的材料的伪栅极层1304以及在光刻工艺中图案化层。之后，可以在伪栅极层1304上形成伪栅极硬掩模层1306并且伪栅极硬掩模层1306可以包括诸如半导体氧化物、半导体氮化物、半导体碳化物、半导体氮氧化物、其他合适的材料和/或它们的组合的任何合适的材料。
在一些实施例中，在伪栅极1302的每一侧上(在伪栅极1302的侧壁上)形成栅极间隔件1308或侧壁间隔件。栅极间隔件1308可以用于补偿随后形成的源极/漏极部件1502并且可以用于设计或改变源极/漏极结构(结)轮廓。栅极间隔件1308可以包括诸如半导体氧化物、半导体氮化物、半导体碳化物、半导体氮氧化物、其他合适的材料和/或它们的组合的任何合适的介电材料。
参照图2B的框226以及图14A和图14B，蚀刻介电层1202和源极/漏极区110内的一层或多层衬底层。关于介电层1202，为了控制和对准源极/漏极部件1502的外延生长，蚀刻技术可以保留在衬底层的顶面之上延伸的层1202的部分。这可以通过使用配置为蚀刻介电层1202的水平面快于垂直面的各向异性蚀刻技术来实现。关于衬底层，在NMOS区302中，蚀刻保留第二衬底层308的一部分余下用作用于外延生长工艺的晶种层。在PMOS区304中，蚀刻可以保留第三衬底层1002的一部分余下用作用于外延生长工艺的晶种层。在另一实施例中，蚀刻可以从PMOS区304的源极/漏极区110完全去除第三衬底层1002仍然保留第二衬底层308的一部分用作晶种层。蚀刻可以作为单蚀刻工艺或作为利用多种蚀刻剂和技术的多蚀刻工艺实施，而且在各个实施例中，蚀刻工艺包括干蚀刻(诸如前述提及的各向异性干蚀刻技术)、湿蚀刻、RIE和/或其他合适的蚀刻技术。
参照图2B的框228以及图15A和图15B，在衬底层(例如，NMOS区302中的第二衬底层308，PMOS区304中的第三衬底层1002等)上形成凸起的源极/漏极部件1502。伪栅极1302和/或栅极间隔件1308将源极/漏极部件1502限制于源极/漏极区110，并且介电层1202将源极/漏极部件限制于水平地在源极/漏极区110内。在许多实施例中，可以通过一种或多种外延或外延(epi)工艺形成源极/漏极部件1502，通过外延或外延(epi)工艺在鳍结构104上以晶体状态生长Si部件、SiGe部件和/或其他合适的部件。合适的外延工艺包括CVD沉积技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD)、分子束外延和/或其他合适的工艺。外延工艺可以使用气态和/或液态前体，其与鳍结构104的组分相互作用。
在外延工艺期间可以通过引入掺杂物质原位掺杂源极/漏极部件1502，掺杂物质包括：诸如硼或BF2的p-型掺杂剂；诸如磷或砷的n-型掺杂剂和/或包括它们的组合的其他合适的掺杂剂。如果不原位掺杂源极/漏极部件1502，则实施注入工艺(即，结注入工艺)以掺杂源极/漏极部件1502。在示例性实施例中，NMOS区302中的源极/漏极部件1502包括SiP，而PMOS区304中的那些源极/漏极部件1502包括GeSnB(锡可以用于调整晶格常数)和/或SiGeSnB。可以实施一种或多种退火工艺以活化源极/漏极部件1502。合适的退火工艺包括快速热退火(RTA)和/或激光退火工艺。
参照图2B的框230以及图16A和图16B，在源极/漏极区110中的源极/漏极部件1502上形成层间电介质(ILD)1602。ILD 1602可以包围伪栅极1302和/或栅极间隔件1308从而允许去除这些部件并且在产生的空腔中形成替换栅极114。因此，在这些实施例中，如图16A所示在沉积ILD 1602之后去除伪栅极1302。ILD 1602也可以是电互连工件的器件(包括FinFET器件106和108)的电互连结构的一部分。在这些实施例中，ILD 1602用作支持并且隔离导电迹线的绝缘体。ILD 1602可以包括任何合适的介电材料，诸如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、其他合适的材料和/或它们的组合。
参照图2B的框232以及图17A和17B，在工件100上形成栅极堆叠件114，包裹鳍结构104的沟道区112。尽管应该理解栅极堆叠件114可以是任何合适的栅极结构，在一些实施例中，栅极堆叠件114是包括界面层1702、栅极介电层1704和金属栅极层1706(其各自可以包括一些子层)的高k金属栅极。
在一个这种实施例中，通过诸如ALD、CVD、臭氧氧化等的合适的方法沉积界面层1702。界面层1702可以包括氧化物、HfSiO、氮化物、氮氧化物和/或其他合适的材料。接下来，通过诸如ALD、CVD、金属有机CVD(MOCVD)、PVD、热氧化、它们的组合和/或其他合适的技术的合适的技术在界面层1702上沉积高k栅极介电层1704。高k介电层可以包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba，Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)或其他合适的材料。
然后，通过ALD、PVD、CVD或其他合适的工艺形成金属栅极层1706，并且金属栅极层1706可以包括诸如金属层、衬垫层、润湿层和/或粘附层的单层或多层。金属栅极层1706可以包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W或任何合适的材料。在一些实施例中，不同的金属栅极材料用于nMOS和pMOS器件。可以实施CMP工艺以产生栅极堆叠件114的基本上平坦的顶面。在栅极堆叠件114形成之后，可以提供工件100以用于进一步的制造，诸如接触件形成和互连结构的进一步制造。
因此，本发明提供了一种通过在沟道区下面形成应变产生结构来提高非平面半导体器件的沟道应变的技术。在一些实施例中，提供了一种集成电路器件。该集成电路器件包括衬底和第一鳍结构和第二鳍结构，每个第一鳍结构和第二鳍结构均设置在衬底上。衬底具有限定在第一鳍结构和第二鳍结构之间的隔离部件沟槽。该集成电路器件还包括设置在隔离部件沟槽内的衬底的水平面上的应变部件以及设置在隔离部件沟槽内的应变部件上的填充电介质。在一些这种实施例中，应变部件还设置在第一鳍结构的垂直面上以及第二鳍结构的垂直面上。在一些这种实施例中，应变部件配置成对在第一鳍结构上形成的晶体管的沟道区产生应变。在一些这种实施例中，该集成电路器件还包括第三鳍结构，第三鳍结构设置在衬底上并且具有在第三鳍结构上设置的p-沟道器件。第三鳍结构具有设置在衬底上的第一层，设置在第一层上的第二层以及设置在第二层的至少三个表面上的第三层。
在进一步实施例中，提供了一种半导体器件，包括衬底和从衬底垂直地延伸的鳍。该鳍包括两个或更多个源极/漏极区和设置在两个或更多个源极/漏极区之间的沟道区。该半导体器件还包括设置在与鳍相邻的衬底上的隔离部件，该隔离部件包括设置在鳍的侧面上和衬底的顶面上的衬垫以及设置在衬垫上的填充材料。填充材料具有与衬底相对的最顶面，从而使得衬垫远离填充材料的最顶面设置。在一些这种实施例中，半导体器件还包括应变部件，设置在鳍的侧面上介于鳍的半导体材料和衬垫之间。在一些这种实施例中，鳍包括设置在衬底上的第一半导体层，设置在第一半导体层上的第二半导体层以及在设置第二半导体层的至少三个表面上的第三半导体层。第二半导体层具有与第一半导体层和第三半导体层不同的组成。
在又一实施例中，提供了一种形成半导体器件的方法。该方法包括接收工件，该工件具有在工件上形成的鳍结构，其中，鳍结构包括第一半导体部分和在组成上与第一半导体部分不同的第二半导体部分。在鳍结构的沟道区内的第一半导体部分上选择性地形成应变结构。在应变结构上形成隔离部件。在邻近沟道区的一对源极/漏极区中凹进第二半导体部分。在一对源极/漏极区中的凹进的第二半导体部分上外延生长源极/漏极结构。在一些这种实施例中，选择性地形成应变结构还包括氧化鳍结构的沟道区内的第一半导体部分以形成包括半导体氧化物的应变结构。
上面论述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于达到与本文所介绍实施例相同的目的和/或实现相同优点的其他处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (17)

1.一种集成电路器件，包括：
衬底；
第一鳍结构和第二鳍结构，所述第一鳍结构和所述第二鳍结构均设置在所述衬底上并且具有限定在所述第一鳍结构和所述第二鳍结构之间的隔离部件沟槽，其中，所述第一鳍结构和所述第二鳍结构均包括设置在所述衬底上的下部和设置在所述下部上的上部，其中，所述下部具有与所述上部不同的半导体材料；
应变部件，设置在所述隔离部件沟槽内的所述衬底的水平面上，并且设置在所述第一鳍结构和第二鳍结构的下部的垂直表面上，而不设置在所述第一鳍结构和所述第二鳍结构的上部的垂直表面上；以及
填充电介质，设置在所述隔离部件沟槽内的所述应变部件上。
2.根据权利要求1所述的集成电路器件，其中，所述应变部件配置为在所述第一鳍结构上形成的晶体管的沟道区上产生应变。
3.根据权利要求1所述的集成电路器件，还包括设置在所述应变部件和所述填充电介质之间的衬垫。
4.根据权利要求3所述的集成电路器件，其中，所述衬垫与所述填充电介质的最顶面间隔开。
5.根据权利要求3所述的集成电路器件，其中，所述隔离部件沟槽内的隔离部件包括位于所述隔离部件的最顶面和所述衬垫的最顶面之间的介电材料。
6.根据权利要求1所述的集成电路器件，还包括第三鳍结构，所述第三鳍结构设置在所述衬底上并且具有设置在所述第三鳍结构上的p-沟道器件，其中，所述第三鳍结构具有设置在所述衬底上的第一层、设置在所述第一层上的第二层以及设置在所述第二层的至少三个表面上的第三层。
7.根据权利要求6所述的集成电路器件，其中，所述第一层包括SiGe，其中，所述第二层包括元素Si，并且其中，所述第三层包括SiGe。
8.一种半导体器件，包括：
衬底；
鳍，所述鳍从所述衬底垂直地延伸出，并且包括两个或多个源极/漏极区和设置在所述两个或多个源极/漏极区之间的沟道区，其中，所述鳍包括设置在所述衬底上的下部和设置在所述下部上的上部，其中，所述下部具有与所述上部不同的半导体材料；
隔离部件，设置在与所述鳍相邻的所述衬底上，其中，所述隔离部件包括：
衬垫，设置在所述鳍的侧面上和所述衬底的顶面上；以及
填充材料，设置在所述衬垫上并且具有与所述衬底相对的最顶面，其中，所述衬垫远离所述填充材料的最顶面设置；以及
应变部件，介于所述鳍的半导体材料和所述衬垫之间，并且设置在所述鳍的下部的垂直表面上，而不设置在所述鳍的上部的垂直表面上。
9.根据权利要求8所述的半导体器件，其中，所述衬垫包括SiN，并且其中，所述填充材料包括SiOx。
10.根据权利要求8所述的半导体器件，其中，所述应变部件还设置在所述衬底的所述顶面上介于所述衬底的半导体材料和所述衬垫之间。
11.根据权利要求8所述的半导体器件，其中，将所述应变部件配置成在所述鳍的所述沟道区中产生沟道应变。
12.根据权利要求11所述的半导体器件，
其中，所述沟道应变是拉伸应变，
其中，所述鳍包括在所述鳍上形成的n-沟道器件，以及
其中，所述n-沟道器件包括所述沟道区和两个或多个所述源极/漏极区。
13.一种形成半导体器件的方法，所述方法包括：
接收工件，所述工件具有在所述工件上形成的鳍结构，其中，所述鳍结构包括第一半导体部分和在组成上与所述第一半导体部分不同的第二半导体部分，所述第二半导体部分在所述第一半导体部分上方；
在所述鳍结构的沟道区内的所述第一半导体部分上选择性地形成应变结构，其中，所述应变结构设置在所述第一半导体部分的垂直表面上，而不设置在所述第二半导体部分的垂直表面上；
在所述应变结构上形成隔离部件；
在邻近所述沟道区的一对源极/漏极区中使所述第二半导体部分凹进；以及
在所述一对源极/漏极区中的凹进的所述第二半导体部分上外延生长源极/漏极结构。
14.根据权利要求13所述的方法，其中，选择性地形成所述应变结构包括在暴露所述沟道区的所述鳍结构上形成硬掩模层。
15.根据权利要求14所述的方法，其中，选择性地形成所述应变结构还包括氧化所述鳍结构的所述沟道区内的所述第一半导体部分以形成包括半导体氧化物的所述应变结构。
16.根据权利要求13所述的方法，其中，基于作为NMOS鳍结构的所述鳍结构实施在所述鳍结构的所述第一半导体部分上选择性地形成所述应变结构。
17.根据权利要求13所述的方法，其中，选择性地形成所述应变结构还包括沿着水平面形成所述应变结构的部分并且在所述鳍结构和另一鳍结构之间延伸。
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