CN107026086A - 增强的沟道应变以减小nmos fet器件的接触电阻 - Google Patents

增强的沟道应变以减小nmos fet器件的接触电阻 Download PDF

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Publication number
CN107026086A
CN107026086A CN201610824116.6A CN201610824116A CN107026086A CN 107026086 A CN107026086 A CN 107026086A CN 201610824116 A CN201610824116 A CN 201610824116A CN 107026086 A CN107026086 A CN 107026086A
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fin structure
fin
strain gauge
area
gauge material
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林育樟
聂俊峰
张惠政
陈豪育
卢永晏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体器件包括衬底、鳍结构和在衬底上形成并且邻近于鳍结构的隔离层。该半导体器件包括在鳍结构和隔离层的至少部分上形成的栅极结构。该半导体器件包括外延层，该外延层包括对鳍结构的沟道区域提供应力的应变材料。该外延层具有第一区域和第二区域，其中，第一区域具有第一掺杂剂的第一掺杂浓度并且第二区域具有第二掺杂剂的第二掺杂浓度。第一掺杂浓度大于第二掺杂浓度。使用磷二聚体的离子注入掺杂外延层。本发明的实施例还涉及增强的沟道应变以减小NMOS FET器件的接触电阻。

Description

增强的沟道应变以减小NMOS FET器件的接触电阻
技术领域
本发明涉及半导体集成电路，更具体地涉及具有鳍式场效应晶体管(Fin FET)结构的半导体器件及其制造工艺。
背景技术
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米技术工艺节点，来自制造和设计问题的挑战已经引起了诸如Fin FET的三维设计的发展。Fin FET器件是多栅极结构类型，通常包括具有高高宽比的半导体鳍，并且在该半导体鳍中形成半导体晶体管器件的沟道和源极/漏极区域。在鳍结构上方以及沿着鳍结构的侧面(例如，包裹)形成栅极，利用沟道和源极/漏极区域的增大的表面积的优势，以产生更快，更可靠和更易控制的半导体晶体管器件。在一些器件中，例如，Fin FET器件的源极/漏极区域中的应变材料利用磷掺杂的含硅外延层。
发明内容
本发明的实施例提供了一种制造鳍式场效应晶体管(Fin FET)器件的方法，所述方法包括：提供具有第一鳍结构和第二鳍结构的衬底；在所述衬底上形成隔离层，所述隔离层形成为邻近于所述第一鳍结构和所述第二鳍结构；在所述第一鳍结构和所述隔离层的至少部分上形成第一栅极结构；在所述第二鳍结构和所述隔离层的至少部分上形成第二栅极结构；通过外延生长操作形成第一应变材料，所述第一应变材料向所述第一鳍结构的沟道区域提供应力；通过外延生长操作形成第二应变材料，所述第二应变材料向所述第二鳍结构的沟道区域提供应力；对所述第一应变材料的至少第一区域注入磷二聚体掺杂剂，所述第一区域具有所述磷二聚体掺杂剂的第一掺杂浓度，所述第一掺杂浓度大于所述第一应变材料的第二区域中的磷掺杂剂的第二掺杂浓度；以及对至少所述第一鳍结构和所述第一应变材料施加热退火操作，通过至少所述热退火操作，所述第一鳍结构的所述沟道区域比所述第二鳍结构的所述沟道区域具有更大的沟道迁移率。
本发明的另一实施例提供了一种制造鳍式场效应晶体管(Fin FET)器件的方法，所述方法包括：提供具有鳍结构的衬底；在所述衬底上形成隔离层，所述隔离层形成为邻近于所述鳍结构；在所述鳍结构和所述隔离层的至少部分上形成栅极结构；通过外延生长操作形成应变材料，所述应变材料向所述鳍结构的沟道区域提供应力；对所述应变材料的至少第一区域注入第一类型的磷掺杂剂，所述第一区域具有所述第一类型的磷掺杂剂的第一掺杂浓度，所述第一掺杂浓度大于所述应变材料的第二区域中的第二类型的磷掺杂剂的第二掺杂浓度；以及对至少所述鳍结构和所述应变材料施加热退火操作，通过至少所述热退火操作，所述鳍结构的所述沟道区域比位于所述衬底上的第二鳍结构的沟道区域具有更大的沟道迁移率。
本发明的又一实施例提供了一种半导体器件，包括：衬底；第一鳍结构；第二鳍结构；隔离层，形成在所述衬底上，所述隔离层形成为邻近于所述第一鳍结构和所述第二鳍结构；第一栅极结构，形成在所述第一鳍结构和所述隔离层的至少部分上；第二栅极结构，形成在所述第二鳍结构和所述隔离层的至少部分上；第一外延层，包括对所述第一鳍结构的沟道区域提供应力的第一应变材料；以及第二外延层，包括对所述第二鳍结构的沟道区域提供应力的第二应变材料，所述第二外延层具有第一区域和第二区域，所述第一区域比所述第二区域更接近于所述第二外延层的表面，所述第一区域具有第一掺杂剂的第一掺杂浓度并且所述第二区域具有第二掺杂剂的第二掺杂浓度，所述第一掺杂浓度大于所述第二掺杂浓度。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该理解，以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据本发明的一些实施例的鳍式场效应晶体管(Fin FET)器件的示例性立体图。
图2是根据本发明的一些实施例的沿着栅电极具有鳍结构的Fin FET器件的示例性截面图。
图3至图19是根据本发明的一些实施例的Fin FET结构的顺序的制造工艺中的中间阶段的截面图的实例。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。此外，术语“由…制成”可以意味着“包括”或“由…组成”。
图1是根据本发明的一个实施例的具有鳍结构的鳍式场效应晶体管(Fin FET)器件100的示例性立体图，并且图2是根据本发明的一些实施例的沿着栅电极的具有鳍结构的Fin FET器件100的示例性截面图。在这些图中，为了简便的目的，省略了一些层/部件。
除了其它部件之外，图1和图2中描述的Fin FET器件100包括衬底110、鳍结构120、栅极介电层130和栅电极140。在这个实施例中，衬底110是硅衬底。可选地，衬底110可以包括诸如锗的另一元素半导体；包括诸如SiC和SiGe的IV-IV化合物半导体、诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的III-V化合物半导体的化合物半导体；或它们的组合。在一个实施例中，衬底110是SOI(绝缘体上硅)衬底的硅层。当使用SOI衬底时，鳍结构120可以突出于SOI衬底的硅层或突出于SOI衬底的绝缘层。在后一种情况中，SOI衬底的硅层用于形成鳍结构120。诸如非晶Si或非晶SiC的非晶衬底或诸如氧化硅的绝缘材料可以用作衬底110。衬底110可以包括已经合适地掺杂有杂质(例如，p-型或n-型电导率)的各个区域。
鳍结构120设置在衬底110上方。鳍结构120可以由与衬底110相同的材料制成并且可以连续地从衬底110延伸。在这个实施例中，鳍结构120由硅(Si)制成。鳍结构120的硅层可以是固有的或适当地掺杂有n-型杂质或p-型杂质。
在图1中，一个鳍结构120设置在衬底110上方，而在图2中，三个鳍结构120设置在衬底110上方。然而，鳍结构的数量不限于一个或三个。该数量可以是两个或四个或更多。此外，一个或多个伪鳍结构可以设置为与鳍结构120的两侧接触以改进图案化工艺中的图案保真度。在一些实施例中，鳍结构120的宽度W在从约5nm至约40nm的范围内，并且在某些实施例中，在从约7nm至约12nm的范围内。在一些实施例中，鳍结构120的高度H在从约10nm至约100nm的范围内，并且在某些实施例中，在从约50nm至约100nm的范围内。
在图2中，位于鳍结构120之间的间隔和/或位于在衬底110上方形成的一个鳍结构和另一个元件之间的间隔由包括一层或多层的绝缘材料的隔离绝缘层(例如，隔离区域150)填充。用于隔离区域150的绝缘材料可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、氟掺杂的硅酸盐玻璃(FSG)或低k介电材料的一层或多层。
如图2所示，位于栅电极140下方的鳍结构120的下部称为阱区域120A，并且鳍结构120的上部称为沟道区域120B。在栅电极140下方，阱区域120A嵌入在隔离区域150内，并且沟道区域120B突出于隔离结构150。沟道区域120B的下部也可以嵌入在隔离区域150内约1nm至约5nm的深度。
突出于隔离区域150的沟道区域120B由栅极介电层130覆盖，并且栅极介电层130进一步由栅电极140覆盖。未由栅电极140覆盖的部分沟道区域120B起Fin FET器件100的源极/漏极(见图1)的作用。
在某些实施例中，栅极介电层130包括单层或可选地多层结构，具有诸如氧化硅、氮化硅或高k介电材料、其它合适的介电材料和/或它们的组合的单层或两个或更多的这些材料的多层的一种或多种介电材料。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其它合适的高k介电材料和/或它们的组合。
栅电极140包括诸如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其它合适的材料和/或它们的组合的一层或多层的任何合适的材料。可以使用后栅极方法或置换栅极方法形成栅极结构。
在本发明的某些实施例中，一个或多个功函调整层160插入在栅极介电层130和栅电极140之间。功函调整层160可以包括单层或可选地多层结构，诸如具有选择的功函数以增强器件性能的金属层(功函金属层)、衬垫层、润湿层、粘合层、金属合金或金属硅化物的各个组合。功函调整层160可以由诸如Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其它合适的金属材料的单层或两种或多种这些材料的多层的一种或多种导电材料制成。在一些实施例中，功函调整层160可以包括用于n-沟道FinFET的第一金属材料和用于p-沟道Fin FET的第二金属材料。例如，用于n-沟道Fin FET的第一金属材料可以包括具有与衬底导带的功函数基本匹配的或至少与沟道区域120B的导带的功函数基本匹配的功函数的金属。类似地，例如，用于p-沟道Fin FET的第二金属材料可以包括具有与衬底价带的功函数基本匹配的或至少与沟道区域120B的价带的功函数基本匹配的功函数的金属。在一些实施例中，功函调整层160可以可选择地包括多晶硅层。可以通过ALD、PVD、CVD、电子束蒸发或其它合适的工艺形成功函调整层160。此外，可以使用不同的金属层形成的功函调整层160分别用于n-沟道Fin FET和p-沟道Fin FET。
同样通过在源极和漏极区域125中适当地掺杂杂质在未由栅电极140覆盖的鳍结构120的上部形成源极和漏极区域125。可以在源极和漏极区域125上形成Si或Ge和诸如Co、Ni、W、Ti或Ta的金属的合金。在一些方面，例如，在源极和漏极区域125中的应变材料利用磷掺杂的含硅外延层。
通常实施离子注入用于形成源极和漏极区域125。例如，N-型源极/漏极工艺包括提供为形成磷掺杂的含硅外延层的室温磷离子注入。在NMOS Fin FET结构(例如，n-型源极/漏极区域)中，沟道迁移率受到离子注入之后形成的寄生电容的不利影响。一种方法是减小寄生电容，用相对高浓度的单原子磷(例如，在1x1021原子/立方厘米以上)实施磷离子注入。虽然更高的浓度可以生产更高的掺杂，但是由于一些磷原子可以局部团簇(例如，形成Si3P4化合物)并且用作应力源，因此离子注入引起更低的掺杂剂活化。为了克服更低的活化，另一个方法包括高温退火以活化掺杂剂并且可能解决由离子注入引起的损害。然而，用于热退火的温度的升高引起沟道区域120B中的不期望的应变损失。
本发明通过在磷掺杂的含硅外延层的顶面上提供相对较重和浅的掺杂提供了减小的接触电容的和增加的NMOS Fin FET的沟道迁移率。特别地，在外延生长操作之后，利用磷二聚体(P2 +)离子注入以在相同的注入能量下比传统的磷离子注入有效地结合更高的化学磷浓度并且引起更高的非晶水平。磷二聚体离子注入可以是或可以部分是在约-20℃温度以下的冷注入以引起更高的非晶水平(或更低的活化能)。
图3至图19示出了根据本发明的一些实施例的Fin FET器件300的顺序的制造中的中间阶段的截面图的实例。可能不是所有描述的组件都是需要的，然而，一种多种实施可以包括未显示在图中的额外的组件。在不背离此处规定所要求的范围的情况下，可以改变组件的布置和类型。可以提供额外的工艺、操作、材料、组件、不同的组件或较少的组件。此外，可以改变操作的顺序。
图3是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的具有衬底110的Fin FET器件300的截面图。在这个实施例中，衬底110包括晶体硅衬底(例如，晶圆)。根据设计需求，可以使用p-型衬底或n-型衬底并且衬底110可以包括各个掺杂区域。在一些实施例中，掺杂区域可以掺杂有p-型或n-型掺杂剂。例如，掺杂区域可以掺杂有诸如硼或BF2的p-型掺杂剂；诸如磷或砷的n-型掺杂剂；和/或它们的组合。掺杂区域可以配置为用于n-型Fin FET或可选地配置为用于p-型Fin FET。
在一些可选实施例中，衬底110可以由诸如金刚石或锗的一些其它合适的元素半导体；诸如砷化镓、碳化硅、砷化铟或磷化铟的合适的化合物半导体；或诸如碳化硅锗、磷砷化镓或磷化镓铟的合适的合金半导体制成。同样可选地，该衬底可以包括外延层。例如，该衬底可以具有位于块状半导体上面的外延层。此外，该衬底可以是应变的以增强性能。例如，外延层可以包括与块状半导体不同的半导体材料(诸如位于块状硅上面的硅锗层或位于块状硅锗上面的硅层)。这种应变的衬底可以通过选择性外延生长(SEG)形成。此外，该衬底可以包括SOI衬底。同样可选地，该衬底可以包括诸如埋氧(BOX)层，诸如通过注氧隔离(SIMOX)技术、晶圆接合、SEG、或其它适当的操作形成的掩埋介电层。
在一个实施例中，在半导体衬底110上形成垫层304a和掩模层304b。例如，垫层304a可以是使用热氧化操作形成的具有氧化硅的薄膜。垫层304a可以用作半导体衬底110和掩模层304b之间的粘合层。垫层304a也可以用作蚀刻掩模层304b的蚀刻停止层。在至少一个实施例中，例如，使用低压化学汽相沉积(LPCVD)或等离子体增强化学汽相沉积(PECVD)由氮化硅形成掩模层304b。掩模层304b在随后的图案化操作期间用作硬掩模。光刻胶层306形成在掩模层304b上并且之后通过光刻图案化操作图案化、在光刻胶层306中形成开口。在掩模层304b和垫层304a的图案化之后以及沟槽蚀刻之前可以去除光刻胶层。
光刻图案化操作可以包括光刻胶涂布(例如，旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、显影光刻胶、清洗、干燥(例如，硬烘烤)、其它合适的操作或它们的组合。可选地，光刻图案化操作可以由诸如无掩模光刻、电子束书写、直写和/或离子束书写的其它适当的方法实现或替换。光刻图案化工艺产生了在沟槽蚀刻操作期间用作掩模的光刻胶层。
图4是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的Fin FET器件300的截面图。蚀刻掩模层304b和垫层304a以暴露下面的半导体衬底110。之后，沟槽蚀刻暴露的半导体衬底110以通过使用图案化的掩模层304b和垫层304a作为掩模形成沟槽310。
在沟槽蚀刻操作中，衬底110可以通过包括干蚀刻、湿蚀刻或干蚀刻和湿蚀刻的组合的各种方法蚀刻。干蚀刻操作可以采用含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C4F8)、含氯气体(例如，C12、CHCl3、CC14、和/或BC13)、含溴气体(例如，HBr和/或CHBr3)、含氧气体、含碘气体、其它合适的气体和/或等离子体或它们的组合。
下一步，可以实施湿蚀刻操作以去除半导体衬底110的原生氧化物。可以使用稀释的氢氟(DHF)酸实施清洗。位于沟槽310之间的部分半导体衬底110形成半导体鳍120。鳍120可以布置为彼此平行的列(从Fin FET器件300的顶部看)，并且相对于彼此紧密间隔开。每个鳍120均具有宽度W和深度D，并且通过沟槽310的宽度S与邻近的鳍间隔开。例如，在一些实施例中，半导体鳍120的宽度W可以在从约3nm至约30nm的范围内。
图5是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的Fin FET器件300的截面图。沟槽310填充有一层或多层的介电材料314。介电材料314可以包括氧化硅。在一个或多个实施中，例如，介电材料314由通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD形成的二氧化硅制成。在可流动CVD中，沉积可流动介电材料，而不是氧化硅。顾名思义，可流动介电材料在沉积期间可以“流动”以填充具有高高宽比的间隙或间隔。通常，各种化学物质添加至含硅前体以允许沉积的膜流动。在一些实施例中，添加氮氢键。可流动介电前体(特别地，可流动氧化硅前体)的实例包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢-聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或甲硅烷基胺(诸如三甲硅烷基胺(TSA))。这些可流动氧化硅材料在多个操作工艺中形成。在沉积可流动膜之后，将可流动膜固化并且之后使可流动膜退火以去除不期望的元素以形成氧化硅。当去除不期望的元素时，可流动膜致密和收缩。在一些实施例中，实施多个退火工艺。之后，固化和退火可流动膜。
在一些实施例中，诸如氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)或低k介电材料的其它介电材料也可以用于形成介电材料314。在实施例中，使用高密度等离子体(HDP)CVD操作，使用硅烷(SiH4)和氧气(O2)作为反应前体形成介电材料314。在其它实施例中，可以使用次大气压CVD(SACVD)操作或高高宽比工艺(HARP)形成介电材料314，其中，工艺气体可以包括正硅酸乙酯(TEOS)和/或臭氧(O3)。在又一其它实施例中，可以使用诸如氢倍半硅氧烷(HSQ)或甲基倍半硅氧烷(MSQ)的旋涂电介质(SOD)操作形成介电材料314。在一些实施例中，填充的凹槽区域(或沟槽310)可以具有诸如用氮化硅或氧化硅填充的热氧化物垫层的多层结构。
图6是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的Fin FET器件300的截面图。在介电材料314的沉积之后，之后实施化学机械抛光(CMP)和/或回蚀刻操作和随后的掩模层304b和垫层304a的去除。在用介电材料314填充沟槽310之后，可以实施退火操作。退火操作包括快速热退火(RTA)、激光退火操作或其它合适的退火操作。
在至少一个实施例中，掩模层304b由氮化硅形成，从而使得使用H3PO4的湿蚀刻操作去除掩模层304b。如果垫层304a由氧化硅形成，则可以使用稀释的HF酸去除垫层304a。沟槽310中的介电材料314的剩余部分在下文中称为隔离区域150。在一些实施例中，在隔离区域150的凹进之后，实施掩模层304b和垫层304a的去除，其中，凹进操作如图7所示。
图7是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的Fin FET器件300的截面图。可以实施蚀刻操作以蚀刻隔离区域150以从隔离区域150暴露半导体鳍120的上部322。蚀刻操作可以包括干蚀刻操作、湿蚀刻操作或干蚀刻操作和湿蚀刻操作的组合以去除部分隔离区域150。应该理解，蚀刻操作可以实施为一个蚀刻操作或多个蚀刻操作。
剩余的隔离区域150包括顶面317。此外，因此，突出于剩余的隔离区域150的顶面317上方的半导体鳍120的上部322用于形成Fin FET器件300的有源区(诸如沟道区域)。半导体鳍120的上部322可以包括顶面323和侧壁324。从隔离区域150的顶面317的半导体鳍120的上部322的高度H可以在从约6nm至约300nm的范围内。在一些实施例中，该高度H大于300nm或小于6nm。为简单起见，位于邻近的隔离区域150之间的半导体鳍120的上部322在下文中称为沟道区域以说明半导体鳍120的每个上部，其中，隔离区域150的顶面317低于半导体鳍120的顶面323。
图8是根据所提供技术的实施例的处于顺序的制造工艺的各个阶段的一个的n-型Fin FET器件802和p-型Fin FET器件804的截面图。栅极堆叠件320形成在半导体鳍120的顶面323和侧壁324上方，延伸至第一隔离区域150a和第二隔离区域150b的顶面317。栅极堆叠件320包括栅极介电层130和位于栅极介电层130上方的栅电极层140。
栅极介电层130形成为覆盖半导体鳍120的至少部分沟道区域的顶面323和侧壁324。在一些实施例中，栅极介电层130包括氧化硅、氮化硅、氮氧化硅或高k电介质的一层或多层。高k电介质可以包括金属氧化物。用于高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物和/或它们的混合物。可以使用诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV臭氧氧化或它们的组合的合适的操作形成栅极介电层130。栅极介电层130还可以包括界面层(未示出)以减小栅极介电层130和鳍120之间的损害。界面层可以包括氧化硅。
之后，在栅极介电层130上形成栅电极层140。在至少一个实施例中，栅电极层140覆盖了多于一个半导体鳍120的上部322，从而使得产生的n-型Fin FET器件802包括多于一个鳍结构。在一些可选实施例中，半导体鳍120的每个上部322均可以用于形成分隔开的n-型Fin FET器件802。栅电极层140可以包括单层或多层结构。栅电极层140可以包括多晶硅。此外，栅电极层140可以是具有均匀或非均匀掺杂的掺杂多晶硅。在一些可选实施例中，栅电极层140可以包括诸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi、具有与衬底材料兼容的功函数的其它导电材料或它们的组合的金属。可以使用诸如ALD、CVD、PVD、镀或它们的组合的合适的操作形成栅电极层140。在一些实施例中，在栅极堆叠件320上形成硬掩模层332(已经用于图案化多晶硅层)。
在图9至图19中，示出了具有一个或多个p-型Fin FET结构(例如，p-型Fin FET器件904)和一个或多个n-型Fin FET结构(例如，n-型Fin FET器件902)的半导体器件。在本发明中，Fin FET器件300描述为一个n-型Fin FET结构，但是根据实施，可以配置为另一类型的Fin FET结构。为了简单的目的，图9至图19中所提供的主题将参照n-型Fin FET器件902进行讨论，其中对于顺序制造的某些部件，额外参考了p-型Fin FET器件904。
图9是根据所提供技术的实施例的处于顺序的制造工艺的各个阶段的一个的n-型Fin FET器件902和p-型Fin FET器件904的立体图。在图9中，提供用于两个鳍结构的一个栅极结构。在图9中，n-型Fin FET器件902由侧壁间隔件材料328覆盖(由沿着栅极堆叠件320的垂直侧的介电层制成)。在一些实施例中，介电层包括氧化硅、氮化硅、氮氧化硅或其它合适的材料的一层或多层。介电层可以包括单层或多层结构。可以通过CVD、PVD、ALD或其它合适的技术形成介电层的毯状层。之后，对介电层实施各向异性蚀刻和/或回蚀刻操作以在栅极堆叠件320的两侧上形成一对侧壁间隔件材料328。在栅极堆叠件320的形成期间，实施各个清洗/蚀刻操作(蚀刻STI区域150a和150b)。
图10是根据所提供技术的实施例的处于顺序的制造工艺的各个阶段的一个的n-型Fin FET器件902和p-型Fin FET器件904的立体图。使未由栅极堆叠件320(图8)和在其上方形成的侧壁间隔件材料328覆盖的部分半导体鳍120凹进以形成位于第一隔离区域150a和第二隔离区域150b的顶面317之下的具有顶面319的半导体鳍120的凹进部分326。在一个实施例中，使用侧壁间隔件材料328作为硬掩模，实施偏置蚀刻操作以使未被保护或暴露的上部322的顶面319凹进以形成半导体鳍120的凹进部分326。在实施例中，可以使用HBr和/或Cl2作为蚀刻气体实施蚀刻操作。
图11是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的n-型FinFET器件902和p-型Fin FET器件904的立体图。通过在半导体鳍120的凹进部分326上方选择性地生长应变材料(例如，应变材料330a、330b)并且在第一隔离区域150a和第二隔离区域150b的顶面317上方延伸产生图11中描述的结构。由于应变材料330a、330b的晶格常数与半导体鳍120的沟道区域不同，因此半导体鳍120的沟道区域是应变的或受到应力的以使器件的载流子迁移率和器件性能增强。虽然应变材料330a、330b分别相对于图11中的每个鳍形成，但是可以连接应变材料330a、330b以形成共同的应变材料结构。
在至少一个实施例中，通过LPCVD操作外延生长诸如碳化硅(SiC)和/或磷化硅(SiP)的应变材料330a以形成n-型Fin FET器件902的源极和漏极区域。在至少另一个其它实施例中，通过LPCVD操作外延生长诸如硅锗(SiGe)的应变材料330b以形成p-型Fin FET器件904的源极和漏极区域。
分别形成p-型Fin FET器件904和n-型Fin FET器件902。在这方面，可以使用光刻和蚀刻操作限定n-型外延区域或p-型外延区域。在图10和图11中，例如，n-型Fin FET器件902由氮化硅(SiN)层覆盖，从而使得在p-型Fin FET器件904中的凹槽和源极/漏极形成期间保护n-型Fin FET器件902。在形成用于p-型Fin FET器件904的应变材料之后，p-型FinFET器件904由SiN层覆盖，并且之后对n-型Fin FET器件902实施包括凹槽形成和应变材料形成的类似的操作。
图12是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的n-型FinFET器件902和p-型Fin FET器件904的立体图。图12B示出了根据本发明的实施例的沿着B-B’的n-型Fin FET器件902的截面图。图12C示出了根据本发明的实施例的深度范围之上的掺杂浓度的实例的绘图。
如图12A所示，当p-型Fin FET器件904由光刻胶层1202覆盖时，实施磷二聚体离子注入1204。如上所述，本发明通过对磷掺杂外延层(例如，n-型Fin FET器件902的n-型外延区域)的顶面提供相对较重和浅的掺杂提供了用于n-型Fin FET器件902的接触电容的减小和沟道迁移率的增加。特别地，利用磷二聚体(P2 +)离子注入1204有效地产生了比使用P+的传统的磷离子注入更高的化学磷浓度并且增加了更高的非晶水平。
对应变材料330a的顶面实施磷二聚体离子注入以提供较高的磷浓度以通过与上层的接触减小接触电阻并且增加沿着沟道区域的拉伸应变，从而增加n-型沟道的有效电子迁移率。在这方面，更高的拉伸应变可以引起沟道区域中的体相晶格参数的减小，诸如在应变材料330a的顶面处的磷浓度从约0.543nm至约0.537nm基于10％至15％的增加。
在一些方面，磷二聚体离子注入1204使用在从约0.1KeV至约500KeV范围内的注入能量注入掺杂剂种类。在一些实施例中，注入剂量在从约1x1015原子/立方厘米至约4x1015原子/立方厘米的范围内。在其它实施例中，加速电压在从约10KeV至约100KeV的范围内。在某些实施例中，加速电压在从约1KeV至约10KeV的范围内。此外，离子束相对于垂直轴1206的倾角可以在从约0度至约45度的范围内变化。此外，可以从两个方向(例如，0度和180度，通过旋转晶圆)或四个方向注入离子。
在一些实施例中，第一掺杂剂的磷二聚体离子注入1204包括冷却至少第一鳍结构和第一应变材料至-20℃之下的温度；因此为冷注入。冷注入中的温度可以在从约-10℃至约-100℃的范围内。例如，在一些实施例中，包括n-型外延区域(或n-型应变材料)的n-型Fin FET器件902可以从室温冷却至-20℃的温度，或在其它实施例中，-20℃之下。
由于相对较高的非晶度(或用于激活需要的较低的活化能)，因此，在这些冷却温度下的磷二聚体离子注入1204引起表面上的更活化的磷掺杂剂。因此，相对于室温注入，实施磷二聚体离子注入1204作为冷注入可以引起更多横向蔓延产生。这是因为更冷的温度引起注入的磷原子相对于应变材料330a的顶面的初始穿透点进一步横向移动。如此处使用的，术语“横向方差”指的是沿着轴(约正交于初始穿透的表面)的离子的横向移动。
在一个或多个实现中，在第一区域1210中注入的离子(杂质)具有第一横向方差并且第二区域1212中的杂质具有第二横向偏差，由于实施磷二聚体离子注入1204作为冷注入操作，因此第一横向方差大于第二横向方差。因此，由于n-型Fin FET器件902的相对较短的沟道长度，因此横向方差的增加引起了接触电阻的减小。例如，磷二聚体离子注入后，可以去除光刻胶层1202。此外，之后实施热退火操作(见图13)。在一些实施例中，使用磷团簇离子，而不是磷二聚体离子。
如以下表1所示，描述了磷二聚体注入和退火的两个不同实例。例如，在室温下用磷二聚体掺杂剂注入器件A；然而，在冷冻温度(例如，在约-20℃)下用磷二聚体掺杂剂注入器件B。用相同的掺杂剂量(介于约1x1015原子/立方厘米和约4x1015原子/立方厘米之间)和相同的退火温度(介于约950和约1250℃之间)注入两个器件。相对于器件A，器件B显示了更低的总电阻(相对于器件A的电阻值的0.98)、高约3％的栅极至源极电容性能和高约2％的栅极至栅极电容性能。在冷冻温度下注入产生了相对于总电阻和电容性能的更高的器件性能以提供用于NMOS Fin FET结构的沟道迁移率的增加。
表1：S/D磷二聚体注入和热优化
A B
N+S/D注入温度 室温 -20℃
相对总电阻 1 0.98
相对寄生电阻 1 0.99
相对沟道电阻 1 0.99
相对栅极至漏极电容 1 1.03
相对栅极至栅极电容 1 1.02
如图12B所示，n-型外延区域可以具有第一区域1210(包括顶面)，该第一区域1210具有在从约0.1纳米(nm)至约8nm的范围内的第一厚度(T1)。与设置在第一区域1210之下的第二区域1212相比，由于磷二聚体离子注入1204，第一区域1210可以接收更高的磷浓度。在一些实施例中，第二区域1212具有在从约25nm至约60nm范围内的第二厚度(T2)，并且在可以可选择地实施的外延生长操作或单原子磷注入期间，包含基于外延生长的磷化硅的掺杂浓度。
图12C示出了深度范围之上的掺杂浓度的SIMS(二次离子质谱)的实例的绘图。如图12C所示，在本实施例中的峰值磷二聚体掺杂浓度(标记为“SiP+P2I/I+μSSA”)大于约1x1022原子/立方厘米(例如，区域1252)，并且位于小于注入的硅区域(例如，图12B的第一区域1210)的顶面几纳米处，从而使得表面附近的掺杂浓度增加。相反地，峰值单原子磷掺杂浓度(标记为“SiP dep”)和具有亚微秒退火的峰值单原子磷掺杂浓度(标记为“SiP+μSSA”)小于峰值磷二聚体掺杂浓度的大小。图12C示出了通过使用P2 +离子注入，在更接近源极/漏极外延区域的表面的部分引入更高量的杂质。
图13是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的n-型FinFET器件902和p-型Fin FET器件904的立体图。在磷二聚体离子注入1204之后，可以在从约950℃至约1250℃的范围内的温度下实施热退火操作1302以激活注入的磷。如上所述，磷浓度的增加(通过磷二聚体离子注入)增加了施加在n-型Fin FET器件902的沟道区域上的拉伸应变。在这方面，拉伸应变的增加增强了沟道电子迁移率。
在一些实施例中，热退火操作1302的应用可以包括加热半导体器件(特别地，n-型Fin FET器件902)至从约900℃至1000℃范围内的温度，或在其它实施例中，至从约1000℃至约1300℃范围内的温度。在一些实施例中，施加持续时间在从约1秒至约10秒范围内的热退火操作1302。在一些方面，横跨n-型Fin FET器件902和p-型Fin FET器件904均匀地施加热退火操作1302。热退火操作1302可以包括从RTA、闪光退火、亚秒退火(SSA)、亚微秒退火(μSSA)、激光退火等的组中选择的退火操作。在一些实施例中，在从约950℃至约1250℃的范围内的温度下实施约7至约10秒的RTA。可选地，在其它实施例中，在从约1050至约1150℃的范围内的温度下实施约1至约6秒的退火操作。在其它实施例中，在从约950至约1150℃的范围内的温度下实施约10至约500微秒的μSSA。
图14是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的n-型FinFET器件902和p-型Fin FET器件904的立体图。在形成源极/漏极区域(例如，应变材料330a、应变材料330b)之后，实施沉积接触蚀刻停止层(CESL)1402的操作。在这个实例中，CESL1402可以施加为均匀地位于n-型Fin FET器件902和p-型Fin FET器件904上方的层。
图15是根据本发明的实施例的处于制造的各个阶段的一个的n-型Fin FET器件902和p-型Fin FET器件904的立体图。CESL操作(见图14)随后是沉积层间介电(ILD)层1502的操作。通过诸如CVD的合适的技术沉积ILD层1502。在这个实施例中，ILD层1502施加为均匀地位于n-型Fin FET器件902和p-型Fin FET器件904上方的层。ILD层1502包括诸如氧化硅、氮化硅、低k介电材料或它们的组合的一层或多层的介电材料。
图16是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的n-型FinFET器件902和p-型Fin FET器件904的立体图。随后，通过CMP操作平坦化ILD层1502和硬掩模，产生如图16所示的结构。
在本发明的实施例中，通过诸如光刻操作图案化ILD层1502来形成源极/漏极电极(接触件)以形成暴露应变材料330a和330b的开口。在开口中沉积诸如铜、钨、镍、钛等的合适的导电材料。在一些实施例中，在导电材料和源极/漏极的界面处形成金属硅化物以改进界面处的电导率。在一个实例中，使用镶嵌和/或双镶嵌操作形成铜基多层互连结构。在另一实施例中，使用钨在开口中形成钨插塞。
在这个实施例中，实现先STI/后栅极方法。在这个实施例中的许多操作与先STI/先栅极方法相同或类似。该方法与去除部分STI区域的操作相同。
为了使用高k金属栅极(HK/MG)，实施在鳍的暴露的端部上面沉积伪栅极电介质的操作、沉积伪栅极的操作和图案化伪栅极的操作。在图案化伪栅极之后，直至ILD层1502的CMP的操作之后，下一步操作与先STI/先栅极方法相同或类似。
图17是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的n-型FinFET器件902和p-型Fin FET器件904的截面图。在ILD层1502的CMP之后，同样实施去除伪栅极的操作和去除伪栅极电介质的操作。使用合适的蚀刻操作去除伪栅极和伪栅极电介质。
图18是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的n-型FinFET器件902和p-型Fin FET器件904的截面图。随后，进行在高k栅极电介质1804上沉积高k金属栅极(HK/MG)1802的操作。根据本发明的实施例，高k栅极电介质1804可以包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其它合适的高k介电材料和/或它们的组合的一层或多层。高k金属栅极1802材料可以包括Ti、TiN、钛铝合金、Al、AlN、Ta、TaN、TaC、TaCN、TaSi等的一层或多层。
图19是根据本发明的实施例的处于顺序的制造工艺的各个阶段的一个的n-型FinFET器件902和p-型Fin FET器件904的截面图。在HK/MG电极结构的形成之后，用类似于先STI/先栅极的方法的方式图案化源极/漏极电极。
在其它实施例中，用于制造Fin FET器件300的方法利用先EPI/先栅极方法或先EPI/后栅极方法。在先EPI方法中，在衬底110上形成外延层，并且之后，随后图案化外延层以形成鳍(例如，半导体鳍120)。在先EPI实施例中的许多操作与先STI方法的操作相同或类似。
根据本发明的实施例的随后的工艺也可以在半导体衬底110上形成各个接触件/通孔/线和多层互连部件(例如，金属层和层间电介质)，配置为连接Fin FET器件300的各个部件或结构。例如，多层互连结构包括诸如传统的通孔或接触件的垂直互连件和诸如金属线的水平互连件。
Fin FET器件300仅作为一个实例。Fin FET器件300可以用在诸如数码相机、图像传感器器件、异质半导体器件、动态随机存取存储(DRAM)单元，单电子晶体管(SET)和/或其它微电子器件(此处统称为微电子器件)的各个应用中。当然，本发明的方面也适用和/或较易适应于包括单栅极晶体管、双栅极晶体管和其它多栅极晶体管的其它类型的晶体管，并且可以在包括传感器单元、存储器单元、逻辑单元和其它的许多不同的应用中采用。
本发明通过对磷掺杂的含硅外延层的顶面提供相对较重和浅的掺杂提供了用于NMOS Fin FET结构的接触电容的减小和沟道迁移率的增加。具体地，在外延层操作之后，利用磷二聚体(P2 +)离子注入以在相同的注入剂量下比传统磷离子注入有效地结合更高的化学磷浓度和非晶水平。磷二聚体离子注入可以是或可以部分是温度在-20℃之下的冷注入以引起更高的非晶水平(或更低的活化能)。
在实施例中，制造Fin FET器件的方法包括提供具有第一鳍结构和第二鳍结构的衬底。该方法包括在衬底上形成隔离层，其中，该隔离层形成为邻近于第一鳍结构和第二鳍结构。该方法包括在第一鳍结构和隔离层的至少部分上形成第一栅极结构。该方法包括在第二鳍结构和隔离层的至少部分上形成第二栅极结构。该方法包括通过外延生长操作形成第一应变材料，其中，第一应变材料向第一鳍结构的沟道区域提供应力。该方法包括通过外延生长操作形成第二应变材料，其中，第二应变材料向第二鳍结构的沟道区域提供应力。该方法也包括对第一应变材料的至少第一区域注入第一掺杂剂，其中，第一区域具有第一掺杂剂的第一掺杂浓度。在这个实施例中，第一掺杂浓度大于第一应变材料的第二区域中的第二掺杂剂的第二掺杂浓度。该方法也包括对至少第一鳍结构和第一应变材料施加热退火操作，其中，通过至少热退火操作，第一鳍结构的沟道区域比第二鳍结构的沟道区域具有更大的沟道迁移率。
在上述方法中，还包括：在所述第二栅极结构和所述第二应变材料上施加光刻胶层；以及在注入所述磷二聚体掺杂剂之后，去除所述光刻胶层。
在上述方法中，其中，作为冷注入操作的部分，注入所述磷二聚体掺杂剂包括将至少所述第一鳍结构和所述第一应变材料冷却至-20℃之下的温度。
在上述方法中，其中，作为冷注入操作的部分，注入所述磷二聚体掺杂剂包括将至少所述第一鳍结构和所述第一应变材料冷却至-20℃之下的温度，在所述第一区域中注入的离子具有第一横向方差，并且在所述第二区域中注入的离子具有第二横向方差，其中，通过所述冷注入操作，所述第一横向方差大于所述第二横向方差。
在上述方法中，其中，对至少所述第一鳍结构和所述第一应变材料施加所述热退火操作包括将所述第一鳍结构和所述第一应变材料加热至在从1000℃至1100℃的范围内的温度。
在上述方法中，其中，施加持续时间在从1秒至10秒范围内的所述热退火操作。
在上述方法中，其中，所述第一掺杂浓度在从1x1021原子/立方厘米至1x1022原子/立方厘米的范围内。
在上述方法中，其中，注入所述磷二聚体掺杂剂的注入剂量在从1x1015原子/立方厘米至4x1015原子/立方厘米的范围内。
在上述方法中，还包括：在所述第一栅极结构和所述第二栅极结构的侧壁上形成间隔件；通过蚀刻未由所述第一栅极结构和所述间隔件覆盖的部分所述第一鳍结构形成第一凹进部分；在所述第一凹进部分中和所述第一凹进部分之上形成所述第一应变材料；通过蚀刻未由所述第二栅极结构和所述间隔件覆盖的部分所述第二鳍结构形成第二凹进部分；以及在所述第二凹进部分中和所述第二凹进部分之上形成所述第二应变材料。
在另一实施例中，制造Fin FET器件的方法包括提供具有鳍结构的衬底。该方法包括在衬底上形成隔离层，其中，该隔离层形成为邻近于鳍结构。该方法包括在鳍结构和隔离层的至少部分上形成栅极结构。该方法包括通过外延生长操作形成应变材料，其中，应变材料向鳍结构的沟道区域提供应力。该方法包括对应变材料的至少第一区域注入第一掺杂剂，其中，第一区域具有第一掺杂剂的第一掺杂浓度，并且第一掺杂浓度大于应变材料的第二区域中的第二掺杂剂的第二掺杂浓度。该方法也包括对至少鳍结构和应变材料施加热退火操作，其中，通过至少热退火操作，鳍结构的沟道区域比位于衬底上的第二鳍结构的沟道区域具有更大的沟道迁移率。
在上述方法中，其中，注入所述第一类型的磷掺杂剂的注入剂量在从1x1015原子/立方厘米至4x1015原子/立方厘米的范围内，并且其中，所述第一掺杂浓度在从1x1021原子/立方厘米至1x1022原子/立方厘米的范围内。
在上述方法中，其中，注入所述第一类型的磷掺杂剂包括将至少所述鳍结构和所述应变材料冷却至-20℃之下的温度。
在上述方法中，其中，施加所述热退火操作包括将所述鳍结构和所述应变材料加热至在从1000℃至1100℃范围内的温度。
在上述方法中，其中，所述第一类型的磷掺杂剂是包括磷二聚体(P2 +)的n-型掺杂剂，并且所述第二类型的磷掺杂剂是包括单原子磷(P)的n-型掺杂剂。
仍在另一实施例中，半导体器件包括衬底、第一鳍结构和第二鳍结构。该半导体器件包括形成在衬底上的隔离层，其中，隔离层形成为邻近于第一鳍结构和第二鳍结构。半导体器件包括形成在第一鳍结构和隔离层的至少部分上的第一栅极结构。该半导体器件包括形成在第二鳍结构和隔离层的至少部分上的第二栅极结构。该半导体器件包括第一外延层，该第一外延层包括对第一鳍结构的沟道区域提供应力的第一应变材料。该半导体器件包括第二外延层，该第二外延层包括对第二鳍结构的沟道区域提供应力的第二应变材料，其中，第二外延层具有第一区域和第二区域。第一区域具有第一掺杂剂的第一掺杂浓度并且第二区域具有第二掺杂剂的第二掺杂浓度。在这个实施例中，第一掺杂浓度大于第二掺杂浓度。
在上述半导体器件中，其中，所述第一掺杂剂是包括磷的n-型掺杂剂。
在上述半导体器件中，其中，所述第一外延层的注入的离子具有第一横向方差，并且所述第二外延层的注入的离子具有第二横向方差，其中，所述第二横向方差大于所述第一横向方差。
在上述半导体器件中，其中，所述第一区域设置在所述第二区域上，所述第一区域的厚度在从0.1纳米(nm)至8nm的范围内。
在上述半导体器件中，其中，所述第一掺杂剂设置在所述第二外延层的顶面上。
在上述半导体器件中，其中，所述第一应变材料配置为用于p-型Fin FET器件并且所述第二应变材料配置为用于n-型Fin FET器件。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造鳍式场效应晶体管(Fin FET)器件的方法，所述方法包括：
提供具有第一鳍结构和第二鳍结构的衬底；
在所述衬底上形成隔离层，所述隔离层形成为邻近于所述第一鳍结构和所述第二鳍结构；
在所述第一鳍结构和所述隔离层的至少部分上形成第一栅极结构；
在所述第二鳍结构和所述隔离层的至少部分上形成第二栅极结构；
通过外延生长操作形成第一应变材料，所述第一应变材料向所述第一鳍结构的沟道区域提供应力；
通过外延生长操作形成第二应变材料，所述第二应变材料向所述第二鳍结构的沟道区域提供应力；
对所述第一应变材料的至少第一区域注入磷二聚体掺杂剂，所述第一区域具有所述磷二聚体掺杂剂的第一掺杂浓度，所述第一掺杂浓度大于所述第一应变材料的第二区域中的磷掺杂剂的第二掺杂浓度；以及
对至少所述第一鳍结构和所述第一应变材料施加热退火操作，通过至少所述热退火操作，所述第一鳍结构的所述沟道区域比所述第二鳍结构的所述沟道区域具有更大的沟道迁移率。
2.根据权利要求1所述的方法，还包括：
在所述第二栅极结构和所述第二应变材料上施加光刻胶层；以及
在注入所述磷二聚体掺杂剂之后，去除所述光刻胶层。
3.根据权利要求1所述的方法，其中，作为冷注入操作的部分，注入所述磷二聚体掺杂剂包括将至少所述第一鳍结构和所述第一应变材料冷却至-20℃之下的温度。
4.根据权利要求3所述的方法，其中，在所述第一区域中注入的离子具有第一横向方差，并且在所述第二区域中注入的离子具有第二横向方差，其中，通过所述冷注入操作，所述第一横向方差大于所述第二横向方差。
5.根据权利要求1所述的方法，其中，对至少所述第一鳍结构和所述第一应变材料施加所述热退火操作包括将所述第一鳍结构和所述第一应变材料加热至在从1000℃至1100℃的范围内的温度。
6.根据权利要求1所述的方法，其中，施加持续时间在从1秒至10秒范围内的所述热退火操作。
7.根据权利要求1所述的方法，其中，所述第一掺杂浓度在从1x1021原子/立方厘米至1x1022原子/立方厘米的范围内。
8.根据权利要求1所述的方法，其中，注入所述磷二聚体掺杂剂的注入剂量在从1x1015原子/立方厘米至4x1015原子/立方厘米的范围内。
9.一种制造鳍式场效应晶体管(Fin FET)器件的方法，所述方法包括：
提供具有鳍结构的衬底；
在所述衬底上形成隔离层，所述隔离层形成为邻近于所述鳍结构；
在所述鳍结构和所述隔离层的至少部分上形成栅极结构；
通过外延生长操作形成应变材料，所述应变材料向所述鳍结构的沟道区域提供应力；
对所述应变材料的至少第一区域注入第一类型的磷掺杂剂，所述第一区域具有所述第一类型的磷掺杂剂的第一掺杂浓度，所述第一掺杂浓度大于所述应变材料的第二区域中的第二类型的磷掺杂剂的第二掺杂浓度；以及
对至少所述鳍结构和所述应变材料施加热退火操作，通过至少所述热退火操作，所述鳍结构的所述沟道区域比位于所述衬底上的第二鳍结构的沟道区域具有更大的沟道迁移率。
10.一种半导体器件，包括：
衬底；
第一鳍结构；
第二鳍结构；
隔离层，形成在所述衬底上，所述隔离层形成为邻近于所述第一鳍结构和所述第二鳍结构；
第一栅极结构，形成在所述第一鳍结构和所述隔离层的至少部分上；
第二栅极结构，形成在所述第二鳍结构和所述隔离层的至少部分上；
第一外延层，包括对所述第一鳍结构的沟道区域提供应力的第一应变材料；以及
第二外延层，包括对所述第二鳍结构的沟道区域提供应力的第二应变材料，所述第二外延层具有第一区域和第二区域，所述第一区域比所述第二区域更接近于所述第二外延层的表面，所述第一区域具有第一掺杂剂的第一掺杂浓度并且所述第二区域具有第二掺杂剂的第二掺杂浓度，所述第一掺杂浓度大于所述第二掺杂浓度。
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