CN106252232A - 掩埋沟道半导体器件及其制造方法 - Google Patents

掩埋沟道半导体器件及其制造方法 Download PDF

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CN106252232A
CN106252232A CN201610090342.6A CN201610090342A CN106252232A CN 106252232 A CN106252232 A CN 106252232A CN 201610090342 A CN201610090342 A CN 201610090342A CN 106252232 A CN106252232 A CN 106252232A
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陈家忠
黄崎峰
梁其翔
蔡辅桓
谢协宏
叶子祯
蔡汉旻
朱虹霖
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供一种用于制造半导体器件的方法，包括在衬底上方形成在第一方向上延伸的一个或多个鳍部。一个或多个鳍部包括沿着第一方向的第一区域和位于第一区域两侧沿着第一方向的第二区域。将掺杂剂注入鳍部的第一区域，但是未注入第二区域。栅极结构位于第一区域上方，并且在鳍部的第二区域上形成源极/漏极。本发明还提供了一种半导体器件及其包括该半导体器件的Gilbert单元混频器。

Description

掩埋沟道半导体器件及其制造方法
技术领域
本发明总体涉及半导体领域，更具体地，涉及半导体器件、相关的制造方法及其包括该半导体器件的Gilbert单元混频器。
背景技术
随着半导体工业已经进入到纳米技术工艺节点以追求更高的器件密度、更高的性能和更低的成本，来自制造和设计问题的挑战已经导致了诸如鳍式场效应晶体管(FinFET)的三维设计的发展。FinFET器件通常包括具有高纵横比的半导体鳍并且在其中形成半导体晶体管器件的沟道和源极/漏极区。利用沟道和源极/漏极区的增大的表面面积的优势，沿着鳍结构的侧面并且在鳍结构的侧面上方(如，包裹)形成栅极，以产生更快、更可靠和更好控制的半导体晶体管器件。在一些器件中，例如，FinFET的源极/漏极(S/D)部分中的应变材料使用硅锗(SiGe)、磷化硅(SiP)或碳化硅(SiC)，这可以用于增强载流子迁移率。
发明内容
根据本发明的一个方面，提供了一种用于制造半导体器件的方法，包括：在衬底上方形成在第一方向上延伸的一个或多个鳍部；其中，所述一个或多个鳍部包括沿着所述第一方向的第一区域和位于所述第一区域两侧且沿着所述第一方向的第二区域；将掺杂剂注入所述鳍部的第一区域，但是未注入所述第二区域；在所述鳍部的第一区域上方形成栅极结构；以及在所述鳍部的第二区域上形成源极/漏极。
优选地，所述掺杂剂是选自由磷、砷和锑组成的组中的N型掺杂剂。
优选地，所述掺杂剂是选自由硼、BF2、铝和镓组成的组中的P型掺杂剂。
优选地，所述第一区域中的掺杂剂的浓度为约1.5×1016原子cm-3至2.0×1020原子cm-3。
优选地，所述第一区域中的掺杂剂的浓度为大约1×1018原子cm-3至2×1018原子cm-3。
优选地，该方法还包括：在所述鳍部上方形成抗蚀剂层；以及在注入所述掺杂剂之前，在所述抗蚀剂层中形成开口以暴露所述鳍部的第一区域。
优选地，该方法还包括：在注入所述掺杂剂之后，去除所述抗蚀剂层。
根据本发明的一个方面，提供了一种半导体器件，包括：一个或多个鳍部，位于衬底上方并且在第一方向上延伸；其中，所述一个或多个鳍部包括沿着所述第一方向的第一区域和位于所述第一区域两侧且沿着所述第一方向的第二区域，并且所述鳍部的第一区域包括浓度为大约1.5×1016原子cm-3至2.0×1020原子cm-3的掺杂剂；栅极结构，位于所述鳍部的第一区域上方；以及源极/漏极，形成在所述鳍部的第二区域上。
优选地，所述掺杂剂是选自由磷、砷和锑组成的组中的N型掺杂剂。
优选地，所述掺杂剂是选自由硼、BF2、铝和镓组成的组中的P型掺杂剂。
优选地，所述第一区域中的掺杂剂的浓度为大约1.7×1017原子cm-3至1.7×1019原子cm-3。
优选地，所述第一区域中的掺杂剂的浓度为大约1×1018原子cm-3至2×1018原子cm-3。
优选地，N型掺杂剂位于所述鳍部的中心区域处，并且距所述鳍部的顶部大约15nm至20nm以及在厚度方向上距沿着所述鳍部的所述第一方向延伸的侧壁3nm至7nm。
优选地，该半导体器件还包括：多个鳍部；以及隔离绝缘层，形成在邻近的鳍部之间。
优选地，该半导体器件具有位于源极与漏极区域之间的为大约7nm至大约16nm的栅极长度。
优选地，所述栅极结构包括高k栅极介电层和金属栅电极。
优选地，所述源极/漏极区域是凸起的源极/漏极区域。
根据本发明的又一方面，提供了一种Gilbert单元混频器包括：多个晶体管，彼此电连接，其中，所述多个晶体管中的至少一个包括：一个或多个鳍部，位于衬底上方并且在第一方向上延伸；其中，所述一个或多个鳍部包括沿着所述第一方向的第一区域和位于所述第一区域两侧且沿着所述第一方向的第二区域，并且所述鳍部的第一区域包括浓度为大约1.5×1016原子cm-3至2.0×1020原子cm-3的掺杂剂；栅极结构，位于所述鳍部的第一区域上方；以及源极/漏极，形成在所述鳍部的第二区域上。
优选地，所述掺杂剂位于所述鳍部的中心区域处，并且距所述鳍部的顶部大约15nm至20nm以及在厚度方向上距沿着所述鳍部的所述第一方向延伸的侧壁3nm至7nm。优选地，所述掺杂剂是选自由磷、砷和锑组成的组中的N型掺杂剂。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1是根据本发明的实施例的用于制造具有鳍结构的半导体FET器件(FinFET)的示例性工艺流程图。
图2至图16示出了根据本发明的实施例的用于制造半导体器件的示例性方法和半导体器件。
图17示出了根据本发明的实施例的混频电路。
图18示出了根据本发明的实施例的包括混频电路的装置。
图19A至图19D是示出了根据本发明的包括FinFET的器件的栅极电压与漏极电流之间关系的示图。
图20是根据本发明的包括FinFET的器件的线性度(linearity)的示图。
具体实施方式
应当理解，以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，元件的尺寸不限制于公开的范围或数值，但是可以取决于工艺条件和/或期望的器件性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简化和清楚，可以以不同的尺寸任意地绘制各个部件。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，并因此对本文中所使用的空间相对位置描述符进行同样的解释。另外，术语“由…制成”可以意为“包括”或者“由…组成”。
FinFET器件具有比块状CMOS器件更大的闪噪。模拟/RF电路要求较低的噪声和较高线性度的MOS器件。
得益于本发明的一个或多个实施例的器件的实例是半导体器件。例如，这样的一个器件是FinFET器件。例如，FinFET器件可以是包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)FinFET器件的互补金属氧化物半导体(CMOS)器件。特别地，Gilbert单元混频器可以得益于本发明。以下公开内容将包括FinFET实例来说明本应用的各个实施例。然而，应该理解，除了特别声明外，本申请不应限制于特定类型的器件。
图1示出了根据本发明的实施例的用于制造具有鳍结构的半导体FET器件(FinFET)的示例性方法。示例性方法100包括在衬底上方形成一个或多个鳍部的操作102和将掺杂剂注入一个或多个鳍部的操作104。在注入操作之后，执行在一个或多个鳍部上方形成栅极结构的操作106。在操作108中，源极/漏极形成在一个或多个鳍部上且分别位于栅极结构的两侧。
如图2所示，根据一个实施例，为了制造一个或多个鳍部，在衬底12上方形成掩模层14。例如，通过热氧化工艺和/或化学汽相沉积(CVD)工艺形成掩模层14。例如，衬底12是具有在大约1×1015原子cm-3至大约2×1015原子cm-3的范围内的杂质浓度的p型硅衬底。在其他的实施例中，衬底12是具有在大约1×1015原子cm-3至大约2×1015原子cm-3的范围内的杂质浓度的n型硅衬底。例如，在一些实施例中，掩模层14包括垫氧(如，氧化硅)层16和氮化硅掩模层18。
可选地，衬底12可以包括：其他元素半导体，诸如锗；化合物半导体，包括诸如SiC和SiGe的IV-IV族化合物半导体、诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的III-V族化合物半导体；或它们的组合。在一个实施例中，衬底12是SOI(绝缘体上硅)衬底中的硅层。当使用SOI衬底时，鳍部可以从SOI衬底的硅层处突出或可以从SOI衬底的绝缘层处突出。在后者的情况下，SOI衬底的硅层用于形成鳍部。诸如非晶Si或非晶SiC的非晶衬底或诸如氧化硅的绝缘材料也可以用作衬底12。衬底12可以包括已适当地掺杂有杂质(例如，具有p型或n型导电性)的各种区域。
可以通过使用热氧化或CVD工艺形成垫氧层16。可以通过CVD、等离子体增强的化学汽相沉积(PECVD)、常压化学汽相沉积(APCVD)、低压CVD(LPCVD)、高密度等离子体CVD(HDPCVD)、原子层沉积(ALD)、物理汽相沉积(PVD)(诸如溅射方法)和/或其他工艺形成氮化硅掩模层18。
在一些实施例中，垫氧层16的厚度在大约2nm至大约15nm的范围内，并且氮化硅掩模层18的厚度在大约2nm至大约50nm的范围内。还在掩模层14上方形成掩模图案20。例如，掩模图案20是通过光刻操作形成的抗蚀剂图案。
通过将掩模图案20用作蚀刻掩模，形成包括垫氧层16和氮化硅掩模层18的硬掩模图案。在一些实施例中，硬掩模图案的宽度在约5nm至约40nm的范围内。在特定实施例中，硬掩模图案的宽度在大约7nm至大约12nm的范围内。
如图3所示，通过将硬掩模图案用作蚀刻掩模，通过使用干蚀刻方法和/或湿蚀刻方法以形成沟槽26的沟槽蚀刻而将衬底12图案化为多个鳍部24。鳍部24的高度在大约20nm至大约300nm的范围内。在特定实施例中，该高度在大约30nm至大约60nm的范围内。当鳍部24的高度不统一时，距离衬底的高度可以从对应于鳍部24的平均高度的平面处测起。每一个鳍部24的宽度都在大约7nm至大约15nm的范围内。
在该实施例中，块状硅晶圆用作衬底12。然而，在一些实施例中，其他类型的衬底可用作衬底12。例如，绝缘体上硅(SOI)晶圆可用作起始材料，并且SOI晶圆的绝缘层构成衬底12，而SOI晶圆的硅层用于鳍部24。
如图3所示，在衬底12上方设置八个鳍部24。然而，鳍部的数量不限于八个。可以只有一个鳍部或八个以上的鳍部。另外，可以邻近鳍部的侧面设置一个或多个伪鳍部以在图案化工艺中改进图案保真度。在一些实施例中，每一个鳍部24的宽度都在大约5nm至大约40nm的范围内，并且在特定实施例中，可以在大约7nm至大约15nm的范围内。在一些实施例中，邻近的鳍部之间的沟槽26的宽度在大约5nm至大约80nm的范围内，而在其他的实施例中，可以在大约7nm至大约15nm的范围内。然而，本领域的技术人员将理解，说明书通篇所列的尺寸和值仅是示例性的，并且可以改变以适合于不同规模的集成电路。
在某些实施例中，FinFET器件是P型FinFET。然而，在其他实施例中，取决于用于源极/漏极和沟道的掺杂剂类型，器件是N型FinFET。
如图4所示，在形成鳍部24之后，在鳍部24之间的沟槽26中以及在鳍部24上方形成隔离绝缘层22，从而使得鳍部24掩埋在隔离绝缘层22中。隔离绝缘层22还称为浅沟槽绝缘层(STI)。
隔离绝缘层22包括通过LPCVD(低压化学汽相沉积)、等离子体CVD或可流动CVD而形成的一个或多个绝缘材料层(诸如，氧化硅、氮氧化硅或氮化硅)。在可流动CVD中，沉积可流动介电材料，而不是氧化硅。正如它们的名字所表明的，可流动介电材料在沉积期间可以“流动”以填充具有高纵横比的间隙或空间。通常，将各种化学物质添加至含硅前体以允许沉积的膜流动。在一些实施例中，添加氮氢键合物。可流动介电前体的实例，特别是可流动氧化硅前体的实例包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或诸如三甲硅烷基胺(TSA)的甲硅烷基胺。在多次操作工艺中形成这些可流动氧化硅材料。在沉积可流动膜之后，对可流动膜进行固化然后进行退火以去除非期望的元素以形成氧化硅。当去除非期望的元素后，可流动膜变得致密和收缩。在一些实施例中，进行多次退火工艺。不止一次地对可流动膜进行固化和退火。可流动膜可掺有硼和/或磷。在一些实施例中，可通过SOG、SiO、SiON、SiOCN和/或氟掺杂的硅酸盐玻璃(FSG)的一层或多层来形成隔离绝缘层22。
执行平坦化操作以去除隔离绝缘层22的一部分。如图5所示，平坦化操作可以包括化学机械抛光(CMP)和/或回蚀刻工艺。
如图6所示，可以去除掩模层14，并且还去除隔离绝缘层22的上部，从而暴露鳍部24的沟道区域(上部)。
在某些实施例中，可以使用合适的蚀刻工艺来执行掩模层14的去除和部分地去除隔离绝缘层22。例如，可以通过湿蚀刻工艺(诸如将衬底浸入氢氟酸(HF)或磷酸(H3PO4))去除掩模层14。另一方面，可以使用干蚀刻工艺来执行部分地去除隔离绝缘层22。例如，可以使用将CHF3或BF3作为蚀刻气体的干蚀刻工艺。
图7示出了器件10的等轴视图，其中鳍部24从隔离绝缘层22处暴露。为了简化本发明，图7中仅示出了三个鳍部。鳍部24的暴露部分包括两个区域。位于鳍部24的中心部分的第一区域36是将要形成栅极结构的区域，并且位于鳍部24的周边部分的第二区域38是将要形成源极/漏极区域的区域。
图8示出了沿着图7的线A-A截取的截面图。如图9A所示，在鳍部24上方形成诸如光刻胶的抗蚀剂层44。通过将抗蚀剂层44暴露于光化辐射然后显影以形成暴露鳍部24的顶部的开口54来图案化抗蚀剂层44。在鳍部24的第一区域36上方形成开口54，并且由抗蚀剂44覆盖鳍部24的第二区域38。图9B示出了具有开口54的抗蚀剂层44的俯视图。
如图10所示，使用图案化的抗蚀剂层44作为掩模，通过离子注入将N型掺杂剂46注入鳍部24。掩蔽鳍部24，从而使得N型掺杂剂注入至鳍部的第一区域36，这将成为FinFET的沟道。在某些实施例中，以介于约1KeV至约100KeV的能量注入掺杂剂。
在某些实施例中，掺杂剂46是选自由磷、砷或锑组成的组中的N型掺杂剂。具体地，在特定实施例中，N型掺杂剂可以是P。在其他实施例中，掺杂剂46是选自由硼、BF2、Al和Ga组成的组中的P型掺杂剂。第一区域36中注入的N型掺杂剂46的浓度为大约1.5×1016至2.0×1020原子cm-3。在特定实施例中，第一区域36中的N型掺杂剂46的浓度为大约1.7×1017至1.7×1019原子cm-3。第一区域36中的N型掺杂剂46的浓度为大约1×1018至2×1018原子cm-3。如图11所示，注入的N型掺杂剂46可以形成掺杂区域48，该掺杂区域位于鳍部的中心区域，且在高度H方向上距离鳍部24的顶部大约15nm至20nm以及在厚度W方向上距鳍部24的侧壁3nm至7nm。掺杂区域48形成掩埋沟道。
对于图12，其是与沿着图7的线B-B的截面图对应的示图，示出了掩埋沟道掺杂区域48。随后将在掩埋沟道掺杂区域48上方形成栅电极结构，并且将在位于第一区域36两侧的第二区域38上方形成源极/漏极区域。沟道长度L对应于第一区域36的长度。在一些实施例中，沟道长度L可以在从大约7nm至大约16nm的范围内。沟道长度L也对应于随后形成的晶体管的栅极长度。
如图13所示，随后在鳍部的第一区域36上方形成栅极结构28。栅极结构形成工艺可以包括以下操作：沉积栅极介电层32；沉积栅电极30；图案化栅电极；轻掺杂漏极(LDD)注入；以及退火。随后在栅极结构28上形成侧壁间隔件34，并且执行对源极/漏极的注入和退火。图14对应于沿着图13的线a-a截取的截面图，示出了鳍部24和栅电极结构28的布置。
在某些实施例中，可使用前栅方法或后栅方法来制造FinFET。在使用高k介电质和金属栅极(HK/MG)的实施例中，应用后栅方法以形成栅电极。在后栅方法中，形成伪栅极，在高温退火之后的操作中将伪栅极随后去除，然后形成高k介电质和金属栅极(HK/MG)。
根据本发明的实施例，高k栅极介电层32可以包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)、其他合适的高k介电材料和/或它们的组合。金属栅极材料可以包括以下材料的一层或多层：Ti、TiN、钛-铝合金、Al、AlN、Ta、TaN、TaC、TaCN、TaSi等。
栅极介电质32可包括氧化硅、氮化硅、氮氧化硅、高k介电材料、其他适合的介电材料和/或它们的组合的一层或多层。在特定实施例中，栅电极30由多晶硅形成并且可以包括形成在栅电极上方的硬掩模。硬掩模可以由合适的硬掩模材料制成，包括SiO2、SiN或SiCN。在一些实施例中，栅极介电层的厚度在大约5nm至大约20nm的范围内，而在其他的实施例中，该厚度在大约5nm至大约10nm的范围内。栅电极结构可以包括附加的层，诸如界面层、覆盖层、扩散/阻挡层、介电层、导电层、其他合适的层或它们的组合。除了多晶硅之外，在一些实施例中，栅电极30包括任何其他合适的材料的一层或多层，诸如铝、铜、钛、钽、钨、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料或它们的组合。在一些实施例中，栅电极层的厚度在大约50nm至大约400nm的范围内，并且该厚度可以在大约100nm至大约200nm的范围内。
在一些实施例中，侧壁间隔件34用于偏移随后形成的掺杂区域，诸如源极/漏极区域。侧壁间隔件34还可以用于设计或改变源极/漏极区域(结)分布。可以通过合适的沉积和蚀刻技术形成侧壁间隔件34，并且侧壁间隔件34可以包括氮化硅、碳化硅、氮氧化硅、其他合适的材料或它们的组合。
可以通过CVD、PVD、ALD或其他合适的技术形成侧壁绝缘材料的毯式层。然后，对侧壁绝缘材料执行各向异性蚀刻以在栅极结构的两个主侧上形成一对侧壁绝缘层(间隔件34)。在一些实施例中，侧壁绝缘层34的厚度在大约5nm至大约30nm的范围内，并且在其他的实施例中，该厚度在大约10nm至大约20nm的范围内。如图13所示，可以不在鳍部的将要成为源极和漏极的区域上方形成侧壁绝缘层。
如图15所示，随后蚀刻鳍部的未被栅极结构28覆盖的第二区域38，以去除鳍部的位于STI区域22上面的部分。可以使用合适的光刻和蚀刻技术来去除鳍部的第二区域38。
如图16所示，在特定的实施例中，随后在鳍部24的蚀刻部分上方形成凸起的源极/漏极区域40，从而提供FinFET半导体器件10。可以通过一个或多个外延或外延(epi)工艺形成凸起的源极/漏极区域，从而Si部件、SiC部件、SiGe部件、SiP部件、SiCP部件或Si EPI或其他合适的部件上的III-V族半导体材料以晶态形成在鳍部上。外延工艺包括CVD沉积方法(如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延生长和/或其他合适的工艺。
在本发明的一些实施例中，形成源极/漏极电极以接触相应的源极/漏极区域。电极可以由合适的导电材料(诸如，铜、钨、镍、钛等)形成。在一些实施例中，在导电材料与源极/漏极界面处形成金属硅化物以提高界面处的导电性。在一个实例中，使用镶嵌工艺和/或双镶嵌工艺形成基于铜的多层互连结构。在另一实施例中，使用钨形成钨插塞。
根据本发明的实施例的随后的处理也可以在半导体衬底上形成各个接触件/通孔/线和多层互连部件(如，金属层和层间介电层)，接触件/通孔/线和多层互连部件配置为连接FinFET器件的各个部件或结构。例如，多层互连包括诸如传统的通孔或接触件的垂直互连件和诸如金属线的水平互连件。
在特定的实施例中，继续源极/漏极区域的外延生长，直到单独的源极/漏极区域合并在一起形成具有合并的源极/漏极区域的FinFET半导体器件。
如图17所示，在本发明的另一实施例中，提供了诸如Gilbert单元混频器50的半导体器件。Gilbert单元混频器包括彼此电连接的多个晶体管M1、M2、M3、M4、M5、M6。至少一个晶体管包括根据本发明先前所述的实施例的掩埋沟道FinFET。如图17所示，Gilbert单元混频器50还包括电感器L1、L2和电容器C1、C2。
如图17所示，在根据本发明的Gilbert单元混频器的一个实施例中，右侧的电路图是左侧电路图的镜像。电感器L1和L2分别连接至晶体管M3和M6。电容器C1连接在电感器L1和晶体管M3之间，并且连接至晶体管M5。电容器C2连接在电感器L2和晶体管M4之间，并且连接至晶体管M4。晶体管M3和M4的电流输出连接至晶体管M1，而晶体管M1的电流输出接地。在某些实施例中，晶体管M1、M2、M3、M4、M5和M6中的每一个都可以是掩埋沟道FinFET晶体管。
如图18所示，Gilbert单元混频器50可以包含在装置52中，该装置包括运算放大器、模数转换器、数模转换器、RF合成器和处理器。图18中的装置是RF完整电路框图，其包括混频器、局域网(LAN)、锁相环(PLL)、压控振荡器(VCO)和ADC。在某些实施例中，该装置中的所有的晶体管都可以是掩埋沟道FINFET器件。
与块状CMOS器件相比，具有掩埋沟道注入的FinFET器件可以降低多达10倍的闪烁噪声并且降低多达40％的功耗。在Gilbert单元混频器中使用根据本发明的掩埋沟道FinFET晶体管可以提供具有减少多达10倍的闪烁噪声的改进的混频器线性度。使用所公开的掩埋沟道FinFET晶体管的Gilbert单元混频器在比块状CMOS器件的阈值电压的一半还小的降低的阈值电压下，线性度改进了2至3倍并且漏极电流和功效增大。在相同的电流级，根据本发明的具有掩埋沟道FinFET晶体管的混频器可以将线性度提高多达3dB。在相同的线性度下，具有掩埋沟道FinFET晶体管的混频器可以将混频器的直流电流降低大约40％。图19A、图19B、图19C和图19D示出了与具有16nm的栅极长度的FinFET的标准器件相比的包括具有根据本发明的掩埋沟道的16nm栅极长度的FinFET的混频器的栅极阈值电压与漏极电流之间的关系。图20示出了包括具有根据本发明的掩埋沟道的16nm栅极长度的FinFET的混频器(BC)与具有16nm栅极长度的FinFET的标准器件(C)的线性度的比较。在图19A至19D和图20中，可以发现，掩埋沟道器件随着电压增大而电流更为线性地增大，但是传统的器件具有随着电压增大而指数型增大的电流。因此，根据本发明的器件具有增大的线性度和低噪声以及对陷阱波动(trap fluctuation)的不敏感性。
在本发明的一个实施例中，提供了一种用于制造半导体器件的方法。方法包括在衬底上方形成在第一方向上延伸的一个或多个鳍部。一个或多个鳍部包括沿着第一方向的第一区域和在第一区域的两侧上沿着第一方向的第二区域。将掺杂剂注入鳍部的第一区域，但是未注入第二区域。在鳍部的第一区域上方形成栅极结构，并且在鳍部的第二区域上形成源极/漏极。
在本发明的另一实施例中，提供了包括位于衬底上方的沿着第一方向延伸的一个或多个鳍部的半导体器件。一个或多个鳍部包括沿着第一方向的第一区域和在第一区域两侧沿着第一方向的第二区域，并且鳍部的第一区域包括浓度为大约1.5×1016至2.0×1020原子cm-3的掺杂剂。栅极结构位于鳍部的第一区域上方，并且在鳍部的第二区域上形成源极/漏极。
在本发明的另一实施例中，提供了包括彼此电连接的多个晶体管的Gilbert单元混频器。这些晶体管中的至少一个晶体管包括在衬底上方沿着第一方向延伸的一个或多个鳍部。一个或多个鳍部包括沿着第一方向的第一区域和在第一区域的两侧沿着第一方向的第二区域。鳍部的第一区域包括浓度为大约1.5×1016至2.0×1020原子cm-3的掺杂剂。栅极结构位于鳍部的第一区域上方，并且在鳍部的第二区域上形成源极/漏极。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种用于制造半导体器件的方法，包括：
在衬底上方形成在第一方向上延伸的一个或多个鳍部；
其中，所述一个或多个鳍部包括沿着所述第一方向的第一区域和位于所述第一区域两侧且沿着所述第一方向的第二区域；
将掺杂剂注入所述鳍部的第一区域，但是未注入所述第二区域；
在所述鳍部的第一区域上方形成栅极结构；以及
在所述鳍部的第二区域上形成源极/漏极。
2.根据权利要求1所述的用于制造半导体器件的方法，其中，所述掺杂剂是选自由磷、砷和锑组成的组中的N型掺杂剂。
3.根据权利要求1所述的用于制造半导体器件的方法，其中，所述掺杂剂是选自由硼、BF2、铝和镓组成的组中的P型掺杂剂。
4.一种半导体器件，包括：
一个或多个鳍部，位于衬底上方并且在第一方向上延伸；
其中，所述一个或多个鳍部包括沿着所述第一方向的第一区域和位于所述第一区域两侧且沿着所述第一方向的第二区域，并且所述鳍部的第一区域包括浓度为大约1.5×1016原子cm-3至2.0×1020原子cm-3的掺杂剂；
栅极结构，位于所述鳍部的第一区域上方；以及
源极/漏极，形成在所述鳍部的第二区域上。
5.根据权利要求4所述的半导体器件，其中，所述掺杂剂是选自由磷、砷和锑组成的组中的N型掺杂剂。
6.根据权利要求4所述的半导体器件，其中，所述掺杂剂是选自由硼、BF2、铝和镓组成的组中的P型掺杂剂。
7.根据权利要求4所述的半导体器件，其中，所述第一区域中的掺杂剂的浓度为大约1.7×1017原子cm-3至1.7×1019原子cm-3。
8.一种Gilbert单元混频器包括：
多个晶体管，彼此电连接，其中，所述多个晶体管中的至少一个包括：
一个或多个鳍部，位于衬底上方并且在第一方向上延伸；
其中，所述一个或多个鳍部包括沿着所述第一方向的第一区域和位于所述第一区域两侧且沿着所述第一方向的第二区域，并且所述鳍部的第一区域包括浓度为大约1.5×1016原子cm-3至2.0×1020原子cm-3的掺杂剂；
栅极结构，位于所述鳍部的第一区域上方；以及
源极/漏极，形成在所述鳍部的第二区域上。
9.根据权利要求8所述的Gilbert单元混频器，其中，所述掺杂剂位于所述鳍部的中心区域处，并且距所述鳍部的顶部大约15nm至20nm以及在厚度方向上距沿着所述鳍部的所述第一方向延伸的侧壁3nm至7nm。
10.根据权利要求8所述的Gilbert单元混频器，其中，所述掺杂剂是选自由磷、砷和锑组成的组中的N型掺杂剂。
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