TW201606991A - 半導體裝置及其製造方法及積體電路裝置 - Google Patents

半導體裝置及其製造方法及積體電路裝置 Download PDF

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TW201606991A
TW201606991A TW104111743A TW104111743A TW201606991A TW 201606991 A TW201606991 A TW 201606991A TW 104111743 A TW104111743 A TW 104111743A TW 104111743 A TW104111743 A TW 104111743A TW 201606991 A TW201606991 A TW 201606991A
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layer
substrate
semiconductor
fin
disposed
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TW104111743A
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TWI578498B (zh
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江國誠
家馨 馮
志強 吳
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台灣積體電路製造股份有限公司
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

本揭露提供一非平面電路裝置，其包含設置於通道區底下的應變產生結構。在一實施例中，一積體電路裝置包括一基板及形成於其上的第一鰭結構與第二鰭結構。一隔離特徵部件溝槽定義於第一鰭結構與第二鰭結構之間。上述電路裝置也包括一應變特徵部件形成於隔離特徵部件溝槽內的基底的水平表面上。應變特徵部件的配置係用於在第一鰭結構上形成的電晶體的通道區產生應變。上述電路也包括一填充介電質，設置於隔離特徵部件溝槽內的應變特徵部件之上。在某些實施例中，應變特徵部件更設置於第一鰭結構與第二鰭結構的垂直表面上。

Description

半導體裝置及其製造方法及積體電路裝置
本發明係有關於積體電路裝置的製造，特別係有關於一種鰭式場效電晶體，其具有應變產生特徵部件設置於位於淺溝槽隔離溝槽內且向下延伸至基底的鰭上。
半導體工業為了追求高裝置密度，高效能，低成本而已經進展到奈米尺寸技術製程的節點。儘管在材料與製造技術上有開創性的突破，但在微縮化像金氧半場效電晶體這樣的平面式裝置的技術證實有很大的挑戰。為了克服困難，電路設計者正在尋找新的結構以用來達到更進步的效能。其中一個探索途徑是發展出三維空間的設計，例如鰭式場效電晶體(Fin-like Field Effect Transistor)。鰭式場效電晶體可以想成典型的平面式元件上有著從基底朝向閘極凸出的結構。一個典型的鰭式場效電晶體是由從基底延伸一薄薄的鰭(或是鰭狀結構)製作而成。場效電晶體的通道是形成於垂直的鰭內，且閘極覆蓋(例如：環繞)鰭的通道區。將閘極覆蓋環繞在鰭上增加了通道區和閘極的接觸面積，閘極可因此由多側去控制通道區。這在許多方面存在優勢，且在某些應用中，鰭式場效電晶體減少短 通道效應，減少漏電以及增加電流。換句話說，它們比平面式元件更快，更小，更有效率。
然而，鰭式場效電晶體和其它非平面式裝置的技 術還在發展當中，就各方面而言，尚未把它們完整的潛能給實現出來。單舉一個例子而言，通道應變(在通道區裡的內在壓力)使用於平面式裝置中可以增進電荷載子通過通道區的流動性。然而，在非平面式元件中已證實很難產生通道應變，且當通道應變產生時，也已證實很難讓載子遷移率的增加有達到符合預期的效果。因此，儘管在非平面式裝置製造含有應變的通道，用傳統的技術便已足夠，但它們在其他方面也已經無法達到令人滿意的要求。為了持續達到不斷增加的設計需求，在本領域與其他地方需要有更多的進步。
本發明一實施例提供一種積體電路裝置，其包 括：一基底；一第一鰭結構和一第二鰭結構，個別設置於基底之上且具有一隔離特徵特徵部件溝槽定義於其間；一應變特徵部件，設置於隔離特徵部件溝槽內的基底的水平表面之上；及一填充介電質，設置於隔離特徵部件溝槽內的應變特徵部件之上。
本發明一實施提供一種半導體裝置，其包括：一 基底；一鰭，從基底垂直延伸且包括二或多個源極/汲極區及形成於上述二或多個源極/汲極區之間的一通道區；及一隔離特徵部件，設置於鄰近鰭的基底之上，其中隔離特徵部件包括：一襯層，形成於鰭的側表面與基底的上表面之上；及一填 充材料，設置於襯層之上，且具有背向基底的頂端表面，其中襯層設置於遠離填充材料的頂端表面。
本發明一實施例提供一種半導體裝置的製造方 法，上述方法包括：取得工作件，具有鰭結構形成於其上，其中鰭結構包括一第一半導體部及組成不同於第一半導體部的一第二半導體部；在鰭結構的通道區內的第一半導體部之上選擇性地形成應變一產生結構；在應變產生結構之上形成一隔離特徵部件；在鄰近通道區的一對源極/汲極區內凹陷第二半導體部；及在上述源極/汲極區內的凹陷的第二半導體部，磊晶成長源極/汲極結構。
100‧‧‧工作件
102‧‧‧基底
104‧‧‧鰭結構
106‧‧‧N型通道鰭式場效電晶體
108‧‧‧P型通道鰭式場效電晶體
110‧‧‧源極/汲極區
112‧‧‧通道區
114‧‧‧閘極堆疊
116‧‧‧隔離特徵部件
118‧‧‧襯層
120‧‧‧填充材料
122‧‧‧應變產生結構
200‧‧‧方法
202~232‧‧‧區塊
302‧‧‧N型金屬氧化物半導體
304‧‧‧P型金屬氧化物半導體
306‧‧‧第一基底層
308‧‧‧第二基底層
310‧‧‧第一基底層306的頂端部份
312‧‧‧第一基底層306的底端部份
318‧‧‧硬罩幕層
320‧‧‧光阻層
402‧‧‧隔離特徵部件溝槽
502‧‧‧第二硬罩幕層
902‧‧‧第三硬罩幕層
1002‧‧‧第三基底層
1202‧‧‧介電層
1302‧‧‧虛置閘極
1304‧‧‧虛置閘極層
1306‧‧‧虛置閘極硬罩幕層
1308‧‧‧閘極間隙壁
1502‧‧‧源極/汲極特徵部件
1602‧‧‧內層介電層
1702‧‧‧界面層
1704‧‧‧閘極介電層
1706‧‧‧金屬閘極層
第1圖係繪示出根據本揭露的不同型態中部份的工作件的立體示意圖。
第2A圖和第2B圖係根據本揭露的不同型態中，在工作件上製作鰭式裝置的方法流程圖。
第3及4圖係繪示出根據本揭露的不同型態中部份的工作件經過製作鰭式裝置的方法的剖面示意圖。
第5A、6A、7A、8A、9A、10A、11A和12A圖係繪示出根據本揭露的不同型態中部份的工作件經過製作鰭式裝置方法而具有通道區的剖面示意圖。
第5B、6B、7B、8B、9B、10B、11B和12B圖係繪示出根據本揭露的不同型態中部份的工作件經過製作鰭式裝置方法而具有源/汲極區的剖面示意圖。
第13圖係繪示出根據本揭露的不同型態中部份的工作件在經過製作鰭式裝置方法的立體示意圖。
第14A、15A、16A和17A圖係繪示出根據本揭露的不同型態中部份的工作件經過製作鰭式裝置方法而具有通道區的剖面示意圖。
第14B、15B、16B和17B圖係繪示出根據本揭露的不同型態中部份的工作件經過製作鰭式裝置方法而具有源/汲極區的剖面示意圖。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用 語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語涵蓋使用或操作中的裝置的不同方位。例如，若翻轉圖式中的裝置，描述為位於其他元件或特徵部件“下方”或“在...之下”的元件，將定位為位於其他元件或特徵部件“上方”。因此，範例的用語“下方”可涵蓋上方及下方的方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
第1圖係繪示出根據本揭露的不同型態中部分的 工作件100的透視圖。第1圖係簡化成讓本揭露的概念能更好說明與清楚的形式。額外的特徵部件可以附加到工作件100中，且在其它實施例的工作件100，以下所提及的某些特徵部件可以更換或移除。
工作件100包括一基底102或晶圓，其上形成一個 或多個鰭結構104。鰭結構104代表任何凸起的特徵部件，儘管描述的實施例具有鰭式場效電晶體鰭結構104，然而實施例可更進一步包括其它凸起的主動和被動裝置形成在基底102上。 描述的鰭結構104包括一N型通道(NMOS)鰭式場效電晶體106和一P型通道(PMOS)鰭式場效電晶體108。依序上，每一個鰭式場效電晶體106和108包括一對相對且摻雜不同半導體材料的源極/汲極區110以及設置在源極/汲極區110間的通道區112。載子(N型通道的電子與P型通道的電洞)流動通過通道區112是藉由對相鄰且包覆通道區112的閘極堆疊114施予一電壓來控制。為了繪示出下方的通道區，閘極堆疊114以透明化表 示。在所述的實施例中，通道區112在基底102的平面上凸起而形成於其上。因此，鰭結構104可以稱為一“非平面式”裝置。 和平面式裝置相比，凸起的通道區112有著更大的表面積，其表面積近似閘極堆疊114。這增強了閘極堆疊114和和通道區112間的電磁場交互作用，以減少微小裝置裡的漏電流和短通道效應。因此在許多實施例中，佔用面積較小的鰭式場效電晶體106和108和其它非平面式裝置與類似的平面式裝置比起來能達到更好的效能。
如以下的詳細說明，為了電性隔離對應的鰭式場 效電晶體106與108彼此，隔離特徵部件116形成於鰭結構104之間的基底102之上。一例示的特徵部件116包含在基底102之上形成的一襯層118以及於襯層118之上形成一填充材料120。隔離特徵部件116也可包含形成在填充材料120和基底102間的溝槽之內的應變產生結構122。在第1圖中，移除部分的填充材料120以顯露應變產生結構122，且移除部分在其下方的襯層118以顯露應變產生結構122。如同名字上所暗示的，應變產生結構122在其正上方的鰭結構104周圍部分製造應變。適宜的配置後，所增加的應變改善了載子流經應變部分時的遷移率。大體上來說，在通道區112上施加壓縮應變可以改善P型金屬氧化物半導體的載子遷移率，而在N型金屬氧化物半導體上則為施加伸張應變來改善載子遷移率。因此，在某些實施例中，應變產生結構122用以產生伸張應變且只形成於N型金屬氧化物半導體鰭式場效電晶體106的通道區112之下。
請參照第2A-17B圖，現在要敘述形成鰭式場效電 晶體106與108以及應變產生結構122的例示性方法。圖式是鰭式場效電晶體裝置106和108的通道區112(例如沿著平面124)及/或源極/汲極區110(例如沿著平面126)的剖面示意圖。第1圖繪示出平面124與126的剖面示意圖以作為參考。
第2A及2B圖係繪示出根據本揭露的不同型態中， 在工作件100上製作鰭式場效電晶體的方法200的流程圖。需要理解的是在其它的實施例中，可在方法200前、中、後增加額外的步驟，且上述的步驟可替換或移除。第3及4圖係在經過方法200的部份的工作件100，其為通道區112(沿著平面124)的剖面示意圖。在相對應地區塊202與區塊204的全部製程裡，源極/汲極區110和通道區112的流程本質上是相似的。為了避免不必要的複述，省略了大體上相似的源極/汲極區的剖面示意圖。不過在後續的製程裡，通道區112和源極/汲極區110都有繪示共剖面示意圖。據此，第5A、6A、7A、8A、9A、10A、11A、12A、14A、15A、16A及17A圖係繪示出根據本揭露的不同型態中沿著通道區112的(沿著平面124)部份的工作件100的剖面示意圖。第5B、6B、7B、8B、9B、10B、11B、12B、14B、15B、16B及17B圖係繪示出根據本揭露的不同型態中沿著源極/汲極區112的(沿著平面126)的部份的工作件100的剖面示意圖。第13圖係繪示出根據本揭露的不同型態中經過了方法200的部份的工作件100的立體透視圖。第3-17B圖簡化成讓本揭露的觀念可以更清楚說明的形式。
請先參照第2A圖的區塊202和第3圖，取得一包含 一基底102的工作件100。基底102可以分割成一用來形成一個 或多個N型金屬氧化物半導體鰭式場效電晶體的第一區，其稱之為N型金屬氧化物半導體區302；以及一用來形成一個或多個P型金屬氧化物半導體鰭式場效電晶體的第二區，其稱之為P型金屬氧化物半導體區304。N型金屬氧化物半導區302可鄰近於P型金屬氧化物半導區304或與其隔開，且各種隔離特徵部件(包含溝槽隔離特徵部件116)及/或虛置裝置可形成於兩區域之間。在以下所述的實施例細節裡，鰭式場效電晶體形成於N型金屬氧化物半導體區302及P型金屬氧化物半導體區304。然而可理解的是這些鰭式場效電晶體可代表任何凸起的結構，且實施例進一步包含其它凸起的主動和被動裝置形成於基底102之上。
在某些實施例中，基底102可包含兩層或是更多 層，如圖式中的基底層306和308。適合基底層306和308兩者或兩者其一的材料包含矽塊材。另外，基底層306和308可包括一元素半導體(單一元素)，例如結晶的矽或鍺；一化合物半導體，例如鍺化矽(silicon germanium)、碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide,)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)，或是其中的組合。基底102也可包含絕緣層上覆矽(silicon on insulator,SOI)結構。因此，基底層306和308兩者或兩者其一可包含一絕緣物，像是一半導體氧化物、一半導體氮化物、一半導體氮氧化物、一半導體碳化物、及/或其它適合的絕緣材料。絕緣層上覆矽基底用植氧分離(separation by implantation of oxygen,SIMOX)，晶圓接合及/ 或其它適合方法製得。在一例示性的實施例中，一第一基底層306包含鍺化矽，而一第二基底層包含單元素矽。(例如不含鍺或其他半導體的摻雜矽或未摻雜矽)。
基底層306和308可具有非均勻的組成。例如第3圖 中，第一基底層306包含一頂端部分310，其成分不同於底端部分312。此範例中，底端部分312包含的鍺化矽(SiGe)，其鍺濃度佔原子百分比約10%~30%，而頂端部分310包含的鍺化矽(SiGe)，其鍺濃度大於底端部分312，佔原子百分比約15%~60%。這些部分可以有任意的相對厚度。在此範例中，頂端部分310厚度(314箭號所指處)約30nm到100nm，底端部分312厚度(316箭號所指處)約1μm到3μm。基底層306和308的組成不但可用於調整基底層306和308的界面間產生的應變，還可用於平衡其它相關裝置的特性。例如，一鍺化矽(SiGe)半導體晶體因為含有鍺原子，所以和元素矽半導體晶體比起來有較大的本質間距(intrinsic spacing)。隨著鍺化矽(SiGe)中的鍺濃度越大，其間距也相對越大。有部分是因為這不同的間距，讓結晶矽結構與結晶鍺化矽結構間的界面(例如基底層306和308的界面)可用於在基底102與鄰近的結構內產生一內部應變。
可以看到，N型金屬氧化物半導體區302和P型金屬 氧化物半導體區304之間基底層306和308的組成可能不同。先前範例中，在N型金屬氧化物半導體區302，基底層306如同上述，其頂端部分310組成不同於底端部分312，然而在P型金屬氧化物半導體區304，基底層306為均勻組成，其矽化鍺的鍺濃度佔原子百分比約10%~30%。
為了方便製造與避免傷害基底層，一或多個硬罩 幕層318可形成於基底102其上。硬罩幕層318可包含一介電層，例如一半導體氧化物、一半導體氮化物、一半導體氮氧化物及/或一半導體碳化物，在一例示性的實施例中，硬罩幕層318包含一氧化矽層與一氮化矽層。硬罩幕318層可藉由熱成長、原子層沉積(atomic-layer deposition,ALD)、化學氣相沉積(chemical vapor deposition,CVD)、高密度電漿化學氣相沉積(high-density plasma CVD,HDP-CVD)、物理氣相沉積(physical vapor deposition,PVD)及/或其它適合的沉積製程形成。
一光阻層320可形成於硬罩幕層318之上，以在方 法200後續步驟中用於定義鰭結構104。一例示性的光阻層320包含一光敏材料，能使該光阻層經照光後而改變性質。性質改變後可用於微影圖案化製程中選擇性地移除曝光部份或未曝光部份的光阻。
請參照第2A圖的區塊204和第4圖，蝕刻部份的基 底102以定義出鰭結構104。在某些實施例中，包含圖案化光阻層320的微影技術。例如，在一實施例中，微影系統讓光阻層320在光罩的特定圖案下曝光。光穿透光罩或從光罩反射後擊中光阻層320，因而將光罩上的圖案轉移到光阻層320。在其它實施例中，光阻層320圖案化係藉由直寫微影技術或無光罩微影技術(例如，雷射圖案化、電子束圖案化及/或離子束圖案化)來圖案化。一旦曝光後，對光阻層320進行顯影只留下曝光的光阻部份，或在其它的實施例中，只留下沒有曝光的光阻部份。一例示性圖案化製程包含光阻層320的軟烘烤、光罩對準、 曝光、預曝光烘烤、光阻層320顯影、沖洗及乾燥(例如硬烘烤)。
在第4圖的實施例中，圖案化製程後只留下鰭結構 104正上方的光阻層320。將剩餘的光阻層移除以露出基底102要蝕刻的部分。因此，圖案化光阻層320後，在工作件100上可施行一或多個蝕刻製程，進而打開硬罩幕層318並蝕刻未覆蓋光阻層320的基底102及/或基底層306和308的部份。蝕刻製程可包含任何適合的蝕刻技術，例如乾蝕刻、濕蝕刻且/或其它蝕刻方法。(例如反應式離子蝕刻(reactive ion etching,RIE))。 在某些實施例中，蝕刻包含多道用不同化學蝕刻劑的蝕刻步驟，其中每一道步驟係針對工作件100上的某一特定材料。例如一實施例中，藉由以氟為基礎的蝕刻劑進行乾蝕刻而蝕刻基底102。
蝕刻係用於在延伸於基底102上的鰭結構104形成任意適合的長度、寬度。在本實施例的中，該製程完全蝕刻穿過第二基底層308和第一基底層306的頂端部份310(在N型金屬氧化物半導體區302)，但未蝕刻N型金屬氧化物半導體區302內第一基底層306的底端部分312。當然，這些深度僅為例示性。除了定義鰭結構104，在區塊204中，蝕刻也在鰭結構104間定義出一或多個隔離特徵部件溝槽402。之後溝槽402可填滿一介電材料以形成一隔離特徵部件116，例如淺溝槽隔離特徵部件(STI)。在蝕刻之後，可移除剩餘的光阻層320和硬罩幕層318。
請參照第2A圖的方塊206和第5A及5B圖，一第二硬罩幕層502形成於鰭結構104上。第二硬罩幕層502覆蓋P型金 屬氧化物半導體區304和N型金屬氧化物半導體區302的源極/汲極區110，但露出N型金屬氧化物半導體區302內的通道區112。這讓之後的應變產生結構122只形成於N型金屬氧化物半導體裝置的通道區112的下面，而不會在其它任何地方形成。 第二硬罩幕層502可包含任意適合的介電層，一例示性的第二硬罩幕層502包含一半導體氮化物。為了只露出N型金屬氧化物半導體通道區112，第二硬罩幕層502可跨越N型金屬氧化物半導體區302和P型金屬氧化物半導體區304兩者的鰭結構104，然後再自N型金屬氧化物半導體通道區112選擇性蝕刻或以其他方法移除。在一實施例中，在第二硬遮蔽層502沉積在N型金屬氧化物半導體區302和P型金屬氧化物半導體區304兩區上之後，一光阻層沉積在第二硬罩幕層502之上。微影圖案化光阻層，以露出N型金屬氧化物半導體通道區112內需蝕刻的第二硬罩幕層502的部份。之後自N型金屬氧化物半導體通道區112移除第二硬罩幕層502的部份，並可剝除剩下的光阻層。
請參照第2A圖的區塊208和第6A及6B圖，在第二 硬罩幕層502露出基底102的部份上形成一介電層，以形成應變產生結構122。介電層材料可包含任何適合的介電質，在某些例示性實施例中，其包含一半導體氧化物。因此在一實施例中，N型金屬氧化物半導體區302的通道區112內第一基底層306露出的部份係氧化形成應變產生結構122。氧化或其它介電質形成技術可改變基底102上的晶格結構及/或間距，且可用來形成或減輕鰭結構104上的應變。特別當第一基底層306具有鍺化矽而第二基底層具有元素矽時，選擇性地氧化第一層306會傳 給鰭結構104鄰近的區域一伸張應變。這使得鰭結構104更適用於N型金屬氧化物半導體鰭式場效電晶體。為此與其它理由，介電質形成製程可藉由第二硬罩幕層502受限於N型金屬氧化物半導體區302的通道區112。在上述的實施例中，應變產生結構122形成於第一基底層306的垂直表面且可形成於鰭結構104之間的第一基底層306的水平表面。
氧化基底102可用任何適合的氧化製程，且在一例 示性實施例中使用濕氧化製程，因其傾向於選擇性地氧化第一基底層306內的鍺而不氧化第二基底層308內的矽。例如，加熱工作件100且維持在約400℃和500℃之間，同時在1大氣壓的環境時提供基底102純水(蒸氣)反應約30分至1小時。此氧化技術形成鍺化矽氧化物應變產生結構122於N型金屬氧化物半導體區302的通道區112內隔離特徵部件溝槽402裡。別處的第二硬罩幕層502避免第一基底層306的氧化，以使應變產生結構122不會形成在N型金屬氧化物半導體區302裡的源極/汲極區110或P型金屬氧化物半導體區304的任何地方。應變產生結構122可長成任意適合的厚度，在各種例示性實施例中，從基底102的水平或垂直表面垂直量測的最厚厚度約在3nm到10nm之間。應變產生結構122形成後，可移除第二硬罩幕層502。
請參照第2A圖的區塊210與第7A及7B圖，一襯層 118形成於基底102之上，且形成於鰭結構104與應變產生結構122兩者之上。襯層118減少基底102與介電填充材料的界面之間晶格的缺陷，其包含任何適合的材料，其中有一半導體氮化物、一半導體氧化物、一熱半導體氧化物、一半導體氮氧化物、 一介電聚合物及/或其它適合的材料；且可用任何適合的沉積製程形成，有熱成長、原子層沉積(ALD)、化學氣相沉積(CVD)、高密度電漿化學氣相沉積(HDP-CVD)、物理氣相沉積(PVD)及/或其它適合的沉積製程。在某些實施例中，襯層118包括由熱氧化製程形成的一傳統熱氧化襯層。在某些例示性實施例中，襯層118包括由高密度電漿化學氣相沉積法所形成的一半導體氮化物。
請參照第2A圖的區塊212與第8A及8B圖，一淺溝 槽隔離填充材料120或介電填充質沉積於隔離特徵部件溝槽402內，以更進一步定義隔離特徵部件116。適合的填充材料120包括一半導體氧化物、一半導體氮化物、一半導體氮氧化物、摻氟矽玻璃(FSG)、低介電係數介電材料及/或其中的組合。在不同實施例中，填充材料120藉由一高密度電漿化學氣相沉積製程、一負壓化學氣相層積(sub-atmospheric CVD,SACVD)、一高縱深比填溝製程(high-aspect ratio process,HARP)及/或旋轉塗布製程。在一實施例中，以一化學氣相沉積法沉積一具流動性的介電材料，其包含一介電填充材料120與一液態或半液態的溶劑。利用一烘烤製程除去溶劑，留下固態的介電填充材料120。
沉積填充材料120之後可施行一化學機械研磨/平 坦(chemical mechanical polishing/planarization,CMP)製程。在本實施例中，化學機械研磨製程完全地將襯層118最頂端的部份從鰭結構104上移除。而在其它實施例中，在經過化學機械研磨製程後仍在鰭結構104的頂端部份保留部份的襯層118。
請參照第2A圖的區塊214與第9A及9B圖，一第三 硬罩幕層902形成於N型金屬氧化物半導體區302上，以選擇性加工P型金屬氧化物半導體區304。例示性的第三硬罩幕層902材料包含一介電層，例如一半導體氧化物、一半導體氮化物、一半導體氮氧化物及/或一半導體碳化物，且在一例示性實施例裡，第三硬罩幕層902包含一半導體氧化物與一半導體氮化物。第三硬罩幕層902可藉由熱成長、原子層沉積(ALD)、化學氣相沉積(CVD)、高密度電漿化學氣相沉積(HDP-CVD)、物理氣相沉積(PVD)及/或其它適合的沉積製程形成。在某些實施例中，該第三硬罩幕層902沉積於N型金屬氧化物半導體區302與P型金屬氧化物半導體區304兩者之上，然後選擇性地從P型金屬氧化物半導體區304移除。
請參照第2A圖的區塊216與第9A及9B圖，P型金屬 氧化物半導體區304內有部份基底102凹陷，而第三硬罩幕層902保護N型金屬氧化物半導體區302內的基底102。任何的蝕刻技術可用於凹蝕P型金屬氧化物半導體區304內的第二基底層308，包含乾蝕刻、濕蝕刻、反應式離子蝕刻(RIE)及/或其它蝕刻方法，且在一例示性實施例中，一乾蝕刻技術利用含氟氣體(例如CF2)選擇性地蝕刻第二基底層308而不蝕刻其周圍結構。在蝕刻之後，可餘留部份的第二基底層308，且在各種實施例中，餘留的第二基底層308厚度約5nm到25nm。
在區塊216中，凹蝕基底102也可包含凹蝕P型金屬 氧化物半導體區304內部分的襯層118。藉由凹蝕襯層108，第二基底層308供磊晶成長的表面積增加，藉以提供第二基底層 308與之後形成的膜層之間較好接合。任何的蝕刻技術可用於凹蝕該襯層118，包含乾蝕刻、濕蝕刻、反應式離子蝕刻(RIE)及/或其它蝕刻方法，且在一例示性實施例中，一濕蝕刻技術利用氫氟酸選擇性地移除襯層108而不蝕刻其周遭結構。襯層108可凹蝕甚於第二基底層308，且在本實施例中，在蝕刻之後，襯層108的頂端表面低於該第二基底層308的頂端表面。
請參照第2B圖的區塊218與第10A及10B圖，一第三 基底層1002形成於P型金屬氧化物半導體區304內的第二基底層308之上。如同第一與第二基底層，該第三基底層1002可包含一元素(單一元素)半導體、一化合物半導體、一介電層、或其組合。在各種例示性實施例中，該第三基底層1002包含鍺化矽，其鍺濃度佔原子百分比約45%~100%。在其他實施例中，第三基底層1002包含摻雜或未摻雜鍺且不含矽的鍺化物(例如一單元素鍺化物半導體)。第三基底層1002可用任何適合的方法沉積，包含磊晶成長、原子層沉積(ALD)、化學氣相沉積(CVD)且/或物理氣相沉積(PVD)，而且可形成任何適合的厚度。在某些例示性範例實施例中，第三基底層1002的厚度約20nm到40nm。
在襯層108中凹蝕甚於第二基底層308的實施例 中，第三基底層1002可沉積在第二基底層308的三個或更多的表面上(一水平的頂端表面與兩垂直的側表面)。此增加第二基底層308與第三基底層1002之間的接合面積，可減少兩者界面的空隙與其它界面缺陷的發生。在沉積第三基底層1002之後可實施一化學機械研磨製程(CMP)，以移除介電填充物之上的材 料。在沉積第三基底層1002之後，可從N型金屬氧化物半導體區302移除第三硬罩幕層902，且可以化學機械研磨(CMP)或其他適合的技術來實施。
請參照第2B圖的區塊220與第11A及11B圖，凹蝕介 電材料120。在N型金屬氧化物半導體區302內，凹蝕製程也可包含凹蝕部份襯層108。在此實施例中，N型金屬氧化物半導體區302內襯層108凹蝕更甚於填充材料120，使得N型金屬氧化物半導體區302內襯層108的頂端表面低於該區域的填充材料120的頂端表面。填充材料120的頂端表面與襯層108的頂端表面之間的差距可藉由微調蝕刻技術控制，且在各種實施例中，其差距範圍約3nm到10nm。任何適合的蝕刻技巧可用於凹蝕填充材料120及/或襯層108，包含乾蝕刻、濕蝕刻、反應式離子蝕刻(RIE)及/或其它蝕刻方法，且在一例示性實施例中，用非等向性乾蝕刻選擇性地移除填充材料120而不蝕刻其它基底層。
請參照第2B圖的區塊222與第12A及12B圖，一介電 層1202形成於鰭結構104與填充材料120之上。介電層1202可有多重功能，包含填滿因凹蝕N型金屬氧化物半導體區302內襯層108所留下的間隙。介電層1202也可作為部份的虛置閘極結構。因此，為了在形成源極/汲極特徵部件1502過程中保護鰭結構104的通道區112，一虛置閘極可形成於N型金屬氧化物半導體區302及/或P型金屬氧化物半導體區304的通道區112上。 因此在一實施例中，設置於通道區112內的介電層1202的部份係一虛置閘極介電質。介電層1202可包含任何適合的介電材料，例如一半導體氧化物、一半導體氮化物、一半導體碳化物、 一半導體氮氧化物、其它適合的材料及/或其組合，且在一實施例中，上述介電材料包含與填充材料120一樣的材料與組成。
請參照第2B圖的區塊224與第13圖，虛置閘極1302 剩餘的結構，例如一虛置閘極層1304，一虛置閘極硬罩幕層1306及/或閘極間隙壁1308，形成於介電層1202之上。對於更細節的部份，形成虛置閘極1302可包含沉積含有多晶矽或其他適合材料的虛置閘極層1304，且用一微影製程圖案化虛置閘極層1304。之後，虛置閘極硬罩幕層1306可形成於虛置閘極層1304之上，且包含任何適合的材料，例如一半導體氧化物、一半導體氮化物、一半導體碳化物、一半導體氮氧化物，其它適合的材料及/或其組合。
在某些實施例中，閘極間隙壁1308或側壁間隙物 形成於虛置閘極1302的每一側上(位於虛置閘極1302的每一側壁上)。閘極間隙壁1308可用於偏移之後形成的源極/汲極特徵部件1502且可用於設計或修改該源極/汲極結構(接面)輪廓。閘極間隙壁1308可包含任何的介電材料，例如一半導體氧化物、一半導體氮化物、一半導體碳化物、一半導體氮氧化物、其它適合的材料及/或其組合。
請參照第2B圖的區塊226與第14A及14B圖，蝕刻介 電層1202與源極/汲極區110內的一或多個基底層。對於介電層1202，為了控制與對準源極/汲極特徵部件1502的磊晶成長，上述蝕刻技術可留下一部份延伸於基底層頂端表面的介電層1202。這可以藉由使用非等向性蝕刻技巧，使介電層1202的水平面蝕刻的速度快於垂直面。關於基底層，在蝕刻N型金屬氧 化物半導體區302中，上述蝕刻留下一部分餘留的第二基底層308，以作為一磊晶成長製程的晶種層。在P型金屬氧化物半導體區304裡，上述蝕刻留下一部分餘留的第三基底層1002作為一磊晶成長製程的晶種層。在其它實施例中，蝕刻可從P型金屬氧化物半導體區304裡的源極/汲極區110完全移除第三基底層1002，留下一部分的第二基底層308作為晶種層。上述蝕刻可為單一蝕刻製程及使用各種蝕刻劑或技術的多重蝕刻製程，且在各種實施例中，上述蝕刻製程包含乾蝕刻(如同先前提到的非等向性乾蝕刻技術)、濕蝕刻、反應式離子蝕刻(RIE)及/或其它蝕刻方法。
請參照第2B圖的區塊228與第15A及15B圖，凸起的 源極/汲極特徵部件1502形成於基底層(例如，N型金屬氧化物半導體區302內的第二基底層302與P型金屬氧化物半導體區304內的第三基底層1002等等)上。虛置閘極1302及/或閘極間隙壁1308把源極/汲極特徵部件1502受限於源極/汲極區110，且介電層1202把源極/汲極特徵部件1502水平地受限於源極/汲極區110。在許多實施例中，源極/汲極特徵部件1502藉由一或多道磊晶製程，藉由矽特徵部件、鍺化矽特徵部件及/或其他適合的特徵部件在鰭結構104上成長為一晶體狀態。適合的磊晶製程包含化學氣相沉積技術(例如蒸汽相磊晶(vapor-phase epitaxy,VPE)及/或超高真空化學氣相沉積(ultra-high vacuum CVD,UHV-CVD))、分子束磊晶及/或其它適合製程。磊晶製程可用氣態及/或液態的前驅物，其與鰭結構104的組成內容物反應。
源極/汲極特徵部件1502可在磊晶製程期間進行原 位摻雜，植入的摻雜物包含：p型摻雜質，例如硼或氟化硼(BF2)；n型摻雜質，例如磷或砷及/或其它適合的摻雜質包含上述之組合。如果源極/汲極特徵部件1502未施行原位摻雜，可施行一離子植入製程(即，一接面佈植製程)摻雜源極/汲極特徵部件1502。在一例示性實施例中，在N型金屬氧化物半導體區302內的源極/汲極特徵部件1502包含磷化矽(SiP)，而在P型金屬氧化物半導體區304的源極/汲極特徵部件1502包含鍺錫硼化合物(GeSnB)(錫可用於微調晶格)及/或矽鍺錫硼化合物(SiGeSnB)。可實施一或多個退火製程以活化源極/汲極特徵部件1502。適合的退火製程包含快速降熱退火(rapid thermal annealing,RTA)及/或雷射退火製程。
請參照第2B圖的區塊230與第16A及16B圖，一內層 介電質(inter-level dielectric,ILD)1602形成於源極/汲極區110的源極/汲極特徵部件1502之上。內層介電層1602可環繞虛置閘極1302及/或閘極間隙壁1308，以移除這些特徵部件且一置換閘極114可形成在後來形成的凹口內。因此，在上述的實施例中，如第16A圖所示，沉積內層間介電層1602之後，移除虛置閘極1302。內層介電層1602可為電性內連接結構的一部分，其電性連接工作件100的裝置，包含鰭式場效電晶體106與108。在上述的實施例中，內層介電層1602作為一絕緣體，其支撐並隔離導電走線。內層介電層1602可包含任何適合的介電材料，例如一半導體氧化物、一半導體氮化物、一半導體碳化物、一半導體氮氧化物、其它適合的材料及/或其組合。
請參照第2B圖的區塊232與第17A及17B圖，一閘極 堆疊114形成於工作件100上，且包覆鰭結構104的通道區112。 雖然我們可以理解的是閘極堆疊114可以為任何的閘極結構，在某些實施例中，閘極堆疊114為高介電常數金屬閘極，其包含一界面層1702、一閘極介電層1704以及一金屬閘極層1706，其中每一層可包含數個次層。
在一實施例中，界面層1702可藉由適合的方法沉 積，例如原子層沉積(ALD)、化學氣相沉積(CVD)、臭氧氧化法等等。界面層1702可包含一氧化物、矽酸鉿(HfSiO)、一矽化物、一氮氧化物、及或其它適合的材料。接著，一高介電常數閘極介電層1704藉由適合方法沉積於界面層1702之上，例如原子層沉積(ALD)、化學氣相沉積(CVD)、有機金屬化學氣相沉積(metal-organic CVD,MOCVD)、物理氣相沉積(PVD)、熱氧化、其中的組合及/或其它適合的技術。高介電常數層1704可包含氧化鑭(LaO)、氧化鋁(AlO)、氧化鋯(ZrO)、氧化鈦(TiO)、氧化鉭(Ta2O5)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3,STO)、鈦酸鋇(BaTiO3,BTO)、鋯酸鋇(BaZrO)、鉻酸鉿(HfZrO)、鑭酸鉿(LaSiO)、矽酸鉿(HfSiO)、矽酸鑭(LaSiO)、矽酸鋁(AlSiO)、鉭酸鉿(HfTaO)、鈦酸鉿(HfTiO)、鈦酸鍶鋇((Ba,Sr)TiO3,BST)、氧化鋁(Al2O3)、氮化矽(Si3N4)、氮氧化矽(SiON)或其它適合的材料。
而後藉由原子層沉積(ALD)、化學氣相沉積 (CVD)、物理氣相沉積(PVD)或其它適合的製程形成一金屬閘極層1706，且其可包含單層或多層，例如一金屬層、一襯層、 一潤濕層及/或一黏著層。金屬閘極層1706可包含鈦、銀、鋁、氮化鋁鈦(TiAlN)、碳化鉭(TaC)、氰化鉭(TaCN)、鉭化矽(TaSiN)、錳、鋯、氮化鈦(TiN)、氮化鉭(TaN)、釕、鉬、鋁、氮化鎢(WN)、銅、鎢或任何適合的材料。在某些實施例中，不同的金屬閘極材料可用於N型金屬氧化物半導體和P型金屬氧化物半導體的裝置。可施行一化學機械研磨製程以在閘極堆疊114上形成一大抵平坦的頂端表面。形成閘極堆疊114後，可進一步製造工作件100，例如接觸窗的形成或更進一步製造內連線結構。
因此，本發明提供一技術，其藉由在通道區下形 成一應變產生結構，以提升非平面半導體裝置的通道應變。在某些實施例中，提供一種積體電路裝置，其包括基底、以及個別形成於基底之上的第一鰭結構及第二鰭結構。基底具有隔離特徵特徵部件溝槽定義於第一鰭結構及第二鰭結構之間。積體電路裝置也包括應變特徵部件，其設置於隔離特徵部件內的基底的水平面之上及填充介電質，形成於隔離特徵部件溝槽內的應變特徵部件之上。在某些實施例中，應變特徵部件更設置於第一鰭結構的垂直表面及第二鰭結構的垂直表面之上。在某些實施例中，應變特徵部件之配置係用於在第一鰭結構上形成的電晶體的通道區之上產生應變。在某些實施例中，積體電路裝置也包括第三鰭結構設置於基底之上，其具有P型通道裝置設置於第三鰭結構之上。第三鰭結構具有設置於該基底之上的第一層、設置於第一層之上的第二層及設置於該第二層的至少三個表面上的第三層。
在其它實施例中，提供一種半導體裝置，其包括 基底及從基底垂直延伸的鰭。鰭包括兩或多個源極/汲極區及設置於上述的兩或多個源極/汲極區之間的通道區。半導體裝置也包括隔離特徵部件，其設置於鄰近鰭的基底之上，其包括設置於鰭的一側表面與基底的頂端表面之上的襯層及設置於襯層之上的填充材料。填充材料具有背向基底的頂端表面，其中襯層設置於遠離填充材料的頂端表面。在某些實施例中，半導體裝置更包括應變特徵部件，其設置於鰭的半導體材料與襯層之間的鰭的側表面之上。在某些實施例中，鰭包括設置於基底之上的第一半導體層、設置於第一半導體層之上的第二半導體層及設置於第二半導體層的至少三個表面之上的第三半導體層，其中第二半導體層的組成不同於第一半導體層及第三半導體層。
在其它的實施例中，提供一種半導體裝置的製造 方法。上述方法包括取得一工作件，其具有形成於工作件之上的鰭，其中鰭包括第一半導體部分及組成不同於第一半導體部分的第二半導體部分。在鰭結構的通道區內的第一半導體部分之上選擇性地形成應變產生結構。在應變產生結構之上形成隔離特徵部件。在鄰近通道區的一對源極/汲極區內凹蝕第二半導體部分。在上述成對的源極/汲極區內的凹陷的第二半導體部，磊晶成長源極/汲極結構。在某些實施例中，選擇性地形成應變產生結構更包括氧化鰭結構的通道區內第一半導體部分，以形成包括半導體氧化物的應變結構。
以上敘述許多實施例的特徵，使所屬技術領域中 具有通常知識者能夠清楚理解以下的說明。所屬技術領域中具有通常知識者能夠理解其可利用本發明揭示內容作為基礎，以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解不脫離本發明之精神和範圍的等效構造可在不脫離本發明之精神和範圍內作任意之更動、替代與潤。
100‧‧‧工作件
102‧‧‧基底
104‧‧‧鰭結構
106‧‧‧N型通道鰭式場效電晶體
108‧‧‧P型通道鰭式場效電晶體
110‧‧‧源極/汲極區
112‧‧‧通道區
116‧‧‧隔離特徵部件
118‧‧‧襯層
120‧‧‧填充材料
122‧‧‧應變產生結構
1202‧‧‧介電層
1302‧‧‧虛置閘極
1304‧‧‧虛置閘極層
1306‧‧‧虛置閘極硬罩幕層
1308‧‧‧閘極間隙壁

Claims (10)

  1. 一種積體電路裝置，包括：一基底；一第一鰭結構和一第二鰭結構，個別設置於該基底之上且具有一隔離特徵特徵部件溝槽定義於其間；一應變特徵部件，設置於該隔離特徵部件溝槽內的該基底的一水平表面之上；及一填充介電質，設置於該隔離特徵部件溝槽內的該應變特徵部件之上。
  2. 如申請專利範圍第1項所述之積體電路裝置，其中該應變特徵部件更設置於該第一鰭結構的一垂直表面及該第二鰭結構的一垂直表面之上，其配置係用於在形成於該第一鰭結構上的一電晶體的一通道區產生一應變。
  3. 如申請專利範圍第1項所述之積體電路裝置，更包括一襯層，設置於該應變特徵部件和該填充介電質之間，其中該襯層與該填充介電質的一頂端表面隔開，且該隔離特徵部件溝槽內的一隔離特徵部件包括一介電材料，其位於該隔離特徵部件的一頂端表面和該襯層的一頂端表面之間。
  4. 如申請專利範圍第1項所述之積體電路裝置，更包括一第三鰭結構，設置於該基底之上，且具有一P型通道裝置設置於其上，其中該第三鰭結構具有一第一層設置於該基底之上、一第二層設置於該第一層之上以及一第三層設置於該第二層的至少三個表面上，其中該第一層包括SiGe，該第二層包括元素Si，且該第三層包括SiGe。
  5. 一種半導體裝置，包括：一基底；一鰭，從該基底垂直延伸且包括二或多個源極/汲極區及形成於該二或多個源極/汲極區之間的一通道區；及一隔離特徵部件，設置於鄰近該鰭的該基底之上，其中該隔離特徵部件包括：一襯層，形成於該鰭的一側表面與該基底的一上表面之上；及一填充材料，設置於該襯層之上，且具有背向該基底的一頂端表面，其中該襯層設置於遠離該填充材料的該頂端表面。
  6. 如申請專利範圍第5項所述之半導體裝置，更包括一應變特徵部件，設置於該鰭的一半導體材料與該襯層之間的該鰭的該側表面之上，且設置於該基底的一半導體材料與該襯層之間的該基底的該上表面之上，其配置係用於在該鰭的該通道區內產生一通道應變，且該通道應變為一張力應變，該鰭包括一N型通道裝置形成於其上，且該N型通道裝置包括該通道區及該二或多個源極/汲極區。
  7. 如申請專利範圍第5項所述之半導體裝置，其中該鰭包括一第一半導體層設置於該基底之上、一第二半導體層設置於該第一半導體層之上以及一第三半導體層設置於該第二半導體層的至少三個表面之上，且其中該第二半導體層的組成不同於該第一半導體層及該第三半導體層。
  8. 一種半導體裝置的製造方法，該方法包括： 取得一工作件，具有一鰭結構形成於其上，其中該鰭結構包括一第一半導體部及組成不同於該第一半導體部的一第二半導體部；在該鰭結構的通道區內的該第一半導體部之上選擇性地形成一應變產生結構；在該應變產生結構之上形成一隔離特徵部件；在鄰近該通道區的一對源極/汲極區內凹陷該第二半導體部；及在該對源極/汲極區內的該凹陷的第二半導體部，磊晶成長源極/汲極結構。
  9. 如申請專利範圍第8項所述之半導體裝置的製造方法，其中選擇性地形成該應變產生結構包括形成一硬罩幕層於露出該通道區的該鰭結構之上及氧化該鰭結構的該通道區內的該第一半導體部，以形成包括一半導體氧化物的該應變產生結構。
  10. 如申請專利範圍第8項所述之半導體裝置的製造方法，其中選擇性地形成該應變產生結構更包括沿著一水平表面形成該應變產生結構的一部分且延伸於該鰭結構與另一鰭結構之間。
TW104111743A 2014-08-05 2015-04-13 半導體裝置及其製造方法及積體電路裝置 TWI578498B (zh)

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