TWI675486B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

Info

Publication number
TWI675486B
TWI675486B TW106118724A TW106118724A TWI675486B TW I675486 B TWI675486 B TW I675486B TW 106118724 A TW106118724 A TW 106118724A TW 106118724 A TW106118724 A TW 106118724A TW I675486 B TWI675486 B TW I675486B
Authority
TW
Taiwan
Prior art keywords
gate
layer
material layer
dielectric material
dielectric
Prior art date
Application number
TW106118724A
Other languages
English (en)
Other versions
TW201824564A (zh
Inventor
江國誠
梁英強
徐志安
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201824564A publication Critical patent/TW201824564A/zh
Application granted granted Critical
Publication of TWI675486B publication Critical patent/TWI675486B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本揭露提供一種半導體結構及其製造方法。半導體結構包括：基板上之鰭片結構；形成在鰭片結構上之第一閘極堆疊及第二閘極堆疊；設置在第一閘極堆疊及第二閘極堆疊上之介電質材料層，其中介電質層包括設置在具有第一厚度之第一閘極堆疊之側壁上之第一部分，及設置在具有大於第一厚度之第二厚度之第二閘極堆疊之側壁上之第二部分；設置在介電質材料層之第一部分上之第一閘極間隔層；以及設置在介電質材料層之第二部分上之第二閘極間隔層。

Description

半導體結構及其製造方法
本揭露是關於一種半導體結構及其製造方法。
半導體積體電路(integrated circuit；IC)行業已經經歷了快速的成長。積體電路材料及設計之技術進步已經生產了數代IC，其中每一代都具有比上一代更小及更複雜的電路。在積體電路進化的過程中，功能密度(即，單位晶片面積之互連元件之數目)普遍隨著幾何尺寸(即，使用製造製程可製造之最小元件(或線路)減小而增加。尺寸的縮小提供了諸多好處，例如產品效能以及降低成本。為實現這些優勢，尺寸的縮小亦增加製程及生產之複雜性。IC處理及製造中的類似發展是具有需求的。例如，諸如鰭狀場效電晶體(fin-like field-effect transistor；FinFET)之三維電晶體已經引入以替換平面電晶體。鰭狀場效電晶體可看作為延伸進閘極中之典型平面元件。典型鰭狀場效電晶體經製造有自基板向上延伸之薄「鰭片」(或鰭片結構)。在此垂直鰭片中形成之場效電晶體之通道，及在此鰭片之通道區上方(例如，捲繞)設置閘極。包裹圍繞閘極之鰭片增大了通 道區與閘極之間之接觸面積並允許閘極自多個側面控制此通道。此構造可以以多種方式及在一些應用中被利用，鰭狀場效電晶體提供了減小短通道效應、降低洩漏及提高電流。換言之，他們可比平面元件更快、更小及更高效。
然而，由於鰭狀場效電晶體及其他非平面元件之固有複雜性，及進一步在進階技術模式中之高圖案密度，用於製造平面電晶體之多種方式並不能很好地適用於製造非平面元件。僅舉一例，用於在半導體基板上形成閘極堆疊之習知技術可產生不當的黏附問題。在此進階技術節點中，需要極高的電晶體閘極之高度。例如，當閘極長度小於20奈米時，定義為閘極高度比閘極寬度之閘極深寬比可大於15。此高閘極深寬比可能導致鄰接閘極黏附在一起，尤其在各種製程期間，諸如濕式蝕刻及清洗。現有方法，諸如藉由應力管理方法執行之處理製程，並不能與具有諸如大於17之高閘極深寬比的產品一起高效工作。
因此，儘管現有製造技術普遍對平面元件已經足夠，但為了繼續滿足不斷增加之設計要求，需要進一步的發展。
本揭露的一實施態樣包括一種半導體結構。半導體結構包括：基板上之鰭片結構；形成在此鰭片結構上之第一閘極堆疊及第二閘極堆疊；設置在此第一閘極堆疊及第二閘極堆疊上之介電質材料層，其中此介電質層包括設置在具 有第一厚度之第一閘極堆疊之側壁上之第一部分，以及設置在具有大於此第一厚度之第二厚度之第二閘極堆疊之側壁上之第二部分；設置在此介電質材料層之第一部分上之第一閘極間隔層；以及設置在此介電質材料層之第二部分上之第二閘極間隔層。
本揭露的另一實施態樣包括一種半導體結構。半導體結構包括：設置在第一鰭片結構上之第一場效電晶體(FET)，其中此第一場效電晶體進一步包括第一閘極堆疊、設置在第一閘極堆疊之兩個側面上之第一源/汲極特徵、設置在此第一閘極堆疊之側壁上之第一閘極間隔層及插入在第一閘極間隔層與第一閘極堆疊之側壁之間之第一介電質材料層；以及設置在第二鰭片結構上之第二場效電晶體，其中此第二場效電晶體進一步包括第二閘極堆疊，設置在第二閘極堆疊之兩個側面上之第二源/汲極特徵，設置在第二閘極堆疊之側壁上之第二閘極間隔層，及插入在第二閘極間隔層與第二閘極堆疊之側壁之間之第二介電質材料層。第一介電質材料層具有第一厚度T1，及第二介電質材料層具有大於第一厚度之第二厚度T2。
本揭露的又一實施態樣包括一種半導體結構之製造方法。此方法包括在半導體基板上形成虛設閘極；在半導體基板上形成層間介電質層(ILD)；移除虛設閘極，進而在層間介電質層中產生閘極溝槽；在閘極溝槽中形成介電質材料層使得介電質材料層被設置在閘極溝槽之側壁上且免於位在閘極溝槽之底表面上；及在閘極溝槽中形成金屬閘 極，進而此金屬閘極藉由介電質材料層之厚度橫跨的一尺寸小於虛設閘極之對應尺寸。
100‧‧‧工件
102‧‧‧基板
104‧‧‧鰭片結構
106‧‧‧核心元件
108‧‧‧輸出入元件
110‧‧‧源/汲極特徵
112‧‧‧通道區
114A、114B‧‧‧閘極堆疊
116‧‧‧隔離特徵
122、124、126、128、130‧‧‧平面
200‧‧‧方法
202、206、208、210、212、214、216、218、220、222、224‧‧‧步驟
252‧‧‧毒化製程
254‧‧‧第一化學處理
256‧‧‧第二化學處理
258‧‧‧清洗製程
260‧‧‧乾燥製程
262‧‧‧沉積步驟
264‧‧‧步驟
402‧‧‧半導體層
404‧‧‧硬遮罩層
502‧‧‧隔離溝槽
702‧‧‧溝槽
802‧‧‧介電質材料層
902‧‧‧虛設閘極
904‧‧‧閘極硬遮罩層
1002‧‧‧閘極側壁特徵
1002A‧‧‧密封層
1002B‧‧‧閘極間隔層
1102‧‧‧層間介電質層
1104‧‧‧空腔
1202、1204‧‧‧切割線
1212、1214‧‧‧介電質材料層
1402、1404‧‧‧切割線
1406‧‧‧抗蝕劑層
1502、1504‧‧‧切割線
1602‧‧‧閘極介電質層
1604‧‧‧閘電極
1702‧‧‧蓋層
1704‧‧‧阻擋層
1706‧‧‧功函數金屬層
1708‧‧‧阻擋層
1710‧‧‧填充金屬層
T1、T2、Tg1、Tg2‧‧‧厚度
Lg1、Lg2‧‧‧尺寸
當結合附圖閱讀時，自以下詳細描述很好地理解本揭露之態樣。應當注意，根據工業中標準實務，各特徵未按比例繪製。事實上，為論述清楚，各特徵之尺寸可任意地增加或縮小。
第1圖為根據一些實施例構建之半導體結構的透視圖。
第2圖為根據一些實施例之積體電路製造方法的流程圖。
第3圖至第11圖為根據一些實施例構建之半導體結構在各製造階段的透視圖。
第12A圖及第12B圖為根據一些實施例構建之半導體結構在一製造階段的透視圖。
第12C圖及第12D圖為根據一些實施例構建之第12A圖及第12B圖中之半導體結構的截面圖。
第13圖為根據一些實施例之積體電路製造方法的流程圖。
第14A圖及第14B圖為根據一些實施例構建之半導體結構在一製造階段的透視圖。
第14C圖及第14D圖為根據一些實施例構建之第13A圖及第131B圖中之半導體結構的截面圖。
第15A圖及第15B圖為根據一些實施例構建之半導體結構在一製造階段的透視圖。
第15C圖及第15D圖為根據一些實施例構建之第14A圖及第14B圖中之半導體結構的截面圖。
第16圖為根據一些實施例構建之第15A圖及第15B圖中之半導體結構的截面圖。
第17圖為根據一些實施例構建之第16圖中之半導體結構之閘電極的截面圖。
本揭露大體係關於積體電路元件製造，及更具體而言，係關於隔離鰭狀場效電晶體與在其上形成之基板之絕緣層及係關於調變藉由此絕緣層產生之通道應變以適合鰭狀場效電晶體之通道類型。
以下揭示內容提供許多不同實施例或實例，以便實現各個實施例之不同特徵。下文描述組件及排列之特定實例以簡化本揭露。當然，此等實例僅為實例且不意欲為限制性。舉例而言，在隨後描述中在第二特徵上方或在第二特徵上第一特徵之形成可包括第一及第二特徵形成為直接接觸之實施例，以及亦可包括額外特徵可形成在第一及第二特徵之間，使得第一及第二特徵可不直接接觸之實施例。另外，本揭露在各實例中可重複元件符號及/或字母。此重複為出於簡單清楚之目的，且本身不指示所論述各實施例及/或配置之間之關係。
另外，空間相對用語，諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者，在此為便於描述可用於描述諸圖中所圖示一個元件或特徵與另一(些)元件或(多個)特徵之關係。除圖形中描繪之方向外，空間相對用語意圖是包含元件在使用或操作中之不同的方向。舉例而言，如若圖中裝置翻轉，描述為位於其他元件或特徵之下方或上方之元件將經定向於另一個元件或特徵之上方。因而，示例性術語「以下」可包含上方及下方之兩者方向。裝置可為不同朝向(旋轉90度或在其他的方向)及在此使用之空間相對的描述詞可因此同樣地解釋。
本揭露涉及但並不限於鰭狀場效電晶體(FinFET)元件。例如，鰭狀場效電晶體元件可為互補金屬氧化物半導體(complementary metal-oxide-semiconductor；CMOS)元件，其包括P型金屬氧化物半導體(metal-oxide-semiconductor；PMOS)鰭狀場效電晶體元件及N型金氧氧化物半導體(metal-oxide-semiconductor；NMOS)鰭狀場效電晶體元件。以下本揭露將繼續使用鰭狀場效電晶體實例來說明本揭露之各實施例。然而，應理解，不應將此申請案限制於元件之特定類型，除非作出特別主張。
第1圖為根據本揭露之各態樣之工件100之部分的透視圖。為清晰及更好地圖說明本揭露之原理起見，簡化了第1圖。額外特徵可併入工件100，及下文描述之特徵之一些可在工件100之其他實施例中替換或除去。
工件100包括基板102。基板102包括塊矽基板。或者，基板102可包括元素半導體，諸如晶體結構中之矽或鍺；化合物半導體，諸如矽化鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；或上述各者之組合。可能的基板102亦包括絕緣體上矽(silicon-on-insulator；SOI)基板。絕緣體上矽基板可使用隔離，藉由插入氧氣(SIMOX)、晶圓鍵、及/或其他適宜方法來製造。基板102亦包括各隔離特徵，諸如淺溝槽隔離(shallow trench isolation；STI)特徵116及藉由淺溝槽隔離特徵116界定之主動區。
在一些實施例中，主動區在具有諸如鰭片結構104之非平面結構之隔離特徵116上方延伸。鰭片結構104具有由淺溝槽隔離特徵隔開之一或多個凸起主動區(或鰭片主動區)。儘管所圖示之實施例包括鰭片結構104，但另一實施例包括在基板102上形成之其他凸起主動及被動元件。
工件100包括場效電晶體，諸如n型通道場效電晶體(n-channel field effect transistor；nFET)及p型通道場效電晶體(p-channel field effect transistor；pFET)。在某一個實例中，主動區在鰭片結構104中界定，工件100包括鰭狀場效電晶體，諸如示例性n型通道鰭狀場效電晶體及p型通道鰭狀場效電晶體。
在本實施例中，工件100包括設計為核心元件106之一(或更多的)第一場效電晶體及設計為輸入/輸出(input/output；I/O)元件108之一(或更多的)第二場效電 晶體。彼等元件藉由所揭示之方法以不同方式設計及形成，此方法將會進一步詳述。每個場效電晶體又包括一對相對源/汲極特徵(或源/汲極區)110，其可包括各摻雜半導體材料；及設置在源/汲極區110之間之通道區112。穿過通道區112之載流子(n型通道元件之電子及p型通道元件之電洞)的流動藉由施加至閘極堆疊114(諸如閘極堆疊114A及閘極堆疊114B)之電壓來控制，閘極堆疊114鄰接通道區112(且當主動區在鰭片結構104中界定時裹包通道區112)。閘極堆疊114顯示為半透明的以更好地圖示下層通道區112。
在一些實施例中，主動區在鰭片結構104中界定，通道區112上升至淺溝槽隔離特徵116上方。相比於可比的平面元件，凸起通道區112提供鄰近閘極堆疊114之更大表面積。這強化了在閘極堆疊114與通道區112之間之電磁場互動，可減小與更小元件關聯之閾值電壓、洩漏及短通道效應。因而在多個實施例中，鰭狀場效電晶體及其他非平面元件以小於平面元件之佔用面積提供更好的效能。
在各實施例中，本揭露之方法及結構提供具有不同結構之場效電晶體(諸如核心元件106及輸出入元件108)，其包括對應的閘極介電質層及閘極側壁介電質材料層，具有不同的厚度。在本實施例中，基板102之半導體材料包括矽及可進一步包括其他半導體材料，諸如包括矽化鍺(SiGe)以獲得應變效應或其他效能增強。主動區104具有朝 向X方向之細長形狀，而閘極堆疊114具有朝向Y方向之細長形狀。X方向及Y方向彼此垂直。
在一些實施例中，本揭露之結構及方法可提供無摻雜之通道區112及具有更高的載流子遷移率及進一步增強之元件效能，諸如增大元件速度。在一些其他實施例中，通道區112可或者摻雜有適當類型之摻雜劑。
形成具有場效電晶體元件(諸如核心元件106及輸出入元件108)之工件100之示例性方法現將參看第2圖至第17圖描述。第2圖為根據本揭露之各態樣之用於在工件100上製造場效電晶體元件之方法200的流程圖。下圖涉及工件100之透視圖，及/或穿過通道區112(例如，沿平面122、平面124或126截取)或穿過場效電晶體元件之源/汲極區110(例如，沿平面128或平面130截取)之截面區。
根據本揭露之各態樣一起描述方法200及工件100之結構。應理解，額外步驟可在方法200之前、在方法200期間及在方法200之後提供，及對於方法之其他實施例可替換或除去所描述之一些步驟。在以下描述中，主動區亦一起稱為鰭片結構104。然而，主動區並不限於鰭片結構中之鰭片主動區。
首先參看第2圖之步驟202及第3圖，所接收之工件100包括基板102，諸如矽基板。基板102可或者或另外包括元素半導體、化合物半導體或其組合。基板102亦可包括絕緣體上矽基板。
各種摻雜製程可經由適當方法，諸如離子注入而應用至基板102。在本實施例中，防穿通(anti-punch-through；APT)製程經應用至基板102以經由離子注入將適當摻雜劑引入基板之各別區中。防穿通製程可包括形成具有界定n型場效電晶體區之開口之硬遮罩；對n型場效電晶體區執行離子注入；及移除硬遮罩及用於p型場效電晶體之類似步驟。
所接收之工件100可具有在其上形成之一或多個層。在第4圖圖示之一個實施例中，基板102包括在諸如矽晶圓之塊矽上磊晶生長之半導體層402，諸如矽。在其他圖示實施例中，基板102包括在塊矽上形成之第一半導體層及在第一半導體層上形成之第二半導體層。第一半導體層包括第一半導體材料(諸如矽化鍺)及第二半導體層包括不同於第一半導體材料之第二半導體材料(諸如矽)。第一及第二半導體層藉由適用技術，諸如選擇性地磊晶生長(selective epitaxy growth；SEG)來磊晶生長。在一些實施例中，用於磊晶生長之適宜的沉積製程包括原子層沉積(atomic layer deposition；ALD)、化學氣相沉積(chemical vapor deposition；CVD)、高密度電漿化學氣相沉積(high-density plasma CVD；HDP-CVD)、物理氣相沉積(physical vapor deposition；PVD)及/或其他適宜沉積製程。此些技術之任一個可用於生長具有包括梯度組成之任一組成之半導體層402。
在一些實施例中，半導體層402可無摻雜形成，因此亦稱為無摻雜半導體層。例如，在沉積期間，前驅物並不包括含摻雜化學試劑。此例進一步而言，不再進一步實施離子注入以消除將摻雜劑引入半導體層402。在此實施例中，所形成之通道區為無摻雜的及具有較少缺陷。
為促進製造及防止損壞半導體層，一或多個硬遮罩層404可在基板102上形成，諸如在半導體層402上。硬遮罩層404包括諸如半導體氧化物、半導體氮化物、半導體氮氧化物及/或半導體碳化物之介電質，及在示例性實施例中，硬遮罩層404包括氧化矽膜及氮化矽膜。硬遮罩層404可藉由熱生長、原子層沉積製程、化學氣相沉積製程、高密度電漿-化學氣相沉積製程、物理氣相沉積製程及/或其他適宜沉積製程而形成。
用於在方法200之隨後操作中界定鰭片結構104之光阻層(或抗蝕劑)可在硬遮罩層404上形成。示例性抗蝕劑層包括光敏材料，光敏材料致使層當暴露在諸如紫外線(UV)光、深度紫外光(deep UV；DUV)光或極紫外光(extreme UV；EUV)光之光中時經歷性質變化。此性質變化可用於藉由所指之顯影製程選擇性移除抗蝕劑層之曝光或未曝光的部分。形成圖案化之抗蝕劑層之此程序亦稱為微影圖案化。
在一個實施例中，抗蝕劑層經圖案化以藉由微影製程留下在工件100上方設置之光阻劑材料之部分。在圖案化抗蝕劑之後，對工件100執行蝕刻處理以打開硬遮罩層 404，進而將圖案自抗蝕劑層轉移至硬遮罩層404。可在圖案化硬遮罩層404之後移除剩餘之抗蝕劑層。示例性微影製程包括旋塗塗覆抗蝕劑層、抗蝕劑層之軟烘烤、遮罩對準、曝光、曝光後烘烤、顯影抗蝕劑層、沖洗及乾燥(例如，硬烘烤)。或者，可藉由諸如無遮罩光微影、電子束寫入、及離子束寫入之其他方法來實施、補充或替代微影製程。用於圖案化硬遮罩層之蝕刻製程可包括濕式蝕刻、乾式蝕刻或其組合。蝕刻製程可包括多個蝕刻步驟。例如，硬遮罩層中之氧化矽膜可藉由稀釋之氫氟酸溶液而蝕刻，及硬遮罩層中之氮化矽膜可由磷酸溶液而蝕刻。
參考第2圖之步驟206及第5圖至第6圖，在基板102中形成淺溝槽隔離特徵116。基板102(包括在本實例中之半導體層402)經蝕刻以經由圖案化硬遮罩層404之開口界定鰭片結構104。對工件100執行一或多個蝕刻製程以蝕刻不由圖案化硬遮罩層404覆蓋之基板102之部分。圖案化硬遮罩層404在蝕刻製程期間用作蝕刻遮罩以圖案化基板。
蝕刻製程可包括諸如乾式蝕刻、濕式蝕刻及/或其他蝕刻方法(例如，反應性離子蝕刻(reactive ion etching；RIE))之任一適宜蝕刻技術。在一些實施例中，蝕刻製程包括具有不同蝕刻化學物質之多個蝕刻步驟，每個目標為工件100之特定材料。在一些實例中，基板之半導體材料可由使用基於氟腐蝕劑之乾式蝕刻製程來蝕刻。
設計蝕刻製程來產生在半導體層402之剩餘部分上方延伸之具有任一適宜高度及寬度之鰭片結構104。除界定鰭片結構104之外，蝕刻製程亦在鰭片結構104之主動區之間界定一或多個隔離溝槽502。
特定言之，控制應用至基板之蝕刻製程使得部分地蝕刻基板102，如第5圖中圖示。這可藉由控制蝕刻時間或藉由控制其他蝕刻參數來實現。在蝕刻製程之後，鰭片結構自基板102形成及延伸。
參看第6圖，一或多個隔離特徵116在基板102上形成。在本實施例中，隔離特徵116在隔離溝槽502中形成，及因此亦稱為淺溝槽隔離特徵。在溝槽502中填充一或多個介電質材料以形成隔離特徵116。適宜的填充介電質材料包括半導體氧化物、半導體氮化物、半導體氮氧化物、氟矽酸鹽玻璃(FSG)、低介電質常數介電質材料、及/或其組合。在各示例性實施例中，介電質材料使用高密度電漿-化學氣相沉積製程、低氣壓化學氣相沉積(sub-atmospheric CVD；SACVD)製程、大深寬比製程(high-aspect ratio process；HARP)、可流動化學氣相沉積(flowable CVD；FCVD)製程及/或旋塗製程來沉積。
介電質材料之沉積之後可為化學機械研磨/平坦化(CMP)製程。化學機械研磨製程可使用硬遮罩層404作為研磨停止層以防研磨至半導體層402。在所圖示實施例中，化學機械研磨製程完全地移除硬遮罩層404，但在另一 實施例中，硬遮罩層404之一些部分保留在化學機械研磨製程之後。
參看第2圖之步驟208及第7圖，隔離特徵116被凹陷，進而在鰭片主動區之間形成鰭片結構104及溝槽702。鰭片主動區藉由隔離特徵116彼此電隔離。任何適宜蝕刻技術可用於凹進填充介電質材料，其包括乾式蝕刻、濕式蝕刻、反應式離子蝕刻及/或其他蝕刻方法，及在示例性實施例中，各向異性乾式蝕刻用於選擇性地移除隔離特徵116之填充介電質材料而不蝕刻鰭片結構104。
參看第2圖之步驟210及第8圖，介電質材料層802在輸出入元件區內之鰭片結構104上形成。介電質材料層802充當輸出入鰭狀場效電晶體之閘極介電質層，或充當輸出入鰭狀場效電晶體之閘極介電質層之部分，由於輸出入元件經歷更苛刻的功率波動，所以輸出入鰭狀場效電晶體具有更厚閘極介電質層以獲得強健效能。在一些實施例中，介電質材料層802包括藉由適宜方法，諸如原子層沉積製程、化學氣相沉積、加熱氧化、臭氧氧化等來沉積氧化矽。介電質材料層802之形成可進一步包括後續退火製程以改進材料品質，諸如增大材料密度及降低缺陷。在本實施例中，介電質材料層在核心元件區及輸出入元件區兩者之鰭片結構上沉積，及隨後在移除虛設閘極之後自核心元件區移除。
參看第2圖之步驟212及第9圖，一或多個虛設閘極902在鰭片結構104上形成。虛設閘極902在通道區112上方形成。在一些實例中，虛設閘極902的形成包括沉積含 有多晶矽或其他適宜材料之虛設閘極層及藉由微影製程及蝕刻來圖案化此層。閘極硬遮罩層904可在虛設閘極材料層上形成並在虛設閘極形成期間用作蝕刻遮罩。閘極硬遮罩層904可包括任一適宜材料，諸如氧化矽、氮化矽、碳化矽、氮氧化矽、其他適宜材料及/或其組合。在一個實施例中，閘極硬遮罩904包括多個膜，諸如氧化矽及氮化矽。在一些實施例中，用以形成虛設閘極之圖案化製程包括藉由微影製程來形成圖案化之抗蝕劑層；使用圖案化之抗蝕劑層作為蝕刻遮罩來蝕刻硬遮罩層；及蝕刻閘極材料層以使用圖案化之硬遮罩層作為蝕刻遮罩來形成虛設閘極。
參看第2圖之步驟214及第10圖，一或多個閘極側壁特徵1002在虛設閘極902之側壁上形成。閘極側壁特徵1002可用於偏移後續形成之源/汲極特徵及可用於設計或修改源/汲極結構輪廓。閘極側壁特徵1002可包括任一適宜介電質材料，諸如半導體氧化物、半導體氮化物、半導體碳化物、半導體氮氧化物、其他適宜的介電質材料及/或其組合。閘極側壁特徵1002具有直接接觸虛設閘極902之側壁之內表面，其中內表面具有不同於介電質材料層802之組成，介電質材料層802直接地接觸虛設閘極902之底表面。如此設計以在後續階段中提供選擇性沉積。例如，介電質材料層802為氧化矽，而閘極側壁特徵1002之內表面為氮化矽。在一些實施例中，閘極側壁特徵1002可包括多個層，諸如虛設閘極902之側壁上之第一閘極間隔層(或密封層1002A)，及密封層1002A上之第二閘極間隔層1002B， 如第11圖圖示。就實施例進一步而言，密封層1002A為氮化矽及第二閘極間隔層1002B為氧化矽或氮化矽。包括密封層(或第一閘極間隔層)及第二閘極間隔層之每個閘極側壁特徵亦一起稱為閘極間隔層。閘極側壁特徵1002之形成包括沉積及各向異性蝕刻，諸如乾式蝕刻。在一個實例中，密封層1002A藉由原子層沉積製程形成及閘極間隔層1002B藉由沉積及各向異性蝕刻而形成。
在一些實施例中，凸起源/汲極特徵110在源/汲極區內形成。凸起源/汲極特徵可藉由用於具有增強載流子遷移率及元件效能之應變效應之選擇性磊晶生長而形成。虛設閘極902及閘極間隔層1002將源/汲極特徵110限制於源/汲極區。在許多實施例中，源/汲極特徵110由一或多個磊晶或磊晶(epi)製程而形成，藉此矽特徵、矽化鍺特徵、碳化矽特徵及/或其他適宜特徵在鰭片結構104上以晶態狀態生長。或者，應用蝕刻製程以在磊晶生長之前凹進源/汲極區。適宜磊晶製程包括化學氣相沉積方法(例如，氣態磊晶(vapor-phase epitaxy；VPE)及/或超高真空化學氣相沉積(ultra-high vacuum CVD；UHV-CVD)、分子束磊晶及/或其他的適宜製程。磊晶製程可使用氣態及/或液體前驅物，其與鰭片結構104之組成互相作用。
源/汲極特徵110在磊晶製程期間藉由引入摻雜物質而經原位摻雜，此摻雜物質包括：p型摻雜劑，諸如硼或二氟化硼(BF2)；n型摻雜劑，諸如磷或砷；及/或包括其組合之其他適宜摻雜劑。若源/汲極特徵110不經原位摻 雜，則執行注入製程(即，接合注入製程)以將對應摻雜劑引入源/汲極特徵110中。在示例性實施例中，n型場效電晶體中之源/汲極特徵110包括碳化矽微粒(SiCP)或矽微粒(SiP)，而在p型場效電晶體中之彼等包括硼摻雜鍺錫(GeSnB)(錫可用於調諧晶格常數)及/或硼摻雜矽鍺錫(SiGeSnB)。在一些其他實施例中，凸起源/汲極特徵110包括一個以上半導體材料層。例如，矽化鍺層在源/汲極區內之基板上磊晶生長及矽層在矽化鍺層上磊晶生長。此後可執行一或多個退火製程以起動源/汲極特徵110。適宜的退火製程包括快速熱退火(rapid thermal annealing；RTA)、雷射退火製程、其他適宜退火技術或其組合。
參看第2圖之步驟216及第11圖，層間介電質層(inter-level dielectric material；ILD)1102在基板上形成以覆蓋源/汲極區中之源/汲極特徵110。層間介電質層1102圍繞虛設閘極902及閘極側壁特徵(或閘極間隔層)1002，允許移除虛設閘極902及替換閘極114在所得之空腔(亦稱為閘極溝槽)1104中形成。因此，在此些實施例中，虛設閘極902在沉積層間介電質層1102之後移除，如第11圖圖示。層間介電質層1102亦可為電互連工件100之各元件之電互連結構之部分。在此些實施例中，層間介電質層1102充當支撐及隔離導電蹤跡之絕緣體。層間介電質層1102可包括任一適宜介電質材料，諸如半導體氧化物、半導體氮化物、半導體氮氧化物、其他適宜的介電質材料或其組合。在一些實施例中，層間介電質層1102之形成包括沉 積及化學機械研磨以提供平面化之頂表面。在化學機械研磨製程、額外蝕刻操作、或其組合期間可移除硬遮罩904。
參看第2圖之步驟218及第11圖，可移除在虛設閘極902，產生閘極溝槽1104。在一些實施例中，虛設閘極藉由蝕刻製程，諸如濕式蝕刻來移除以選擇性地移除虛設閘極。若更多材料存在，則蝕刻製程可包括多個蝕刻步驟以移除虛設閘極。
參看第2圖之步驟220及第12A圖、第12B圖、第12C圖及第12D圖，介電質材料層選擇性地在閘極溝槽之側壁上形成而閘極溝槽之底表面沒有介電質材料層。第12A圖及第12B圖分別為工件100之核心元件106及輸出入元件108的透視圖；及第12C圖及第12D圖分別為沿鰭片主動區中之切割線1202及切割線1204截取之穿過通道區之核心元件106及輸出入元件108的截面圖。
特別地，核心元件區及輸出入元件區內之介電質材料層具有不同的厚度。因此，彼等被單獨標記。在步驟220中，執行選擇性沉積以便介電質材料層1212在核心元件106之閘極溝槽之側壁上選擇性沉積及介電質材料層1214在輸出入元件108之閘極溝槽之側壁上選擇性沉積使得每個介電質材料層不存在於對應閘極溝槽之底表面上。核心元件106之介電質材料層1212具有第一厚度T1及輸出入元件108之介電質材料層1214具有大於第一厚度之第二厚度T2。在一些實施例中，比率T2/T1大於2。在一些實施例中，第一厚度T1在2埃與5埃之間變化而第二厚度T2在1奈米與 2奈米之間變化。第一及第二介電質材料層可單獨地形成或以集體程序形成。例如，第一介電質材料層在核心及輸出入區兩者內形成及額外介電質材料僅在輸出入區內選擇性沉積而主動區由沉積覆蓋。介電質材料層1212或介電質材料層1214改變閘極溝槽之尺寸並界定藉由對應介電質材料層偏移之對應最終閘極堆疊之尺寸。
步驟220中之選擇性沉積製程在下文參看第13圖之流程圖進一步描述。步驟220包括具有對工件100之毒化製程252(或處理)之操作。毒化製程改變各材料層以具有用於選擇性沉積之不同的表面組合物。例如，工件100包括鰭片結構(包括閘極溝槽之底表面)上之氧化矽之第一表面及在閘極溝槽之側壁上之氮化矽之第二表面。每個由毒化製程改變為具有不同的表面組成。第二表面可或者或另外包括矽之表面。
在本實施例中，毒化製程252包括第一化學處理254及第二化學處理256。根據一些實施例，第一化學處理254包括應用第一化學試劑以轉換第一材料層(氧化矽)以具有羥基封端面及轉換第二材料層(氮化矽或矽)以具有氫/氟封端面。在一個實例中，第一化學試劑包括稀釋之氫氟酸(diluted hydrofluoric acid；DHF)，諸如100：1氫氟酸溶液。第一處理可具有自5秒至15秒之處理歷時。第二化學處理256包括應用第二化學試劑以將羥基封端面轉換成含碳親水面中。例如，第二化學試劑包括十八烷基三氯矽烷(ODTS)甲苯溶液。在第二化學處理中，工件之表面浸泡在 十八烷基三氯矽烷甲苯溶液中歷時適宜的時間。在一個實例中，工件之表面浸泡在10毫米十八烷基三氯矽烷甲苯溶液中歷時自20小時至30小時之持續時間。
在一些實施例中，毒化製程252進一步包括在應用第二化學試劑之後之清洗製程258。根據一些實例，清洗製程包括在甲苯、丙酮及氯仿溶液中順序地沖洗工件。毒化製程252可進一步包括在沖洗之後在氮氣環境中之乾燥製程260。
在毒化製程之後，步驟220進行至沉積步驟262。由於毒化表面具有不同的表面特性，介電質材料層(1212或1214)僅沉積在第二材料層上，或在本實例中之氫/氟封端面上。沉積可使用適宜的沉積技術。在本實施例中，沉積使用原子層沉積製程沉積。原子層沉積製程包括具有兩個前驅物順序地層接層地沉積之循環的程序。在一些實例中，介電質材料為氮化矽，及氮化矽之沉積包括具有第一前驅物之原子層沉積製程，此第一前驅物具有六氯二矽烷(Si2Cl6)、二氯甲矽烷(SiH2Cl2)、乙矽烷(Si2H6)或其組合。第二前驅物可包括雙(叔-丁基胺基)矽烷(C8H22N2Si)或其他適宜化學試劑。
在沉積介電質材料之後，可隨後在步驟264執行蝕刻製程以自第一材料層(氧化矽)選擇性移除含碳親水面。
參看第2圖之步驟222及第14A圖、第14B圖、第14C圖及第14D圖，介電質材料層802自核心元件區移 除。第14A圖及第14B圖分別為工件100之核心元件106及輸出入元件108的透視圖；及第14C圖第14D圖分別為沿鰭片主動區中之切割線1402及切割線1404截取之穿過通道區之核心元件106及輸出入元件108的截面圖。在步驟222中，介電質材料層802自核心元件區移除。在一些實施例中，移除製程包括微影製程及蝕刻。實施例進一步而言，移除製程包括藉由微影製程形成圖案化之抗蝕劑層1406，其中圖案化之抗蝕劑層1406覆蓋輸出入元件區及具有經配置以便核心元件區在其間曝光之開口。蝕刻製程可包括濕式蝕刻，諸如氫氟酸以在核心元件區中之閘極溝槽內選擇性移除氧化矽。
參看第2圖之步驟224及第15A圖、第15B圖、第15C圖及第15D圖，閘極堆疊114在閘極溝槽中形成。第15A圖及第15B圖分別為工件100之核心元件106及輸出入元件108的透視圖；及第15C圖第15D圖分別為沿鰭片主動區中之切割線1502及切割線1504截取之穿過源/汲極區之核心元件106及輸出入元件108的截面圖。在步驟224中，閘極堆疊114A在核心元件區之閘極溝槽中形成，及閘極堆疊114B在輸出入元件區之閘極溝槽中形成。
閘極堆疊114(諸如114A或114B)在捲繞鰭片結構104之通道區112之工件100上形成。在一些實施例中，閘極堆疊114為包括高介電質常數介電質材料之閘機介電質層及金屬或金屬合金之閘電極。在一些實例中，閘極介電質層及閘電極每個可包括一定數量個子層。高介電質常數 介電質層可包括金屬氧化物、金屬氮化物，諸如氧化鋼(La2O3)、一氧化鋁(AlO)、氧化鋯(ZrO2)、二氧化鈦(TiO2)、五氧化二鉭(Ta2O5)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3(STO))、鈦酸鋇(BaTiO3(BTO))、鋯酸鋇(BaZrO3)、氧化鉿鋯(HfZrO)、氧化鉿鑭(HfLaO)、(HfSiO)、氧化鑭矽(LaSiO)、氧化鋁矽(AlSiO)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、鋇鍶((Ba,Sr)TiO3(BST))、氧化鋁(Al2O3)、氮化矽(Si3N4)、氮氧化物(SiON)或其他適宜介電質材料。閘電極可包括鈦(Ti)、銀(Ag)、鋁(Al)、氮化鋁鈦(TiAlN)、碳化鉭(TaC)、碳氮化鉭(TaCN)、矽氮化鉭(TaSiN)、錳(Mn)、鋯(Zr)、一氮化鈦(TiN)、一氮化鉭(TaN)、釕(Ru)、鉬(Mo)、氮化鎢(WN)、銅(Cu)、鎢(W)或任一適宜材料。在一些實施例中，不同的金屬材料用於具有各別功函數之n型場效電晶體及p型場效電晶體元件。閘極堆疊114藉由程序，諸如包括沉積及化學機械研磨之程序在閘極溝槽中形成。不過應理解，閘極堆疊114可為任一適宜閘極結構。
工件100之結構，尤其閘極結構，參看第16圖進一步描述。第16圖為根據一些實施例之沿鰭片活動區中之切割線122截取之核心元件(核心場效電晶體)106及輸出入元件(輸出入場效電晶體)108的截面圖。鰭片結構104為基板102之連續部分並擠出在淺溝槽隔離特徵116上方。
核心元件106包括閘極堆疊114A及在閘極堆疊114A之兩個側面上設置之源/汲極特徵110。閘極堆疊 114A包括閘極介電質層1602及藉由閘極介電質層1602圍繞之閘電極1604。閘極介電質層1602為配置在閘極溝槽內之U型。在圖示實例中，鰭片主動區朝向X方向而閘極堆疊114A朝向Y方向。閘極堆疊114A沿X方向跨尺寸Lg1，尺寸Lg1通常稱為閘極長度，因為其定義通道長度。閘極介電質層具有厚度Tg1。核心元件106進一步包括閘極側壁特徵1002，諸如密封層1002A、閘極間隔層1002B或兩者。在本實施例中，密封層1002A為L型。這包括自閘極堆疊114A之頂表面至鰭片結構104垂直延伸之第一部分，及沿X方向在鰭片結構上橫向延伸之第二部分。閘極間隔層1002B在密封層1002A之側壁上及密封層之第二部分之頂部上形成。
在一個此種實施例中，閘極介電質層1602包括藉由適宜方法，諸如原子層沉積製程、化學氣相沉積、臭氧氧化等來沉積之界面層。界面層可包括氧化矽、氮化矽、氮氧化矽及/或其他適宜材料。在一些實施例中，閘極介電質層包括藉由適宜技術，諸如原子層沉積製程、化學氣相沉積、金屬有機化學氣相沉積(metal-organic CVD；MOCVD)、物理氣相沉積、熱氧化、其組合及/或其他適宜技術，在界面層(若界面層存在)上沉積高介電質常數介電質層。
隨後在閘極溝槽中填充閘電極材料。閘電極1604由原子層沉積製程、物理氣相沉積、化學氣相沉積、電鍍、其他適宜製程或其組合而形成。閘電極可包括單層或多層，諸如金屬層、襯墊層、潤濕層及/或黏附層。在填充 閘電極材料之後，可執行化學機械研磨製程以產生閘極堆疊114A(亦包括閘極堆疊114B)之大體上平面的頂表面。在形成閘極堆疊114之後，可提供工件100用於進一步製造，諸如互連結構之接觸形成及進一步製造。
另外，核心元件106包括在閘極堆疊114A與閘極側壁特徵1002(密封層1002A及閘極間隔層1002B)之間插入之介電質材料層1212。介電質材料層1212藉由選擇性沉積形成；自閘極堆疊114A之頂表面垂直延伸並具有均勻厚度T1。這裡，均勻厚度(厚度T1與類似於後文描述之均勻厚度T2)意思是，對應層之厚度具有很小之變化，諸如小於10%。
輸出入元件108包括閘極堆疊114B及在閘極堆疊114B之兩個側面上設置之源/汲極特徵110。閘極堆疊114B包括閘極介電質層1602及藉由閘極介電質層1602圍繞之閘電極1604。閘極介電質層1602為配置在閘極溝槽內之U型。閘極堆疊114B朝向Y方向及沿X方向跨尺寸Lg2，其稱為閘極長度。在本實施例中，尺寸Lg2大於尺寸Lg1。閘極介電質層1602具有厚度Tg1。然而，輸出入元件108之總閘極介電質層包括介電質材料層802及閘極介電質層1602兩者。因此，輸出入元件108之閘電極之總厚度為大於厚度Tg1之厚度Tg2。換言之，輸出入元件108之閘極介電質之當量氧化物厚度大於核心元件106之閘極介電質之當量氧化物厚度，因而使輸出入元件耐受功率波動更強健。輸出入元件108進一步包括閘極側壁特徵1002，諸如密封層 1002A、閘極間隔層1002B或兩者，類似於核心元件106之彼等。在本實施例中，密封層1002A為L型。這包括自閘極堆疊114B之頂表面至鰭片結構104垂直延伸之第一部分，及沿X方向在鰭片結構上橫向延伸之第二部分。閘極間隔層1002B在密封層1002A之側壁上及密封層之第二部分之頂部上形成。
另外，輸出入元件108包括在閘極堆疊114B與輸出入元件108內之閘極側壁特徵1002(諸如密封層1002A及閘極間隔層1002B)之間插入之介電質材料層1214。介電質材料層1214藉由選擇性沉積而形成；自閘極堆疊114B之頂表面垂直延伸並在介電質材料層802上方結束(有時可接觸氧化矽層)；及具有大於厚度T1之均勻厚度T2。在一些實例中，比率T2/T1大於2。在一些實例中，厚度T1自2埃至5埃之範圍內變化而厚度T2自1奈米至2奈米之範圍內變化。
特別地，虛設閘極具有比最終閘極(閘極堆疊114A或閘極堆疊114B)之對應尺寸(尺寸Lg1或尺寸Lg2)更大之尺寸。即使最終閘極具有更小尺寸，藉由揭示之方法製成之對應虛設閘極具有更大之尺寸，因而更強壯及強健以支撐其形狀及位置而無塌陷。如上所述，當半導體製造發展到具有更少特徵尺寸及高圖案密度之進階技術節點時，閘極可黏附在一起。所揭示之方法及結構提供半導體結構以消除上述問題。特別地，核心元件106及輸出入元件108經設計 及製造以具有用於各別效能調節及增強之不同特性(閘極介電質厚度Tg1及Tg2與側壁介電質厚度T1及T2)。
介電質材料層1212/1214及閘極側壁特徵1002經選擇具有某些組成及表面特性以實現選擇性沉積，進一步促進閘極強健以解決黏附問題，諸如在濕式蝕刻或濕清洗期間之黏附問題。在一些實施例中，介電質材料層1212或1214為氮化矽層。閘極側壁特徵1002之內表面接觸介電質材料層(1212或1214)且為氮化矽面。例如，當閘極側壁特徵1002僅包括一個材料層時，其為氮化矽層。在其他實例中，閘極側壁特徵1002包括密封層1002A及閘極間隔層1002B，密封層1002A為氮化矽層而閘極間隔層1002B為氧化矽層或氮化矽層。
參照作為截面圖之第17圖進一步描述閘電極1604。根據一些實施例，閘電極1604可表示核心元件106之閘電極或具有詳細閘極材料層之輸出入元件108之閘電極。
如第17圖圖示，閘電極1604包括蓋層1702、阻擋層1704、功函數金屬層1706、另一阻擋層1708及填充金屬層1710。實施例進一步而言，蓋層1702包括氮化鈦、氮化鉭或其他適宜材料，由諸如原子層沉積之適當沉積方法而形成。阻擋層1704包括氮化鈦、氮化鉭或其他適宜材料，由諸如原子層沉積之適當沉積方法而形成。在一些實例中，阻擋層可能不存在或他們中之僅一個存在於閘電極中。
功函數金屬層1706包括具有適當功函數之金屬或金屬合金之導電層使得增強對應場效電晶體以獲得其元件效能。對於p型場效電晶體及n型場效電晶體，功函數(work function；WF)金屬層1706不一樣，分別稱為n型功函數金屬及p型功函數金屬。功函數金屬之選擇取決於在主動區上形成之場效電晶體。例如，半導體結構100包括n型場效電晶體之第一主動區及p型場效電晶體之另一主動區，及因此，n型功函數金屬及p型功函數金屬分別在對應閘極堆疊中形成。特定而言，n型功函數金屬為具有第一功函數之金屬使得降低關聯n型場效電晶體之閾值電壓。n型功函數金屬接近矽導電帶能量(Ec)或更低功函數，從而表現出較容易之電子逃逸。例如，n型功函數金屬具有約4.2eV或更少之功函數。p型功函數金屬為具有第二功函數之金屬使得降低關聯p型場效電晶體之閾值電壓。p型功函數金屬接近矽價帶能量(Ev)或更高功函數，從而表現出對原子核之強電子鍵結能量。例如，p型功函數金屬具有約5.2eV或更高之功函數。
在一些實施例中，n型功函數金屬包括鉭(Ta)。在其他實施例中，n型功函數金屬包括鈦鋁(TiAl)、氮化鋁鈦(TiAlN)或其組合。在其他實施例中，n型金屬包括鉭、鈦鋁、氮化鋁鈦、氮化鎢(WN)或其組合。n型功函數金屬可包括各種基於金屬膜，此些金屬膜作為堆疊用於最佳化元件效能及處理相容性。在一些實施例中，p型功函數金屬包括氮化鈦(TiN)或氮化鉭(TaN)。在其他實施例中，p型金屬 包括氮化鈦、氮化鉭、氮化鎢(WN)、鈦鋁(TiAl)或其組合。p型功函數金屬可包括各種基於金屬膜，此些金屬膜作為堆疊用於最優化元件效能及處理相容性。功函數金屬由諸如物理氣相沉積之適用技術而沉積。
阻擋層1708包括氮化鈦、氮化鉭或其他適宜材料，由諸如原子層沉積之適當沉積方法而形成。在各實施例中，填充金屬層1710包括鋁、鎢或其他適宜金屬。填充金屬層1710由諸如物理氣相沉積或電鍍之適用技術而沉積。
本揭露提供製造具有各鰭狀場效電晶體之半導體結構及其中鰭狀場效電晶體決於核心元件或輸出入元件具有不同配置及尺寸之半導體結構的方法。各種優勢可存在於不同實施例中。此方法包括選擇性沉積使得虛設閘極具有更大之尺寸以進行濕式蝕刻/清洗而無破裂。核心元件及輸出入元件之不同結構增強各別元件效能。
因而，本揭露根據一些實施例提供半導體結構。半導體結構包括：基板上之鰭片結構；形成在此鰭片結構上之第一閘極堆疊及第二閘極堆疊；設置在此第一閘極堆疊及第二閘極堆疊上之介電質材料層，其中此介電質層包括設置在具有第一厚度之第一閘極堆疊之側壁上之第一部分，以及設置在具有大於此第一厚度之第二厚度之第二閘極堆疊之側壁上之第二部分；設置在此介電質材料層之第一部分上之第一閘極間隔層；以及設置在此介電質材料層之第二部分上之第二閘極間隔層。
本揭露亦根據一些其他實施例提供半導體結構。半導體結構包括：形成在基板上之第一閘極堆疊及第二閘極堆疊；設置在此第一閘極堆疊及第二閘極堆疊上之介電質材料層，其中此介電質層包括設置在具有第一厚度之第一閘極堆疊之側壁上之第一部分，及設置在具有大於此第一厚度之第二厚度之第二閘極堆疊之側壁上之第二部分；設置在此介電質材料層之第一部分上之第一閘極間隔層；以及設置在此介電質材料層之第二部分上之第二閘極間隔層。
本揭露亦提供根據一些其他實施例之半導體結構。半導體結構包括設置在第一鰭片結構上之第一場效電晶體(FET)，其中此第一場效電晶體進一步包括第一閘極堆疊、設置在第一閘極堆疊之兩個側面上之第一源/汲極特徵、設置在此第一閘極堆疊之側壁上之第一閘極間隔層及插入在第一閘極間隔層與第一閘極堆疊之側壁之間之第一介電質材料層；及設置在第二鰭片結構上之第二場效電晶體，其中此第二場效電晶體進一步包括第二閘極堆疊，設置在第二閘極堆疊之兩個側面上之第二源/汲極特徵，設置在第二閘極堆疊之側壁上之第二閘極間隔層，及插入在第二閘極間隔層與第二閘極堆疊之側壁之間之第二介電質材料層。第一介電質材料層具有第一厚度T1，及第二介電質材料層具有大於第一厚度之第二厚度T2。
本揭露提供一種半導體結構之製造方法。此方法包括在半導體基板上形成虛設閘極；在半導體基板上形成層間介電質層(ILD)；移除虛設閘極，進而在層間介電質層 中產生閘極溝槽；在閘極溝槽中形成介電質材料層使得介電質材料層被設置在閘極溝槽之側壁上且免於位在閘極溝槽之底表面上；及在閘極溝槽中形成金屬閘極，進而此金屬閘極藉由介電質材料層之厚度橫跨的一尺寸小於虛設閘極之對應尺寸。
在各實施例中，此方法可進一步包括在施加第二化學試劑之後執行清洗製程及在氮氣環境中執行乾燥製程，其中此清洗製程包括順序地在甲苯、丙酮及氯仿中沖洗。此方法可進一步包括施加蝕刻製程以在沉積製程之後自第一材料層選擇性移除含碳親水面。在此方法中，根據一些實例，第一材料層為氧化矽層及第二材料層為矽層及氮化矽層之其一。
上文概述若干實施例之特徵，使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解，可輕易使用本揭露作為設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施例的相同目的及/或實現相同優勢。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭露之精神及範疇，且可在不脫離本揭露之精神及範疇的情況下產生本文的各種變化、替代及更改。

Claims (10)

  1. 一種半導體結構，其包含：一第一鰭片與一第二鰭片，位在一基板上；一第一閘極堆疊，部分包覆該第一鰭片，包含一第一閘極介電質膜以及一第一閘電極；一第二閘極堆疊，部分包覆該第二鰭片，包含一第二閘極介電質膜以及一第二閘電極；一第一閘極側壁特徵，設置在該第一閘極堆疊的側壁上，該第一閘極側壁特徵包含一第一閘極間隔層以及一第二閘極間隔層，其中該第一閘極間隔層的材料不同於該第二閘極間隔層的材料；以及一第二閘極側壁特徵，設置在該第二閘極堆疊的側壁上，該第二閘極側壁特徵包含一第三閘極間隔層以及一第四閘極間隔層，其中該第三閘極間隔層的材料不同於該第四閘極間隔層的材料；一第一介電質材料層，設置在該第二閘極間隔層與該第一閘極堆疊的側壁之間，其中該第一介電質材料層直接接觸該第一閘極堆疊的該第一閘極介電質膜與該第二閘極間隔層，該第一介電質材料層具有一第一厚度；以及一第二介電質材料層，設置在該第四閘極間隔層與該第二閘極堆疊的側壁之間，其中該第二介電質材料層直接接觸該第二閘極堆疊的該第二閘極介電質膜與該第四閘極間隔層，該第二介電質材料層具有一第二厚度，且該第二厚度大於該第一厚度。
  2. 如請求項1所述之半導體結構，其中該第二厚度比該第一厚度之一比率大於2。
  3. 如請求項1所述之半導體結構，其中該第二閘極間隔層與該第四閘極間隔層為L形。
  4. 一種半導體結構，其包含：一第一場效電晶體，包含一第一鰭片結構、設置在該第一鰭片結構的一第一通道區上的一第一閘極堆疊、設置在該第一鰭片結構上且位於該第一閘極堆疊之兩側上之兩第一源/汲極特徵、設置在該第一閘極堆疊之一側壁上之一第一閘極間隔層、以及設置在該第一閘極間隔層之一部分的該側壁上的一第一介電質材料層，其中該第一介電質材料層直接接觸該第一閘極間隔層與該第一閘極堆疊之該部分的該側壁；以及一第二場效電晶體，包含一第二鰭片結構、設置在該第二鰭片結構的一第二通道區上的一第二閘極堆疊、設置在該第二鰭片結構上且位於該第二閘極堆疊之兩側上之兩第二源/汲極特徵、設置在該第二閘極堆疊之一側壁上之一第二閘極間隔層、以及設置在該第二閘極間隔層之一部分的該側壁上的一第二介電質材料層，其中該第二介電質材料層直接接觸該第二閘極間隔層與該第二閘極堆疊之該部分的該側壁，其中：該第一介電質材料層具有一第一厚度T1，以及該第二介電質材料層具有大於該第一厚度T1之一第二厚度T2。
  5. 如請求項4所述之半導體結構，其中該第一閘極堆疊包括設置在該第一鰭片結構上之一第一閘極介電質膜以及設置在該第一閘極介電質膜上之一第一閘電極；以及該第二閘極堆疊包括設置在該第二鰭片結構上之一第二閘極介電質膜以及設置在該第二閘極介電質膜上之一第二閘電極，其中該第一介電質材料層位在該第一閘極介電質膜之一頂表面上方，及該第二介電質材料層位在該第二閘極介電質膜之一頂表面上方。
  6. 一種半導體結構的製造方法，包含：在一半導體基板上形成一虛設閘極；在該半導體基板上形成一層間介電質層；移除該虛設閘極，進而在該層間介電質層中產生一閘極溝槽；在該閘極溝槽中形成一介電質材料層使得該介電質材料層被設置在該閘極溝槽之側壁上且免於位在該閘極溝槽之一底表面上；以及在該閘極溝槽中形成一金屬閘極，進而該金屬閘極藉由該介電質材料層之一厚度橫跨的一尺寸小於該虛設閘極之一對應尺寸。
  7. 如請求項6所述之方法，其中形成該虛設閘極之步驟包括形成一第一材料之一閘極介電質層、在該閘極介電質層上形成一虛設閘電極、以及在該虛設閘電極之一側壁上形成一第二材料層之一閘極側壁特徵，其中該第二材料層在組成上不同於該第一材料層；以及形成該介電質材料層在該閘極溝槽中之步驟包括執行一選擇性沉積，進而將該介電質材料層沉積至在該閘極溝槽之該側壁上之該第二材料層，而免於沉積在該閘極溝槽之該底表面上之該第一材料層。
  8. 如請求項7所述之方法，其中該介電質材料層為氮化矽；該第一材料層為氧化矽；以及該第二材料層為氮化矽。
  9. 如請求項7所述之方法，其中形成該介電質材料層包括：執行一毒化處理，該毒化處理進一步包括：施加一第一化學試劑以轉換該第一材料層以具有一羥基封端面及轉換該第二材料層以具有一氫/氟封端面，以及施加一第二化學試劑以轉換該羥基封端面至一含碳親水面；以及執行一沉積製程以在該氫/氟封端面上選擇性沉積該介電質材料層。
  10. 如請求項6所述之方法，其中形成該介電質材料層包括在具有一第一厚度之該閘極溝槽之該側壁上形成該介電質材料層及在具有大於該第一厚度之一第二厚度之另一閘極溝槽之側壁上形成該介電質材料層。
TW106118724A 2016-12-15 2017-06-06 半導體結構及其製造方法 TWI675486B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/379,632 US10651171B2 (en) 2016-12-15 2016-12-15 Integrated circuit with a gate structure and method making the same
US15/379,632 2016-12-15

Publications (2)

Publication Number Publication Date
TW201824564A TW201824564A (zh) 2018-07-01
TWI675486B true TWI675486B (zh) 2019-10-21

Family

ID=62251300

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106118724A TWI675486B (zh) 2016-12-15 2017-06-06 半導體結構及其製造方法

Country Status (5)

Country Link
US (3) US10651171B2 (zh)
KR (2) KR20180069680A (zh)
CN (1) CN108231876B (zh)
DE (1) DE102017117863B4 (zh)
TW (1) TWI675486B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10651171B2 (en) 2016-12-15 2020-05-12 Taiwan Semiconductor Manufacturing Co. Ltd. Integrated circuit with a gate structure and method making the same
CN108807532B (zh) * 2017-04-28 2021-07-06 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
CN109309056B (zh) * 2017-07-27 2020-12-22 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10483168B2 (en) * 2017-11-15 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Low-k gate spacer and formation thereof
US11289583B2 (en) * 2018-09-28 2022-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. High aspect ratio gate structure formation
US11205647B2 (en) 2019-06-28 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
TWI758071B (zh) * 2020-04-27 2022-03-11 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
DE102021103469A1 (de) * 2020-04-30 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierter schaltkreis und verfahren zu dessen herstellung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050051866A1 (en) * 2003-06-09 2005-03-10 Taiwan Semiconductor Manufacturing Co. Method for forming devices with multiple spacer widths
US20080122011A1 (en) * 2006-11-03 2008-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Variable width offset spacers for mixed signal and system on chip devices
US20080258227A1 (en) * 2007-04-18 2008-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Strained spacer design for protecting high-k gate dielectric
US20100072545A1 (en) * 2008-09-22 2010-03-25 Jeong-Do Ryu Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100269336B1 (ko) 1998-09-16 2000-10-16 윤종용 전도층이 포함된 게이트 스페이서를 갖는 반도체 소자 및 그 제조방법
US6737716B1 (en) * 1999-01-29 2004-05-18 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP2001077209A (ja) * 1999-07-08 2001-03-23 Mitsubishi Electric Corp 半導体装置の製造方法
JP3782297B2 (ja) * 2000-03-28 2006-06-07 株式会社東芝 固体撮像装置及びその製造方法
JP2003258129A (ja) * 2002-03-01 2003-09-12 Seiko Epson Corp 不揮発性記憶装置の製造方法
TWI249843B (en) * 2002-05-14 2006-02-21 Sony Corp Semiconductor device and its manufacturing method, and electronic apparatus
JP2003347428A (ja) 2002-05-24 2003-12-05 Huabang Electronic Co Ltd 堆積したスペーサー構造および方法
US6909145B2 (en) 2002-09-23 2005-06-21 International Business Machines Corporation Metal spacer gate for CMOS FET
US7011929B2 (en) * 2003-01-09 2006-03-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming multiple spacer widths
US7176522B2 (en) * 2003-11-25 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacturing thereof
US7829978B2 (en) * 2005-06-29 2010-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Closed loop CESL high performance CMOS device
US7544561B2 (en) * 2006-11-06 2009-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
JP5203669B2 (ja) 2007-10-22 2013-06-05 株式会社東芝 半導体装置およびその製造方法
KR20090078151A (ko) * 2008-01-14 2009-07-17 삼성전자주식회사 반도체 소자의 제조방법
US7910453B2 (en) 2008-07-14 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Storage nitride encapsulation for non-planar sonos NAND flash charge retention
US8329545B1 (en) * 2008-12-30 2012-12-11 Micron Technology, Inc. Method of fabricating a charge trap NAND flash memory
EP2462611B1 (en) * 2009-08-05 2019-09-25 Faculdade De Ciências E Tecnologia/ Universidade Nova De Lisboa Amorphous multicomponent dielectric based on the mixture of high band gap and high k materials, respective devices and manufacture
US20110147848A1 (en) 2009-12-23 2011-06-23 Kuhn Kelin J Multiple transistor fin heights
US8310013B2 (en) 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US8399931B2 (en) 2010-06-30 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Layout for multiple-fin SRAM cell
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8561003B2 (en) 2011-07-29 2013-10-15 Synopsys, Inc. N-channel and P-channel finFET cell architecture with inter-block insulator
CN102956457B (zh) 2011-08-22 2015-08-12 中国科学院微电子研究所 半导体器件结构及其制作方法、及半导体鳍制作方法
US8466027B2 (en) 2011-09-08 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation and associated devices
US8723272B2 (en) 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
KR101964262B1 (ko) * 2011-11-25 2019-04-02 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8377779B1 (en) 2012-01-03 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices and transistors
US8735993B2 (en) 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8716765B2 (en) 2012-03-23 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8981481B2 (en) * 2012-06-28 2015-03-17 Intel Corporation High voltage three-dimensional devices having dielectric liners
US8492228B1 (en) * 2012-07-12 2013-07-23 International Business Machines Corporation Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers
US8736056B2 (en) 2012-07-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Device for reducing contact resistance of a metal
KR20140034347A (ko) 2012-08-31 2014-03-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9029226B2 (en) 2013-03-13 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for doping lightly-doped-drain (LDD) regions of finFET devices
US9508719B2 (en) 2014-11-26 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same
US9577070B2 (en) 2014-11-26 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Gate spacers and methods of forming
CN105826381B (zh) * 2015-01-09 2018-11-16 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
KR102342847B1 (ko) 2015-04-17 2021-12-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
JP2016207853A (ja) * 2015-04-23 2016-12-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9583485B2 (en) 2015-05-15 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device structure with uneven gate structure and method for forming the same
CN106409830B (zh) * 2015-07-27 2020-05-05 联华电子股份有限公司 具有金属栅极的半导体元件及其制作方法
WO2017111774A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Transistor with inner-gate spacer
US20170200803A1 (en) * 2016-01-11 2017-07-13 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US10651171B2 (en) 2016-12-15 2020-05-12 Taiwan Semiconductor Manufacturing Co. Ltd. Integrated circuit with a gate structure and method making the same
US10115895B1 (en) * 2017-09-26 2018-10-30 Sandisk Technologies Llc Vertical field effect transisitors having a rectangular surround gate and method of making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050051866A1 (en) * 2003-06-09 2005-03-10 Taiwan Semiconductor Manufacturing Co. Method for forming devices with multiple spacer widths
US20080122011A1 (en) * 2006-11-03 2008-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Variable width offset spacers for mixed signal and system on chip devices
US20080258227A1 (en) * 2007-04-18 2008-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Strained spacer design for protecting high-k gate dielectric
US20100072545A1 (en) * 2008-09-22 2010-03-25 Jeong-Do Ryu Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor

Also Published As

Publication number Publication date
TW201824564A (zh) 2018-07-01
CN108231876B (zh) 2020-09-04
KR20180069680A (ko) 2018-06-25
CN108231876A (zh) 2018-06-29
US10651171B2 (en) 2020-05-12
US20210043626A1 (en) 2021-02-11
KR20190088450A (ko) 2019-07-26
US20180350803A1 (en) 2018-12-06
DE102017117863B4 (de) 2022-09-01
US10818658B2 (en) 2020-10-27
US20180175029A1 (en) 2018-06-21
KR102099742B1 (ko) 2020-04-13
DE102017117863A1 (de) 2018-06-21

Similar Documents

Publication Publication Date Title
US11961900B2 (en) Integrated circuit with a fin and gate structure and method making the same
US10622464B2 (en) Integrated circuit structure with substrate isolation and un-doped channel
CN108807380B (zh) 半导体结构和形成集成电路结构的方法
TWI675486B (zh) 半導體結構及其製造方法
US11289494B2 (en) Structure and method for SRAM FinFET device having an oxide feature
US9698058B2 (en) Structure and method for FinFET device
US10468528B2 (en) FinFET device with high-k metal gate stack
CN103928517A (zh) FinFET器件及其制造方法
US11791217B2 (en) Gate structure and method with dielectric gates and gate-cut features
US20200365734A1 (en) Structure and Method for FinFET Device with Asymmetric Contact