CN110556337B - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

Info

Publication number
CN110556337B
CN110556337B CN201810551963.9A CN201810551963A CN110556337B CN 110556337 B CN110556337 B CN 110556337B CN 201810551963 A CN201810551963 A CN 201810551963A CN 110556337 B CN110556337 B CN 110556337B
Authority
CN
China
Prior art keywords
layer
work function
area
forming
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810551963.9A
Other languages
English (en)
Other versions
CN110556337A (zh
Inventor
王楠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201810551963.9A priority Critical patent/CN110556337B/zh
Priority to US16/419,416 priority patent/US10971405B2/en
Publication of CN110556337A publication Critical patent/CN110556337A/zh
Application granted granted Critical
Publication of CN110556337B publication Critical patent/CN110556337B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Materials Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种半导体器件及其形成方法，方法包括：提供基底，所述基底包括第一区和第二区，所述第一区与第二区邻接且位于第二区两侧，所述第一区和第二区的基底上具有多个分立的鳍部；在第一区的鳍部内形成第一掺杂区；在第二区的鳍部内形成第二掺杂区，第一掺杂区的掺杂离子浓度比第二掺杂区低，第二掺杂区与第一掺杂区的掺杂离子类型相同；形成第一掺杂区和第二掺杂区后，在第一掺杂区和第二掺杂区上形成横跨鳍部的栅极结构。所述方法使得第一区的晶体管的阈值电压比第二区的晶体管阈值电压低，第二区晶体管的沟道开启电压较大，第二区的鳍部产生的热量较少，中间区域内不容易发生热量的集聚，自发热效应不显著，提高了半导体器件的性能。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高的元件密度，以及更高的集成度的方向发展。器件作为最基本的半导体器件，目前正被广泛应用，传统的平面器件对沟道电流的控制能力变弱，产生短沟道效应而导致漏电流，最终影响半导体器件的电学性能。
为了克服器件的短沟道效应，抑制漏电流，现有技术提出了鳍式场效应晶体管(Fin FET)，鳍式场效应晶体管是一种常见的多栅器件，鳍式场效应晶体管的结构包括：位于半导体衬底表面的鳍部和隔离层，所述隔离层覆盖部分所述鳍部的侧壁，且隔离层表面低于鳍部顶部；位于隔离层表面，以及鳍部的顶部和侧壁表面的栅极结构；位于所述栅极结构两侧的鳍部内的源区和漏区。
然而，现有技术形成的半导体器件的性能较差。
发明内容
本发明解决的技术问题是提供一种半导体器件及其形成方法，以提高半导体器件的性能。
为解决上述技术问题，本发明提供一种半导体器件的形成方法，包括：提供基底，所述基底包括第一区和第二区，所述第一区与第二区邻接且位于第二区两侧，所述第一区和第二区的基底上具有多个分立的鳍部；在第一区的鳍部内形成第一掺杂区；在第二区的鳍部内形成第二掺杂区，第一掺杂区的掺杂离子浓度比第二掺杂区低，第二掺杂区与第一掺杂区的掺杂离子类型相同；形成第一掺杂区和第二掺杂区后，在第一掺杂区和第二掺杂区上形成横跨鳍部的栅极结构。
可选的，所述第一掺杂区的形成工艺包括：离子注入工艺或者固态源掺杂工艺。
可选的，所述第二掺杂区的形成工艺包括：离子注入工艺或者固态源掺杂工艺。
可选的，当所述第一掺杂区和第二掺杂区的形成工艺均为离子注入工艺时，所述第一掺杂区和第二掺杂区的形成方法包括：在所述基底上形成掩膜层，所述掩膜层暴露出第一区和第二区的鳍部的位置和形状；以所述掩膜层为掩膜，对所述第一区和第二区的鳍部进行第一离子注入；第一离子注入后，对所述第一区和第二区的鳍部进行第二离子注入，所述第一离子注入的方向和第二离子注入的方向沿半导体衬底法线方向对称，所述第一离子注入和第二离子注入的方向平行于鳍部的延伸方向，形成所述第一掺杂区和第二掺杂区。
可选的，所述掩膜层距离第一区的边缘鳍部的距离为30nm～300nm。
可选的，所述掩膜层距离鳍部顶部的高度为鳍部高度的N倍，N为大于或等于1的整数，N为第二区一侧的第一区内的鳍部的个数。
可选的，当所述鳍部用于形成P型器件时，所述第一离子注入或者第二离子注入的参数包括：所述注入离子包括磷离子或砷离子，能量范围为10KeV～30KeV，剂量范围为1E13atom/cm2～5E14atom/cm2，倾斜角度为10～40度；所述倾斜角度为注入方向与基底所在平面的法线之间的夹角。
可选的，当所述鳍部用于形成N型器件时，所述第一离子注入或者第二离子注入的参数包括：所述注入离子包括硼离子或BF2-离子，能量范围为35KeV～30KeV，剂量范围为1E13atom/cm2～5E14atom/cm2，倾斜角度为10度～40度；所述倾斜角度为注入方向与基底所在平面的法线之间的夹角。
可选的，当所述第一掺杂区和第二掺杂区的形成工艺均为固态源掺杂工艺时，所述第一掺杂区和第二掺杂区的形成方法包括：在所述基底第一区的鳍部表面形成具有第一掺杂离子的第一掺杂层，所述第一掺杂层内的离子浓度为第一浓度；在所述基底第二区的鳍部表面形成具有第二掺杂离子的第二掺杂层，所述第一掺杂离子和第二掺杂离子的掺杂离子类型相同，所述第二掺杂层内的离子浓度为第二浓度，所述第二浓度大于第一浓度；形成第一掺杂层和第二掺杂层后，对所述第一掺杂层、第二掺杂层和进行退火处理，使得所述第一掺杂离子进入第一区的鳍部，使得所述第二掺杂离子进入第二区的鳍部。
可选的，当所述鳍部用于形成P型器件时，所述第一掺杂层的材料包括硅或硅锗；所述第一掺杂离子为P型离子，所述第一掺杂离子包括磷离子或砷离子，所述第二掺杂层的材料包括硅或硅锗；所述第二掺杂离子为P型离子，所述第二掺杂离子包括磷离子或砷离子。
可选的，当所述鳍部用于形成N型器件时，所述第一掺杂层的材料包括氧化硅或氮化硅；所述第一掺杂离子为N型离子，所述第一掺杂离子包括硼离子、BF2-离子或铟离子，所述第二掺杂层的材料包括氧化硅或氮化硅；所述第二掺杂离子为N型离子，所述第二掺杂离子包括硼离子、BF2-离子或铟离子。
可选的，所述基底还包括第三区，所述第三区位于第一区和第二区之间，所述第三区与第一区和第二区相邻；在所述第三区的鳍部内形成第三掺杂区，所述第三掺杂区的掺杂离子浓度高于第一掺杂区，所述第三掺杂区的掺杂离子浓度小于第二掺杂区，第三掺杂区的掺杂离子类型与第一掺杂区或第二掺杂区的掺杂离子类型相同。
相应的，本发明还提供一种采用上述任意一项方法形成的半导体器件
本发明还提供另一种半导体器件的形成方法，包括：提供基底，所述基底包括第一区和第二区，所述第一区与第二区邻接且位于第二区两侧，所述基底第一区和第二区上具有多个分立的鳍部；在所述基底上形成介质层，所述介质层内具有开口，所述开口暴露出部分鳍部表面；在所述开口底部表面形成栅介质层；在位于第一区的开口内形成位于栅介质层表面的第一调节功函数层；在形成第一调节功函数层之前或之后，在位于第二区的开口内形成位于栅介质层表面的第二调节功函数层，所述第二调节功函数层的功函数值和第一调节功函数层的功函数值不同，第一调节功函数层和第二调节功函数层的功函数类型相同；形成第一调节功函数层和第二调节功函数层后，在所述开口内形成栅电极层，所述栅电极层填充满所述开口。
可选的，当所述鳍部用于形成N型器件时，所述第一调节功函数层和第二调节功函数层的材料为N型功函数材料；当所述鳍部用于形成P型器件时，所述第一调节功函数层和第二调节功函数层的材料为P型功函数材料。
可选的，所述第一调节功函数层的厚度小于第二调节功函数层的厚度。
可选的，所述N型功函数材料包括：TiN或TaN。
可选的，所述P型功函数材料包括：TaC、Ti、Al或TiAl。
可选的，所述第二调节功函数层内的氮原子百分比浓度高于第一调节功函数层内的氮原子百分比浓度。
相应的，本发明还提供一种采用上述任意一项方法形成的半导体器件。
与现有技术相比，本发明的技术方案具有以下有益效果：
本发明技术方案提供的半导体器件的形成方法中，基底具有第一区和第二区，第二区位于基底中间位置，第一区和第二区的鳍部分别用于形成相同导电类型的晶体管。第一掺杂区的掺杂浓度低于第二掺杂区的掺杂浓度，使得第一区的晶体管的阈值电压比第二区的晶体管阈值电压低，第二区晶体管的沟道开启电压较大，沟道内的电流较小，第二区的鳍部产生的热量较少，中间区域内不容易发生热量的集聚，自发热效应不显著，从而提高了半导体器件的性能。
本发明技术方案提供的半导体器件的形成方法中，基底具有第一区和第二区，第二区位于基底中间位置，通过控制横跨鳍部的栅极结构中第一区的第一调节功函数层和第二调节功函数层的功函数值，使得位于中间位置的第二区的鳍部内沟道区的阈值电压较高，中间位置第二区鳍部中的沟道电流减小，第二区鳍部沟道内产生的热量较少，中间区域内不容易发生热量的集聚，自发热效应不显著，从而提高了半导体器件的性能。
附图说明
图1至图2是一种半导体器件形成过程的结构示意图；
图3至图5是本发明一实施例中半导体器件形成过程的结构示意图；
图6至图11是本发明另一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有技术的半导体器件的性能较差。
图1至图2是一种半导体器件形成过程的结构示意图。
参考图1，提供半导体衬底100，所述半导体衬底100上具有隔离结构101和多个鳍部110，所述隔离结构101覆盖鳍部110部分侧壁；在隔离结构101上形成图形化层102，所述图形化层102暴露出鳍部110；以所述图形化层102为掩膜，对所述鳍部110进行离子注入。
参考图2，图2为半导体器件的俯视图，进行离子注入后，在隔离结构101上形成横跨鳍部110的伪栅极结构120；形成伪栅极结构后，在伪栅极结构120两侧的鳍部110内形成源漏掺杂区130。
随着半导体技术的发展，半导体器件的尺寸越来越小，鳍部与鳍部之间的距离相应缩小，然而器件的密度增加，半导体器件的热量难以通过半导体衬底快速传导出去，而半导体器件边缘区的鳍部边缘空间较大，热量易于挥发，半导体器件中间区鳍部的沟道区的热量难以传导出去，从而导致半导体器件中间区鳍部的温度较高，从而导致半导体器件形成较差。
本发明，通过对中间区的鳍部进行掺杂或控制横跨中间区鳍部的栅极结构的功函数层的功函数值，增加中间区鳍部的阈值电压，从而降低中间区鳍部的沟道区的离子电流，降低中间区鳍部产生的热量，减小半导体器件的自发热效应，所述方法提高了半导体器件的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图5是本发明一实施例中半导体器件形成过程的结构示意图。
请参考图3，提供基底。
本实施例中，所述基底包括：半导体衬底200和位于半导体衬底200表面的若干分立的鳍部210。在其他实施例中，所述基底还可以为平面衬底。
本实施例中，所述半导体衬底200包括第一区A和第二区B，所述第一区A与第二区B邻接且位于第二区B两侧，所述半导体衬底200的第一区A和第二区B内具有鳍部210。
本实施例中，所述半导体衬底200的材料为单晶硅。所述半导体衬底200还可以是多晶硅或非晶硅。所述半导体衬底200的材料还可以为锗、锗化硅、砷化镓等半导体材料。所述半导体衬底200还能够是绝缘体上半导体结构，所述绝缘体上半导体结构包括绝缘体及位于绝缘体上的半导体材料层，所述半导体材料层的材料包括硅、锗、硅锗、砷化镓或铟镓砷等半导体材料。
本实施例中，所述若干鳍部210通过图形化所述半导体衬底200而形成。在其它实施例中，可以是：在所述半导体衬底上形成鳍部材料层，然后图形化所述鳍部材料层，从而形成鳍部210。
本实施例中，所述鳍部210的材料为单晶硅。在其它实施例中，所述鳍部210的材料为单晶锗硅或者其它半导体材料。
本实施例中，所述半导体衬底200上还具有隔离层201，所述隔离层201覆盖鳍部210的部分侧壁表面，且所述隔离层201表面低于所述鳍部210的顶部表面。所述隔离层201的材料包括氧化硅。
本实施例中，所述鳍部210的表面具有保护层(未图示)，所述保护层在后续对鳍部210进行离子注入时保护鳍部210。
所述保护层的材料包括氮化硅、氮碳化硅、氮硼化硅、氮碳氧化硅或氮氧化硅，本实施例中，所述保护层的材料为氧化硅。
其他实施例中，所述基底还包括第三区，所述第三区位于第一区和第二区之间，所述第三区与第一区和第二区相邻。
在第一区的鳍部内形成第一掺杂区；在第二区的鳍部内形成第二掺杂区，第一掺杂区的掺杂离子浓度比第二掺杂区低，第二掺杂区与第一掺杂区的掺杂离子类型相同。
所述第一掺杂区的形成工艺包括离子注入工艺或者固态源掺杂工艺。
所述第二掺杂区的形成工艺包括离子注入工艺或者固态源掺杂工艺。
在一实施例中，第一掺杂区的形成工艺为离子注入工艺，第二掺杂区的形成工艺为固态源掺杂工艺。
在另一实施例中，第一掺杂区的形成工艺为固态源掺杂工艺，第二掺杂区的形成工艺为离子注入工艺。
本实施例中，所述第一掺杂区和第二掺杂区的形成工艺均为离子注入工艺，所述第一掺杂区和第二掺杂区的形成方法如图4至图5所示。
参考图4，在所述基底上形成要成掩膜层202，所述掩膜层202暴露出第一区A和第二区B的鳍部210的位置和形状。
所述掩膜层202的材料包括氧化硅、氮化硅或有机材料涂层。
本实施例中，所述掩膜层202的材料为光刻胶，掩膜层202采用涂布工艺以及涂布工艺之后的光刻工艺形成。
所述掩膜层202在后续进行离子注入时提供掩膜保护半导体衬底200。
本实施例中，所述掩膜层202的材料为光刻胶。所述掩膜层202的形成方法包括：在半导体衬底200的表面旋涂形成初始掩膜层(未图示)；对所述初始掩膜层进行曝光和显影处理，暴露出第一区A和第二区的鳍部210的位置和形状，形成所述掩膜层202。
其他实施例中，所述掩膜层202的材料为氧化硅或者氮化硅，所述掩膜层202的形成方法包括：在半导体衬底200的表面形成初始掩膜层，所述初始掩膜层的材料为氧化硅或者氮化硅；在初始掩膜层表面形成第一图像化层，所述第一图形化层暴露出第一区A和第二区B的的鳍部210的位置和形状；以所述第一图形化层为掩膜，刻蚀所述初始掩膜层直至暴露出半导体衬底200的表面，形成掩膜层202。所述第一图形化层的材料为光刻胶。
所述掩膜层距离第一区边缘鳍部的距离为30nm～300nm。
所述掩膜层距离第一区边缘鳍部的距离小于30nm，掩膜层的阴影效应范围会到达第二区的鳍部，影响到第二区的鳍部的掺杂；所述掩膜层距离第一区边缘鳍部的距离大于300nm，如利用离子注入时掩膜层的阴影效应达到相同的效果，需要的掩膜层厚度过厚，同时效果不佳。
所述掩膜层距离鳍部顶部的高度为鳍部高度的N倍，N为大于等于1的整数，N为第一区一侧的第二区内的鳍部的个数。
本实施例中，所述掩膜层作为离子注入的掩膜层，主要利用的是掩膜层的高度和距离的结合，再与离子注入时的倾斜角度相结合，利用阴影效应，使得离掩膜层较近的第一区的掺杂离子浓度较低或者不能获得掺杂离子，则第二区的掺杂离子浓度高于第一区的掺杂离子浓度，使得第二区的晶体管的阈值电压高于第一区的晶体管的阈值电压，第二区晶体管的沟道开启电压较大，沟道内的电流较小，第二区的鳍部产生的热量较少，中间位置的鳍部温度较低，中间区域内不容易发生热量的集聚，自发热效应不显著，从而提高了半导体器件的性能。
参考图5，形成所述掩膜层202后，以所述掩膜层202为掩膜，对所述第一区A和第二区B的鳍部210进行离子注入，使得第二区B内鳍部中的离子掺杂浓度高于第一区A内鳍部中离子掺杂的浓度。
本实施例中，对所述第一区A和第二区B的鳍部210进行离子注入的方法包括：以所述掩膜层202为掩膜，对所述第一区A和第二区B的鳍部210进行第一离子注入；第一离子注入后，对所述第一区A和第二区B的鳍部210进行第二离子注入，所述第一离子注入的方向和第二离子注入的方向沿半导体衬底法线方向对称，所述第一离子注入和第二离子注入的方向平行于鳍部的延伸方向。
当所述鳍部用于形成N型器件时，所述掺杂离子为P型离子，包括磷离子或砷离子。当所述鳍部用于形成P型器件时，所述掺杂离子为N型离子，包括硼离子、BF2-离子或铟离子。
本实施例中，所述鳍部用于形成N型器件，所述第一离子注入或第二离子注入的参数包括：所述注入离子包括磷离子或砷离子，能量范围为10KeV～30KeV，剂量范围为1E13atom/cm2～5E14atom/cm2，倾斜角度为10度～40度；所述倾斜角度为注入方向与基底所在平面的法线之间的夹角。
所述倾斜角度位于10度～40度之间，配合掩膜层的厚度和距离第一区边缘鳍部的距离，能够保证在该角度范围内，第一区的鳍部位于掩膜层的阴影效应区域内，从而使得第二掺杂区的掺杂浓度高于第一掺杂区的掺杂浓度，使得第一区的晶体管的阈值电压比第二区的晶体管阈值电压低，第二区晶体管的沟道开启电压较大，沟道内的电流较小，第二区的鳍部产生的热量较少，中间位置的鳍部温度较低，中间区域内不容易发生热量的集聚，自发热效应不显著，提高半导体器件的性能。
假设鳍部的宽度为D1，鳍部的高度为H1，第一区A内边缘鳍部到掩膜层的距离为A1，鳍部之间的距离为A2，掩膜层的高度为H2，H2＝(N+1)H1，离子注入的倾斜角度为α，则
Figure BDA0001680485920000091
其他实施例中，所述鳍部用于形成P型器件，所述第一离子注入或第二离子注入的参数包括：所述注入离子包括硼离子或BF2-离子，能量范围为35KeV～30KeV，剂量范围为1E13atom/cm2～5E14atom/cm2，倾斜角度为10度～40度；所述倾斜角度为注入方向与基底所在平面的法线之间的夹角。
第二离子注入后还包括对第一区A和第二区B鳍部210进行退火处理，以便修复离子注入工艺对鳍部的损伤，同时激活鳍部内的掺杂离子。
在另一实施例中，所述第一掺杂区和第二掺杂区的形成工艺均为固态源掺杂工艺，对所述第一区A和第二区B鳍部进行掺杂的工艺为固态源掺杂工艺。
所述第一掺杂区和第二掺杂区的形成方法包括：在所述基底第一区的鳍部表面形成具有第一掺杂离子的第一掺杂层，所述第一掺杂层内的离子浓度为第一浓度；在所述基底第二区的鳍部表面形成具有第二掺杂离子的第二掺杂层，所述第一掺杂离子和第二掺杂离子的掺杂离子类型相同，所述第二掺杂层内的离子浓度为第二浓度，所述第二浓度大于第一浓度；形成第一掺杂层和第二掺杂层后，对所述第一掺杂层、第二掺杂层和进行退火处理，使得所述第一掺杂离子进入第一区的鳍部，使得所述第二掺杂离子进入第二区的鳍部。
当所述鳍部用于形成P型器件时，所述第一掺杂层的材料包括硅或硅锗；所述第一掺杂离子为P型离子，所述第一掺杂离子包括磷离子或砷离子，所述第二掺杂层的材料包括硅或硅锗；所述第二掺杂离子为P型离子，所述第二掺杂离子包括磷离子或砷离子。
当所述鳍部用于形成N型器件时，所述第一掺杂层的材料包括氧化硅或氮化硅；所述第一掺杂离子为N型离子，所述第一掺杂离子包括硼离子、BF2-离子或铟离子，所述第二掺杂层的材料包括氧化硅或氮化硅；所述第二掺杂离子为N型离子，所述第二掺杂离子包括硼离子、BF2-离子或铟离子。
在一实施例中，所述基底还包括第三区，所述第三区位于第一区和第二区之间，所述第三区与第一区和第二区相邻；在所述第三区的鳍部内形成第三掺杂区，所述第三掺杂区的掺杂离子浓度高于第一掺杂区，所述第三掺杂区的掺杂离子浓度小于第二掺杂区，第三掺杂区的掺杂离子类型与第一掺杂区或第二掺杂区的掺杂离子类型相同。
在所述第三区的鳍部内形成第三掺杂区的工艺包括：离子注入工艺或者固态源掺杂工艺。
形成第一掺杂区和第二掺杂区后，在第一掺杂区和第二掺杂区上形成横跨鳍部的栅极结构。
所述栅极结构包括栅介质层和位于栅介质层表面的栅极层，所述栅介质层覆盖鳍部部分顶部和部分侧壁表面。
相应的，本实施例还提供一种采用图3至图5方法形成的半导体器件。
图6至图11是本发明另一实施例中半导体器件形成过程的结构示意图。
请参考图6，提供基底。
所述基底包括半导体衬底300以及位于半导体衬底300上的多个分立的鳍部310，所述基底上还具有隔离层301，所述隔离层301覆盖部分鳍部310的侧壁。
所述半导体衬底300包括第一区A和第二区B，所述第一区A与第二区B邻接且位于第二区B两侧，所述半导体衬底300的第一区A和第二区B内具有鳍部310。
所述半导体衬底、鳍部、和隔离层的形成步骤、材料、尺寸、形状，如图3所述，在此不做赘述。
继续参考图6，在所述基底上形成介质层330，所述介质层330内具有开口302。
所述介质层330用于实现不同半导体器件之间的电隔离。
所述开口302的形成方法包括：在基底上形成横跨鳍部的伪栅极结构，所述伪栅极结构包括伪栅介质层和位于伪栅介质层表面的伪栅极层；在所述基底表面形成介质层；所述介质层的表面与所述伪栅结构的顶部表面齐平；去除所述伪栅结构，在介质层内形成开口。
所述介质层330的形成方法包括：在所述基底表面形成覆盖伪栅极结构的顶部表面的初始介质层；形成初始介质后，平坦化所述初始介质层直至暴露出所述伪栅极结构的顶部表面。
所述开口302的形成方法还包括：在形成初始介质层之前，在所述伪栅结构两侧的鳍部310内形成源漏掺杂层。
所述源漏掺杂层包括位于伪栅极结构两侧的多个分立鳍部中的多个源漏掺杂层单元。
本实施例中，所述伪栅极层材料为多晶硅，所述伪栅介质层的材料为氧化硅。
所述介质层330的材料包括氧化硅或氮化硅。本实施例中，所述介质层330的材料为氧化硅。
参考图7，在所述开口302底部表面形成栅介质层322。
本实施例中，在所述开口302底部表面形成栅介质层322之前还包括：在所述开口302底部暴露出的鳍部310表面形成界面层321，所述栅介质层322位于开口302底部表面和界面层321表面。
所述界面层321用于提高所述栅介质层322与鳍部310之间的结合强度，并用于修复所述栅介质层322与鳍部310之间界面处的缺陷。
所述界面层321的形成工艺为氧化工艺，例如热氧化工艺或湿法氧化工艺。
本实施例中，所述界面层321的形成工艺为热氧化工艺。
所述界面层321的材料为氧化硅或氮氧化硅。
本实施例中，所述界面层321的材料为氧化硅。
所述栅介质层322的材料为高K(K大于3.9)介质材料，所述栅介质层322的材料包括氧化铪、氧化锆、氧化铪硅、氧化镧、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛或氧化铝。
本实施例中，所述栅介质层322的材料为氧化铪。
形成所述栅介质层322的工艺包括化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。
本实施例中，形成所述栅介质层322的工艺为化学气相沉积工艺。
形成栅介质层322后，在位于第一区的开口内形成位于栅介质层表面的第一调节功函数层；在形成第一调节功函数层之前或之后，在位于第二区的开口内形成位于栅介质层表面的第二调节功函数层，所述第二调节功函数层的功函数值和第一调节功函数层的功函数值不同，第一调节功函数层和第二调节功函数层的功函数类型相同。
当所述鳍部用于形成N型器件时，所述第一调节功函数层和第二调节功函数层的材料为N型功函数材料；当所述鳍部用于形成P型器件时，所述第一调节功函数层和第二调节功函数层的材料为P型功函数材料。
本实施例中，所述第一调节功函数层的厚度与第二调节功函数层的厚度不同，所述第一调节功函数层的厚度小于第二调节功函数层的厚度。所述第一调节功函数层和第二调节功函数层的形成方法请参考图8至图9所示。
请参考图8，形成所述栅介质层322后，在位于第二区B的开口310内的鳍部310上的栅介质层322表面的第一功函数层323。
所述第一功函数层323为第二区B内鳍部310上功函数层的一部分，用于调节第二区B内鳍部310上功函数层的厚度，使得第二区B内鳍部310上功函数层的阈值电压高于第一区A内的鳍部310上功函数层的阈值电压。
所述第一功函数层323的形成方法包括：开口310内的鳍部310上的栅介质层322表面形成第一功函数材料层；形成第一功函数材料层后，在第一功函数材料层表面形成第二图形化层，所述第二图形化层暴露出第一区A内的开口310的位置和形状；以所述第二图形化层为掩膜，刻蚀去除第一区A内的开口302内的栅介质层322表面的第一功函数材料层，形成第一功函数层323。
本实施例中，所述鳍部用于形成N型器件，所述第一调节功函数层和第二调节功函数层的材料为N型功函数材料，所述N型功函数材料包括：TiN或TaN。
在一实施例中，所述鳍部用于形成P型器件，所述第一调节功函数层和第二调节功函数层的材料为P型功函数材料，所述P型功函数材料包括：TaC、Ti、Al或TiAl。
本实施例中，所述第一功函数层323的材料为N型功函数材料，所述N型功函数材料包括TiN或TaN。
本实施例中，所述第一功函数层323的材料为TiN；所述第一功函数层的厚度为10埃～30埃。所述第一功函数层323厚度小于10埃，对第二区B内的功函数层的调节作用有限，所述第一功函数层323厚度大于30埃，对半导体器件的阈值电压调节过多，不利于半导体器件的性能。
所述第一功函数材料层的形成工艺包括化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。
本实施例中，形成栅介质层322后，形成所述第一功函数层323之前，还包括：在所述开口310的侧壁和底部形成位于栅介质层322表面的覆盖层(未图示)。
所述覆盖层避免栅介质层322暴露在后续退火处理的工艺气体中，同时在形成第一功函数层的过程中保护栅介质层322，同时和后续形成的功函数层共同调节晶体管的阈值电压。
所述覆盖层205的材料包括TiN或TaN。
其他实施例中，不形成所述覆盖层。
请参考图9，形成所述第一功函数层323后，在开口302内的鳍部310上形成第二功函数层324。
所述第二功函数层324位于第一区A和第二区B的开口302内。
所述第二功函数层324用于保护所述栅介质层322，避免后续栅电极层的材料向所述栅介质层322内扩散，从而保证栅介质层322的介电常数不易发生变化，则所形成的晶体管的阈值电压不易发生偏移。
本实施例中，所述第二功函数层324的材料为N型功函数材料，所述N型功函数材料包括TiN或TaN。
所述第二功函数层324的材料包括TiN或TaN。
本实施例中，所述第二功函数层的材料为TiN。
第一区A内的鳍部310上的第一调节功函数层包括位于第一区A上的开口310内的鳍部310上的第二功函数层324。
第二区B内的鳍部310上的第二调节功函数层包括位于第一区A上的开口310内的鳍部310上的第一功函数层323和位于第一功函数层323表面的第二功函数层324。
本实施例中，通过控制所述第一功函数层323的厚度，使得第一区A内的鳍部310上的第一调节功函数层厚度小于第二区B内的鳍部310上的第二调节功函数层，使得位于中间位置的第二区B的鳍部310内沟道区的阈值电压较高，中间位置第二区B鳍部310中的沟道电流减小，第二区B鳍部210沟道内产生的热量较少，中间位置的鳍部310温度较低，中间区域内不容易发生热量的集聚，自发热效应不显著，从而提高了半导体器件的性能。
当所述鳍部用于形成N型器件时，所述第一调节功函数层和第二调节功函数层的材料为N型功函数材料；所述N型功函数材料包括：TiN或TaN。还可以通过控制第一调节功函数层和第二调节功函数层内氮原子百分比浓度，使得第一调节功函数层的功函数值小于第二调节功函数层的功函数值。
本实施例中，所述第一调节功函数层和第二调节功函数层的材料为TiN。
通过控制第一调节功函数层和第二调节功函数层内氮原子百分比浓度，使得第二调节功函数层内的氮原子百分比浓度高于第一调节功函数层的氮原子百分比浓度，使得第二区B上的鳍部310内的晶体管的阈值电压增高，第二区B上的鳍部310沟道区的电流减小，第二区B内的晶体管产生的热量减小，多鳍部器件的自发热效应减小，从而提高半导体器件的性能。
本实施例中，所述第一调节功函数层和第二调节功函数层的形成方法包括：在位于开口内的鳍部上的栅介质层表面形成初始第一调节功函数层，回刻蚀第一区开口内的初始第一调节功函数层，在第二区的开口内形成第一调节功函数层；形成第一功函数层后，在第一区的开口内的鳍部上形成第二调节功函数层。
请参考图10，形成第二功函数层324，在开口310内所述第二功函数层324表面形成栅电极材料层340。
所述栅电极材料层340为后续形成栅电极层提供材料层。
形成栅电极材料层340的工艺包括：等离子体化学气相沉积工艺、低压化学气相沉积工艺、电镀工艺或溅射工艺。
所述栅电极材料层340的材料为金属材料，所述金属材料包括铜、钨、镍、铬、钛、钽和铝中的一种或多种组合。
所述栅电极材料层340的形成工艺为物理气相沉积工艺和电镀工艺中的一种或两种组合。本实施例中所述栅电极材料层340的形成工艺为物理气相沉积工艺。
本实施例中，形成第二功函数层324后，形成栅电极材料层340之前，在第二功函数层324表面形成阻挡层(未图示)，所述阻挡层用于保护第二功函数层324。
其他实施例中，不形成所述阻挡层。
所述阻挡层的材料包括TaN、Ta及其组合。
本实施例中，所述阻挡层的材料为TaN。
本实施例中，覆盖层、第一功函数层323、阻挡层和第二功函数层324共同调节所要形成的半导体器件的阈值电压，所述阻挡层厚度过厚，不利于半导体器件阈值电压的调节，所述阻挡层厚度过薄，对第二功函数层的保护效果不佳，从而影响半导体器件的性能。
所述阻挡层的形成工艺包括化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。
参考图11，形成栅电极材料层340后，平坦化所述栅电极材料层340、第二功函数层324、栅介质层322，直至露出介质层330的顶部表面，形成栅电极层325，所述栅电极层325填充满所述开口302。
本实施例中，平坦化所述栅电极材料层340、阻挡层、第二功函数层324、栅介质层322，直至暴露出介质层330的顶部表面，形成栅电极层325。
相应的，本实施例还提供一种采用图6至图11方法形成的半导体器件。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (7)

1.一种半导体器件的形成方法，其特征在于，包括：
提供基底，所述基底包括第一区和第二区，所述第一区与第二区邻接且位于第二区两侧，所述基底第一区和第二区上具有多个分立的鳍部；
在所述基底上形成介质层，所述介质层内具有开口，所述开口暴露出部分鳍部表面；
在所述开口底部表面形成栅介质层；
在位于第一区的开口内形成位于栅介质层表面的第一调节功函数层；
在形成第一调节功函数层之前或之后，在位于第二区的开口内形成位于栅介质层表面的第二调节功函数层，所述第二调节功函数层的功函数值和第一调节功函数层的功函数值不同，第一调节功函数层和第二调节功函数层的功函数类型相同；
形成第一调节功函数层和第二调节功函数层后，在所述开口内形成栅电极层，所述栅电极层填充满所述开口；
通过控制栅极结构的功函数层的功函数值实现第二区鳍部上的功函数层阈值电压高于第一区鳍部上的功函数层的阈值电压。
2.根据权利要求1所述的半导体器件的形成方法，其特征在于，当所述鳍部用于形成N型器件时，所述第一调节功函数层和第二调节功函数层的材料为N型功函数材料；当所述鳍部用于形成P型器件时，所述第一调节功函数层和第二调节功函数层的材料为P型功函数材料。
3.根据权利要求2所述的半导体器件的形成方法，其特征在于，所述第一调节功函数层的厚度小于第二调节功函数层的厚度。
4.根据权利要求2所述的半导体器件的形成方法，其特征在于，所述N型功函数材料包括：TiN或TaN。
5.根据权利要求2所述的半导体器件的形成方法，其特征在于，所述P型功函数材料包括：TaC、Ti、Al或TiAl。
6.根据权利要求4所述的半导体器件的形成方法，其特征在于，所述第二调节功函数层内的氮原子百分比浓度高于第一调节功函数层的氮原子百分比浓度。
7.一种根据权利要求1至6任意一项方法形成的半导体器件。
CN201810551963.9A 2018-05-31 2018-05-31 半导体器件及其形成方法 Active CN110556337B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201810551963.9A CN110556337B (zh) 2018-05-31 2018-05-31 半导体器件及其形成方法
US16/419,416 US10971405B2 (en) 2018-05-31 2019-05-22 Semiconductor devices and fabrication methods thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810551963.9A CN110556337B (zh) 2018-05-31 2018-05-31 半导体器件及其形成方法

Publications (2)

Publication Number Publication Date
CN110556337A CN110556337A (zh) 2019-12-10
CN110556337B true CN110556337B (zh) 2021-09-07

Family

ID=68694241

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810551963.9A Active CN110556337B (zh) 2018-05-31 2018-05-31 半导体器件及其形成方法

Country Status (2)

Country Link
US (1) US10971405B2 (zh)
CN (1) CN110556337B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11018234B2 (en) 2018-07-26 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11380548B2 (en) * 2019-12-30 2022-07-05 Taiwan Semiconductor Manufacturing Company Ltd. Method of manufacturing semiconductor structure through multi-implantation to fin structures

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107316904A (zh) * 2016-04-25 2017-11-03 台湾积体电路制造股份有限公司 FinFET及其形成方法
CN107768367A (zh) * 2016-08-17 2018-03-06 台湾积体电路制造股份有限公司 半导体组件
CN107919323A (zh) * 2016-10-10 2018-04-17 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130256802A1 (en) * 2012-03-27 2013-10-03 International Business Machines Corporation Replacement Gate With Reduced Gate Leakage Current
US9306067B2 (en) * 2014-08-05 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Nonplanar device and strain-generating channel dielectric
US9633908B2 (en) * 2015-06-16 2017-04-25 International Business Machines Corporation Method for forming a semiconductor structure containing high mobility semiconductor channel materials
US9905467B2 (en) * 2015-09-04 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US10438948B2 (en) * 2016-01-29 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method and device of preventing merging of resist-protection-oxide (RPO) between adjacent structures
CN107026126B (zh) * 2016-02-02 2021-01-26 联华电子股份有限公司 半导体元件及其制作方法
US9748235B2 (en) * 2016-02-02 2017-08-29 Globalfoundries Inc. Gate stack for integrated circuit structure and method of forming same
WO2018063359A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Multi voltage threshold transistors through process and design-induced multiple work functions
US10510762B2 (en) * 2016-12-15 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Source and drain formation technique for fin-like field effect transistor
US10170555B1 (en) * 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Intermetallic doping film with diffusion in source/drain
CN109390401B (zh) * 2017-08-10 2022-07-05 联华电子股份有限公司 半导体元件及其制作方法
US10453753B2 (en) * 2017-08-31 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET
US10460993B2 (en) * 2017-11-30 2019-10-29 Intel Corporation Fin cut and fin trim isolation for advanced integrated circuit structure fabrication
US10170577B1 (en) * 2017-12-04 2019-01-01 International Business Machines Corporation Vertical transport FETs having a gradient threshold voltage
US10453844B2 (en) * 2017-12-06 2019-10-22 International Business Machines Corporation Techniques for enhancing vertical gate-all-around FET performance
US10354922B1 (en) * 2017-12-27 2019-07-16 International Business Machines Corporation Simplified block patterning with wet strippable hardmask for high-energy implantation
US10734478B2 (en) * 2018-03-19 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11410890B2 (en) * 2018-06-28 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial layers in source/drain contacts and methods of forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107316904A (zh) * 2016-04-25 2017-11-03 台湾积体电路制造股份有限公司 FinFET及其形成方法
CN107768367A (zh) * 2016-08-17 2018-03-06 台湾积体电路制造股份有限公司 半导体组件
CN107919323A (zh) * 2016-10-10 2018-04-17 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
US10971405B2 (en) 2021-04-06
CN110556337A (zh) 2019-12-10
US20190371679A1 (en) 2019-12-05

Similar Documents

Publication Publication Date Title
TWI591697B (zh) 在鰭式場效電晶體中形成擊穿中止區域的方法
TWI415263B (zh) 半導體裝置及其製造方法
US20210272850A1 (en) Method for fabricating a semiconductor device
US8159038B2 (en) Self aligned silicided contacts
US7737009B2 (en) Method of implanting a non-dopant atom into a semiconductor device
US20130240990A1 (en) Semiconductor structure and method for manufacturing the same
US9698241B1 (en) Integrated circuits with replacement metal gates and methods for fabricating the same
US10361279B2 (en) Method for manufacturing FinFET structure with doped region
US20160351675A1 (en) Integrated circuits and methods for fabricating integrated circuits having replacement metal gate electrodes
US10056461B2 (en) Composite masking self-aligned trench MOSFET
US20240234548A1 (en) Method for manufacturing semiconductor structure with source/drain structure having modified shape
TWI815949B (zh) 金屬閘極形成方法及其形成結構
US20120007166A1 (en) Non-volatile memory device using finfet and method for manufacturing the same
US20140203353A1 (en) Method for manufacturing semiconductor device and semiconductor device
US11355634B2 (en) Semiconductor device and fabrication method thereof
CN110556337B (zh) 半导体器件及其形成方法
US20180012888A1 (en) Semiconductor structure and fabrication method thereof
CN107591367B (zh) 半导体结构的制造方法
US11581320B2 (en) Semiconductor device
CN110718463B (zh) 隧穿场效应晶体管及其形成方法
CN109087939B (zh) 半导体结构的形成方法、ldmos晶体管及其形成方法
CN110610855A (zh) 制造半导体装置的方法
CN110534432B (zh) 半导体器件及其形成方法
CN109273528B (zh) 半导体器件及其形成方法
CN115565877A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant