TWI538217B - 鰭式場效電晶體裝置及其製作方法 - Google Patents

鰭式場效電晶體裝置及其製作方法 Download PDF

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TWI538217B
TWI538217B TW104101342A TW104101342A TWI538217B TW I538217 B TWI538217 B TW I538217B TW 104101342 A TW104101342 A TW 104101342A TW 104101342 A TW104101342 A TW 104101342A TW I538217 B TWI538217 B TW I538217B
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layer
semiconductor material
field effect
effect transistor
fin
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TW104101342A
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TW201541645A (zh
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江國誠
馮家馨
張智勝
吳志強
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台灣積體電路製造股份有限公司
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Description

鰭式場效電晶體裝置及其製作方法
本揭露是關於一種鰭式場效電晶體裝置之結構及其製作方法。
半導體積體電路產業近來經歷了指數性的成長。隨著積體電路材料與設計之技術進步，創造了許多個積體電路世代，每個積體電路世代都較先前世代具有更小且更複雜之電路。在積體電路演進的過程中，功能性密度(例如每晶片區域互相連接的元件數量)逐漸地增加，而幾何尺寸(例如製程上所能產生的最小的元件(或線))亦逐漸地縮小。體積的縮小提高了生產效率並降低了相關成本。
體積的縮小也提高了積體電路處理與製造的複雜性，為了實現這些進步，積體電路處理與製造的相關發展是需要的。舉例而言，立體式電晶體，例如鰭式場效電晶體(Fin-like field-effect transistor；FINFET)，已被引進而取代了平面式電晶體。雖然目前的鰭式場效電晶體裝置與其製作方法足已達到其預期之目的，但在各方面而言，鰭式場效電晶體裝置與其製作方法仍尚未達到完美。
本揭露提供鰭式場效電晶體裝置之一實施方式。鰭式場效電晶體裝置包含基板與第一鰭狀結構，基板具有第一閘極區，第一鰭狀結構位於基板上之第一閘極區內。第一鰭狀結構包含上半導體材料件、下半導體材料件以及襯墊，下半導體材料件受到氧化物特徵圍繞，襯墊包覆下半導體材料件之氧化物特徵並向上延伸至包覆上半導體材料件之下部份。鰭式場效電晶體裝置亦包含介電層，介電層側向地鄰近上半導體材料件之中央部份。如此一來，上半導體材料件包含上部份，上部份不側向地鄰近介電層，亦不受襯墊包覆。
本揭露提供鰭式場效電晶體裝置之另一實施方式。鰭式場效電晶體裝置包含基板、第一鰭狀結構、第二鰭狀結構。基板具有N型鰭式場效電晶體區域與P型鰭式場效電晶體區域。第一鰭狀結構位於基板上之N型鰭式場效電晶體區域，第一鰭狀結構包含磊晶矽(Si)層、磊晶矽鍺(SiGe)層、襯墊以及介電層。磊晶矽層作為第一鰭狀結構之上部份。磊晶矽鍺層作為第一鰭狀結構之下部份，磊晶矽鍺層之外層具有矽鍺氧化物(SiGeO)特徵。襯墊包覆矽鍺氧化物特徵，並向上延伸至包覆磊晶矽層之下部份。介電層側向地鄰近磊晶矽層之中央部份，其中上部份之磊晶矽層包含上部份，上部份不側向地鄰近介電層，亦不受襯墊包覆。第二鰭狀結構位於基板上之P型鰭式場效電晶體區域，第二鰭狀結構包含磊晶矽鍺層、磊晶矽層、另一磊晶矽鍺 層、襯墊以及介電層。磊晶矽鍺層作為第二鰭狀結構之上部份。磊晶矽層作為第二鰭狀結構之中部份。另一磊晶矽鍺層作為第二鰭狀結構之下部份。襯墊包覆較低之磊晶矽鍺層與中部份之磊晶矽層，並向上延伸至包覆上部份之磊晶矽鍺層的下部份。介電層，側向地鄰近上部份之磊晶矽鍺層之一中央部份，其中上部份之磊晶矽鍺層包含上部份，上部份不側向地鄰近介電層，亦不受襯墊包覆。
本揭露提供鰭式場效電晶體裝置之一種製作方法。製作方法包含提供具有N型鰭式場效電晶體區域與P型鰭式場效電晶體區域之基板、形成多個第一鰭狀結構於N型鰭式場效電晶體區域與P型鰭式場效電晶體區域。每一第一鰭狀結構包含第一磊晶半導體材料層，作為其上部份；第二磊晶半導體材料層，作為其中央部份；以及第三磊晶半導體材料層，作為其下部份。製作方法亦包含形成圖案化氧化物硬式遮罩於N型鰭式場效電晶體區域與P型鰭式場效電晶體區域，以露出位於N型鰭式場效電晶體區域之第一閘極區之第一鰭狀結構。製作方法亦包含退火以形成半導體氧化物特徵於位於第一閘極區之第一鰭狀結構之第二半導體材料層之外層。製作方法亦包含形成襯墊，襯墊包覆位於N型鰭式場效電晶體區域與P型鰭式場效電晶體區域兩者之第一鰭狀結構；設置介電層於第一鰭狀結構之間；在將硬式遮罩層覆蓋於N型鰭式場效電晶體區域之後使位於P型鰭式場效電晶體區域之襯墊凹陷；於將硬式遮罩層覆蓋於N型鰭式場效電晶體區域時，形成第二鰭 狀結構於P型鰭式場效電晶體區域；在移除硬式遮罩層之後，使位於N型鰭式場效電晶體區域之襯墊凹陷；以及使位於N型鰭式場效電晶體區域與P型鰭式場效電晶體區域兩者之介電層凹陷。
100‧‧‧方法
102~130‧‧‧步驟
200‧‧‧鰭式場效電晶體裝置
200A‧‧‧N型場效電晶體
200B‧‧‧P型場效電晶體
210‧‧‧基板
212‧‧‧第一半導體材料層
214‧‧‧第二半導體材料層、矽鍺層
216‧‧‧第三半導體材料層、矽層
220‧‧‧第一鰭狀結構
222‧‧‧圖案化之鰭片硬罩層
230‧‧‧凹槽
310‧‧‧圖案化氧化硬式遮罩
312‧‧‧第一區域
314‧‧‧第二區域
322‧‧‧第一半導體氧化物特徵
320‧‧‧第二鰭狀結構
324‧‧‧矽鍺氧化物特徵、第二半導體氧化物特徵
326‧‧‧第三半導體氧化物特徵
402‧‧‧第一層體
450A‧‧‧第一源極/汲極區
450B‧‧‧第二源極/汲極區
460‧‧‧閘極區域
460A‧‧‧第一閘極區
460B‧‧‧第二閘極區
510‧‧‧閘極堆疊
512‧‧‧介電層
514‧‧‧電極層
516‧‧‧閘極硬式遮罩、閘極硬式遮罩層
520‧‧‧間隔物
610A‧‧‧第一源極/汲極特徵
610B‧‧‧第二源極/汲極特徵
720‧‧‧層間介電層
810A‧‧‧第一閘極凹槽
810B‧‧‧第二閘極凹槽
910A‧‧‧第一高介電/金屬閘極堆疊
910B‧‧‧第二高介電/金屬閘極堆疊
t1‧‧‧第一厚度
t2‧‧‧第二厚度
t3‧‧‧第三厚度
404‧‧‧第二層體
405‧‧‧襯墊
410‧‧‧介電層
412‧‧‧介面
415‧‧‧圖案化硬式遮罩
430‧‧‧第四半導體材料層
440‧‧‧第三鰭狀結構
450‧‧‧源極/汲極區域
w1‧‧‧第一寬度
w2‧‧‧第二寬度
d1‧‧‧第一距離
d2‧‧‧第二距離
d3‧‧‧第三距離
A-A‧‧‧線
B-B‧‧‧線
細讀以下詳細敘述並搭配對應之圖式，可了解到本揭露之多個態樣。須注意的是，圖式中的多個特徵並未依照該業界領域之標準作法繪製實際比例。事實上，為了討論的清楚，所述之特徵的尺寸可以任意的增加或減少。
第1圖為根據部份實施方式之鰭式場效電晶體裝置之範例製作方法的流程圖。
第2A圖為根據部份實施方式之處理中的範例鰭式場效電晶體裝置的立體圖。
第2B圖為根據第1圖之方法而處於製造階段之範例鰭式場效電晶體裝置沿第2A圖之線A-A的剖面圖。
第3A圖為根據部份實施方式之處理中的範例鰭式場效電晶體裝置的立體圖。
第3B圖為根據第1圖之方法而處於製造階段之範例鰭式場效電晶體裝置沿第3A圖之線A-A的剖面圖。
第4A圖與第4B圖為根據部份實施方式之處理中的鰭式場效電晶體裝置的立體圖。
第5圖為根據第1圖之方法而處於製造階段之範例鰭式場效電晶體裝置沿第4A圖之線A-A的剖面圖。
第6A圖與第6B圖為根據部份實施方式之處理中的鰭式場效電晶體裝置的立體圖。
第7A圖與第7B圖為根據部份實施方式之處理中的鰭式場效電晶體裝置的立體圖。
第8A圖、第8B圖與第9圖為根據第1圖之方法而處於製造階段之範例鰭式場效電晶體裝置沿第7B圖之線B-B的剖面圖。
第10A圖與第10B圖為根據部份實施方式之處理中的鰭式場效電晶體裝置的立體圖。
第10C圖與第10D圖為根據第1圖之方法而處於製造階段之範例鰭式場效電晶體裝置沿第10A圖之線A-A的剖面圖。
第10E圖為根據第1圖之方法而處於製造階段之範例鰭式場效電晶體裝置沿第10B圖之線B-B的剖面圖。
第11A圖與第11B圖為根據部份實施方式之處理中的鰭式場效電晶體裝置的立體圖。
第12A圖與第12B圖為根據部份實施方式之處理中的鰭式場效電晶體裝置的立體圖。
第13A圖與第13B圖為根據部份實施方式之處理中的鰭式場效電晶體裝置的立體圖。
第13C圖與第13D圖為根據第1圖之方法而處於製造階段之範例鰭式場效電晶體裝置沿第13A圖之線A-A的剖面圖。
第13E圖與第13F圖為根據第1圖之方法而處於製造 階段之範例鰭式場效電晶體裝置沿第13B圖之線B-B之剖面圖。
以下本揭露將提供許多個不同的實施方式或實施例以實現本揭露之多個特徵。許多元件與設置將以特定實施例在以下說明，以簡化本揭露。當然這些實施例僅用以示例而不應用以限制本揭露。舉例而言，敘述「第一特徵形成於第二特徵上」包含多種實施方式，其中涵蓋第一特徵與第二特徵直接接觸，以及額外的特徵形成於第一特徵與第二特徵之間而使兩者不直接接觸。此外，於各式各樣的實施例中，本揭露可能會重複標號以及/或標註字母。此重複是為了簡化並清楚說明，而非意圖表明這些討論的各種實施方式以及/或配置之間的關係。
本揭露是針對，但不限制於，鰭式場效電晶體(Fin-like field-effect transistor；FINFET)裝置。舉例而言，鰭式場效電晶體裝置可以是互補式金屬氧化物半導體(Complementary metal-oxide-semiconductor；CMOS)裝置，此互補式金屬氧化物半導體裝置包含P型金屬氧化物半導體(P-type metal-oxide-semiconductor；PMOS)鰭式場效電晶體裝置以及N型金屬氧化物半導體(N-type metal-oxide-semiconductor；NMOS)鰭式場效電晶體裝置。以下將以鰭式場效電晶體裝置為例說明本發明之多個實施方式。然而，需了解到，除了專利申請範圍所請求的 內容，本專利申請不應限制於任何特定型態的裝置。
第1圖為根據部份實施方式之鰭式場效電晶體裝置200之製作方法100的流程圖。需了解到，額外的步驟可增添於此方法之前、之中、之後，於本揭露之其他實施方式中，上述之步驟其中一些可以被替換或取消。以下透過參照各個圖式，整體地介紹鰭式場效電晶體裝置200與其製作方法100。
參照第1圖與第2A~2B圖，方法100開始於步驟102，其提供基板210。基板210可包含矽塊材基板(bulk silicon substrate)。或著，基板210可包含基本的半導體，例如晶體結構的矽或鍺；化合物半導體，例如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦；或上述之組合。
於另一實施方式中，基板210具有絕緣層覆矽(silicon-on-insulator；SOI)結構，此絕緣層覆矽結構具有絕緣層於基板210內。絕緣層之一例可以是埋藏氧化層(buried oxide layer；BOX)。絕緣層覆矽之基板可以由氧離子直接植入法(separation by implantation of oxygen；SIMOX)、晶圓接合和/或其他適合的方法製成。
於本實施方式中，基板210包含第一半導體材料層212、位於第一半導體材料層212上之第二半導體材料層214和位於第二半導體材料層214上之第三半導體材料層216。第二半導體材料層214與第三半導體材料層216互不相同。第二半導體材料層214具有第一晶格常數，第三半 導體材料層216具有第二晶格常數，第一晶格常數與第二晶格常數不同。於本實施方式中，第二半導體材料層214包含矽鍺(SiGe)，而第一半導體材料層212與第三半導體材料層216皆包含矽(Si)。於多個例子中，第一半導體材料層212、第二半導體材料層214、第三半導體材料層216可包含鍺(Ge)、矽(Si)、砷化鎵(GaAs)、砷化鋁鎵(AlGaAs)、矽鍺(SiGe)、磷砷化鎵(GaAsP)或其他適合的材料。於本實施方式中，第二半導體材料層214與第三半導體材料層216藉由磊晶成長的方式形成，這被稱為覆蓋通道磊晶(blanket channel epi)。於多個例子中，磊晶方式包含化學氣相沉積法(Chemical vapor deposition；CVD)(例如氣相磊晶(Vapor-phase epitaxy；VPE))、超高真空化學氣相沉積法(Ultra-high vacuum；UHV-CVD)、分子束磊晶法和/或其他適合方法。
如同本技術領域中已知的，基板210可根據設計需求而包含有各種摻雜特徵。於部份實施方式中，根據設計需求(例如P型基板或N型基板)，基板210可包含多個摻雜區。於部份實施方式中，摻雜區可以摻雜有P型或N型摻雜物。舉例而言，摻雜區可以摻雜有P型摻雜物，例如硼或二氟化硼(BF2)，N型摻雜物，例如磷或砷，以及/或上述之組合。摻雜區可配置用於N型鰭式場效電晶體(n-type FinFET：NFET)或P型鰭式場效電晶體(p-type FinFET：PFET)。
同時參照第1圖與第3A~3B圖，方法100進行到 步驟104，在基板210內形成第一鰭狀結構220與凹槽230。第一鰭狀結構220具有範圍為大約4奈米至大約10奈米之第一寬度w1。於一實施方式中，圖案化之鰭片硬罩(fin hard mask；FHM)層222形成於基板210上。此圖案化之鰭片硬罩層222包含氧化矽、氮化矽、氮氧化矽或其他合適的介電材料。此圖案化之鰭片硬罩層222可包含單層材料或多層材料。此圖案化之鰭片硬罩層222的形成，可藉由熱氧化法、化學氣相沉積法(Chemical vapor deposition；CVD)、原子層沉積法(Atomic layer deposition；ALD)或其他合適的方法先沉積材料層，再以微影製程形成圖案化之光阻層，並透過圖案化之光阻層的開口而蝕刻材料層，以形成圖案化之鰭片硬罩層222。
範例性的微影製程可包含形成光阻層、藉由微影曝光製程將光阻層曝光、進行曝光後的烘烤製程、以及使光阻層顯影以形成圖案化的光阻層。此微影製程可被其他技術替換，例如電子束寫(e-beam writing)、離子束寫(ion-beam writing)、無光罩圖案化(maskless patterning)法或分子印刷法(molecular printing)。
接著，透過圖案化之鰭片硬罩層222蝕刻基板210，以在基板210內形成第一鰭狀結構220與凹槽230。於另一實施方式中，圖案化之光阻層可直接當作圖案化之鰭片硬罩層222，而作為於基板210內形成第一鰭狀結構220與凹槽230之蝕刻製程的蝕刻遮罩。蝕刻製程可包含濕蝕刻或乾蝕刻。於一實施方式中，濕蝕刻液包含氫氧化四 甲基銨(tetramethylammonium hydroxide；TMAH)、氟化氫(HF)/硝酸(HNO3)/醋酸(CH3COOH)溶液或其他合適的溶液。其各自的蝕刻製程可以藉由各種蝕刻參數進行調整，例如使用的蝕刻劑、蝕刻溫度、蝕刻液的濃度、蝕刻壓力、電源功率、射頻偏壓、射頻偏壓功率、蝕刻劑流動速率和/或其他合適的參數。舉例而言，濕蝕刻液可包含氫氧化銨(NH4OH)、氫氧化鉀(KOH)、氟化氫(HF)、氫氧化四甲基銨(TMAH)、其他合適的濕蝕刻液或上述之材料之組合。乾蝕刻製程包含使用氯基化學的偏壓電漿蝕刻製程。其餘乾蝕刻氣體包含四氟化碳(CF4)、三氟化氮(NF3)、六氟化硫(SF6)以及氦(He)。乾蝕刻可以使用例如深反應式離子蝕刻(deep reactive-ion etching；DRIE)之機制而以非等向性的方法進行。
於本實施方式中，蝕刻深度被控制足以完全露出凹槽230內之第二半導體材料層214與第三半導體材料層216、且部份露出第一半導體材料層212。因此，形成的第一鰭狀結構220具有第三半導體材料層216作為其上部份、第二半導體材料層214作為其中央部份以及第一半導體材料層212作為其下部份。
於部份實施方式中，鰭式場效電晶體裝置200包含N型鰭式場效電晶體，以標號200A標記，而作為N型鰭式場效電晶體200A。鰭式場效電晶體裝置200亦包含P型鰭式場效電晶體，以標號200B標記，而作為P型鰭式場效電晶體。
同時參照第1圖與第4A~4B圖，方法100進行到步驟106，步驟106於基板210上形成圖案化氧化硬式遮罩(patterned oxidation-hard-mask；OHM)310，其包含包覆第一鰭狀結構220之一部份。於本實施方式中，在N型鰭式場效電晶體200A中，此圖案化氧化硬式遮罩310覆蓋基板210之第一區域312並露出第二區域314。在P型鰭式場效電晶體200B中，此圖案化氧化硬式遮罩310完全包覆第一鰭狀結構220。圖案化氧化硬式遮罩310可包含氧化矽、氮化矽、氮氧化矽、或其他合適的介電材料。圖案化氧化硬式遮罩310的形成，可藉由熱氧化法、化學氣相沉積法(Chemical vapor deposition；CVD)、原子層沉積法(Atomic layer deposition；ALD)或其他合適的方法先沉積材料層，再以微影製程形成圖案化之光阻層，透過圖案化之光阻層的開口而蝕刻材料層，而形成圖案化氧化硬式遮罩310。
同時參照第1圖、第4A圖與第5圖，方法100進行到步驟108，將鰭式場效電晶體裝置200進行熱氧化處理。於一實施方式中，熱氧化處理是於含氧的環境中進行。於另一實施方式中，熱氧化處理是於含有氧氣與水蒸氣的環境中進行。在N型鰭式場效電晶體200A之第二區域314內，於熱氧化處理的過程中，第一半導體材料層212、第二半導體材料層214與第三半導體材料層216之至少外層，分別被轉化為第一半導體氧化物特徵322、第二半導體氧化物特徵324與第三半導體氧化物特徵326。在此同時，在N型鰭式場效電晶體200A之第一區域312內，如同整個P 型鰭式場效電晶體200B，第一鰭狀結構220皆藉由圖案化氧化硬式遮罩310而免於氧化。因此，此熱氧化處理是具選擇性的氧化處理。
在熱氧化處理之後，位於第二區域314的第一鰭狀結構220具有與第一區域312不同的結構。為了清楚而更好的說明起見，位於第二區域314的第一鰭狀結構220(包含第二半導體氧化物特徵324)被稱為第二鰭狀結構320。因此，第二鰭狀結構320具有第三半導體材料層216作為其上部份、第二半導體材料層214作為其中央部份以及第一半導體材料層作為其下部份，其中第二半導體材料層214之外層包含第二半導體氧化物特徵324。
於本實施方式中，熱氧化處理經特殊控制，使第二半導體材料層214的氧化速度相較於第一半導體材料層212與第三半導體材料層216快上許多。換句話說，相較於第二半導體氧化物特徵324，第一半導體氧化物特徵322與第三半導體氧化物特徵326是非常薄的。舉例而言，鰭式場效電晶體裝置200的熱氧化處理是在水反應氣體中進行，其溫度範圍為大約攝氏400度至大約攝氏600度，壓力為大約1至大約20標準大氣壓(atm)下。在熱氧化處理後，進行清理處理，以移除第一半導體氧化物特徵322與第三半導體氧化物特徵326。此清理處理可以以稀釋的氫氟酸(diluted hydrofluoric；DHF)進行。
於本實施例中，第二半導體氧化物特徵324於垂直方向上延伸，其水平截面的尺寸隨著其在第二半導體材料 層214從上表面到下表面的位置而變化。進一步來說，第二半導體氧化物特徵324之水平截面的尺寸最大值為第二寬度w2，當愈接近於第二半導體氧化物特徵324之上表面與下表面時，其水平截面的尺寸會降低而愈接近於零，這使得第二半導體氧化物特徵324的剖面形狀為橄欖形。藉由控制熱氧化處理、選擇第二半導體材料層214的成分與厚度、控制氧化的溫度，將會達到第二半導體氧化物特徵324之第二寬度w2，其中，第二寬度w2會給予第一鰭狀結構220內之第三半導體材料層216適當的應力，進而定義出閘極區域下的閘極通道，這部份會在之後詳述。
於一實施方式中，第二半導體材料層214包含矽鍺(SiGex1)，且第一半導體材料層212與第三半導體材料層216皆包含矽(Si)。下標x1是第一鍺成份，以原子百分比表示，其數值可以調整以符合預定的體積膨脹目標。於一實施方式中，x1的值選定為大約20%至大約80%。經由熱氧化處理，矽鍺層214的外層被氧化，藉以形成矽鍺氧化物(SiGeO)特徵324。矽鍺氧化物特徵324之第二寬度w2的範圍為大約3奈米至10奈米。矽鍺層214的中心部份改變為第二鍺成份x2，其數值遠大於x1。矽鍺(SiGex2)的中心部份的尺寸和形狀隨著處理條件而變化，例如熱氧化的溫度和時間。且，中心部份的第二鍺成份x2高於其他部份，例如上部份、下部份、左側部份和右側部份。
同時參照第1圖與第6A~6B圖，方法100進行到步驟110，步驟110於N型鰭式場效電晶體200A與P型鰭 式場效電晶體200B內形成襯墊405，襯墊405共形地包覆第一鰭狀結構220與第二鰭狀結構320。首先，藉由蝕刻處理移除圖案化氧化硬式遮罩310，例如選擇性濕蝕刻。於本實施方式中，襯墊405包含氮化矽、氮氧化矽、氧化鋁或其他合適的材料。襯墊405具有第一厚度t1(可參照第13C圖)，其範圍為大約20埃至大約60埃。於本實施方式中，襯墊405以原子沉積法(Atomic layer deposition；ALD)沉積製成，以達到適量的薄膜覆蓋，包覆第一鰭狀結構220。或者，襯墊405可以藉由化學氣相沉積法(Chemical vapor deposition；CVD)、物理氣相沉積法(Physical vapor deposition；PVD)或其他適合的方法製成。於一實施方式中，襯墊405是以兩層層體製成，即第一層體402與設置於第一層體402上的第二層體404，圖中未繪示。第一層體402可包含矽和氮氧化矽，第二層體404可包含氮化矽和氧化鋁。第一層體402具有範圍大約10埃到大約30埃的第二厚度t2(可參照第13D圖)，第二層體404具有範圍大約20埃到大約60埃的第三厚度t3(可參照第13D圖)。於本實施方式中，襯墊405被設計作為緩衝層，用以避免第二半導體材料層214於下游或後續的處理中進一步氧化，同時襯墊405亦被作為阻止第二半導體材料層214向外擴散的屏障，之後會有詳細的介紹。
同時參照第1圖與第7A~7B圖，方法100進行到步驟112，步驟112於基板210上設置介電層410，其包含填滿N型鰭式場效電晶體200A與P型鰭式場效電晶體 200B內的凹槽230。此介電層410可包含氧化矽、氮化矽、氮氧化矽、旋塗式玻璃(spin-on-glass)、旋塗聚合物(spin-on-polymer)、其他合適的材料或以上材料之組合。介電層410可藉由化學氣相沉積法(Chemical vapor deposition；CVD)、物理氣相沉積法(Physical vapor deposition；PVD)、原子沉積法、熱氧化法、旋塗法、其他適合的方法或以上方法之組合而形成。如同前面提過的，設計使襯墊405覆蓋於第一鰭狀結構220與第二鰭狀結構320上，襯墊405可作為緩衝層，用以抵抗介電層410之形成過程中，例如介電層410之熱固化處理，所衍伸的影響。
同時參照第1圖與第7A~7B圖，方法100進行到步驟114，步驟114於基板210上形成圖案化硬式遮罩415，此圖案化硬式遮罩415覆蓋N型鰭式場效電晶體200A，而不覆蓋P型鰭式場效電晶體200B。此圖案化硬式遮罩415可包含氮化矽、氮氧化矽、碳化矽或其他合適的材料。圖案化硬式遮罩415的形成方法，與步驟106之圖案化氧化硬式遮罩310的形成方法相似。
同時參照第1圖與第8A圖，方法100進行到步驟116，步驟116凹陷P型鰭式場效電晶體200B內之第一鰭狀結構220內之襯墊405與第三半導體材料層216，此時，N型鰭式場效電晶體200A受到圖案化硬式遮罩415的保護。藉由適合的蝕刻方法，使襯墊405與第三半導體材料層216凹陷，例如使用選擇性濕蝕刻、選擇性乾蝕刻或上 述之組合。或者，透過形成於P型鰭式場效電晶體200B上的圖案化光阻層，亦可以使襯墊405與第三半導體材料層216凹陷。於本實施方式中，控制此凹陷之處理使餘留的襯墊405之上表面低於餘留的第三半導體材料層216，但仍高於第二半導體材料層214第一距離d1。如同前面提過的，設計第一距離d1足以阻礙第二半導體材料層214之向上的向外擴散，使其無法沿著介電層410與第三半導體材料層216的介面412而進入第一鰭狀結構之上部份，之後將會有閘極通道形成於此。舉例而言，第一距離d1足以阻礙矽鍺層214內的鍺，使其無法沿著介電層410與矽層216的介面412，進行向上的向外擴散。於一實施方式中，第一距離d1的範圍為大約2奈米至大約10奈米。
於另一實施方式中，如同第8B圖所示，其中襯墊可由第一層體402與第二層體404形成，第一層體402被凹陷，以使餘留的第一層體402之上表面高於第二半導體材料層214第二距離d2，第二層體404被凹陷，以使餘留的第二層體404之上表面高於第二半導體材料層214第一距離d1。第二距離d2大於第一距離d1。於一實施方式中，第二距離d2的範圍為大約5奈米至大約20奈米。此雙層的襯墊可以增強阻礙第二半導體材料層214沿著介電層410與第三半導體材料層216的介面412而向外擴散的能力。
同時參照第1圖、第7A圖與第9圖，方法100進行到步驟118，步驟118在，在凹陷之第三半導體材料層216上設置第四半導體材料層430，以在P型鰭式場效電晶 體200B內形成第三鰭狀結構440，此時，N型鰭式場效電晶體200A受到圖案化硬式遮罩415的保護。第四半導體材料層430可藉由磊晶成長方式形成。磊晶製程包含化學氣相沉積法(Chemical vapor deposition；CVD)、分子束磊晶法和/或其他適合方法。第四半導體材料層430可包含鍺(Ge)、矽(Si)、砷化鎵(GaAs)、砷化鋁鎵(AlGaAs)、矽鍺(SiGe)、磷砷化鎵(GaAsP)或其他適合的材料。於本實施方式中，第四半導體材料層430為矽鍺。因此，第三鰭狀結構440具有第四半導體材料層430作為其上部份、第三半導體材料層216作為其中上部份、第二半導體材料層214作為其中下部份以及第一半導體材料層212作為其下部份。
之後，可進行化學機械研磨(Chemical mechanical polishing；CMP)處理，用以移除多餘的第四半導體材料層430，以及平坦化P型鰭式場效電晶體200B之上表面。藉由適合的蝕刻處理，例如濕蝕刻、乾蝕刻或上述之組合，移除N型鰭式場效電晶體200A之硬式遮罩415。
同時參照第1圖與第10A~10E圖，方法100進行到步驟120，步驟120凹陷N型鰭式場效電晶體200A內之襯墊405並凹陷N型鰭式場效電晶體200A與P型鰭式場效電晶體200B內的介電層。首先，藉由適當的蝕刻方法，例如選擇性濕蝕刻或選擇性乾蝕刻，移除N型鰭式場效電晶體200A內的圖案化硬式遮罩415。接著藉由適當的蝕刻方法，例如選擇性濕蝕刻、選擇性乾蝕刻或上述之組合，凹陷襯墊405。於本實施方式中，此凹陷之處理被控制使餘 留的襯墊405之上表面低於餘留的第三半導體材料層216，但高於第二半導體材料層214第一距離d1。於另一實施方式中，其中襯墊可由第一層體402與第二層體404形成，第一層體402被凹陷，以使餘留的第一層體402之上表面高於第二半導體材料層214第二距離d2。
接著，凹陷N型鰭式場效電晶體200A與P型鰭式場效電晶體200B內的介電層410以露出第一鰭狀結構220(位於N型鰭式場效電晶體200A)之上部份與第三鰭狀結構440(位於P型鰭式場效電晶體200B)之上部份。於本實施方式中，此凹陷之處理被控制使凹陷後的介電層410之上表面高於襯墊405之上表面第三距離d3。於本實施方式中，第三距離d3被設計足以讓襯墊405遠離第一鰭狀結構、第二鰭狀結構、第三鰭狀結構之上部份，其中，閘極區域將會於稍後形成於此上部份，用以避免襯墊405於閘極區域的不利影響，例如襯墊405的固定消耗。於一實施方式中，第三距離d3的範圍為大約3奈米至大約10奈米。或者，襯墊可由第一層體402與第二層體404共同形成，其中凹陷後的介電層410之上表面高於第二層體404之上表面第三距離d3。第一層體402的上表面水平齊於或低於凹陷後的介電層410之上表面。
於一實施方式中，於凹槽230內的凹陷之介電層410形成淺溝槽隔離區(shallow trench isolation；STI)特徵。
同時參照第10A圖與第10B圖，於某些實施方式 中，第一鰭狀結構220、第二鰭狀結構320和第三鰭狀結構440包含源極/汲極(drain/source；S/D)區域450與閘極區域460。進一步而言，源極/汲極區域450之一為源極，而源極/汲極區域450之另一為汲極。源極/汲極區域450由閘極區域460分隔開來。為清楚說明起見，位於N型鰭式場效電晶體200A內的源極/汲極區域450與閘極區域460以第一源極/汲極區450A與第一閘極區460A稱之，位於P型鰭式場效電晶體200B內的源極/汲極區域450與閘極區域460以第二源極/汲極區450B與第二閘極區460B稱之。
於一實施方式中，第一源極/汲極區450A位於第一鰭狀結構220之一部份，並由位於第二鰭狀結構320之一部份之第一閘極區460A分隔開來。於P型鰭式場效電晶體200B內，第三鰭狀結構440包含第二源極/汲極區450B，此第二源極/汲極區450B由第二閘極區460B分隔開來。
同時參照第1圖與第11A~11B圖，方法100進行到步驟122，步驟122於第一閘極區460A與第二閘極區460B上形成閘極堆疊510，並於閘極堆疊510之側壁上形成多個側壁間隔物520。於一採用後閘極(gate-last)製程的實施方式中，閘極堆疊510為虛設閘極，且將於後續的階段中被最終的閘極堆疊所取代。尤其，在高熱溫處理後，虛設的閘極堆疊510將稍後被高介電層(high-k dielectric layer)和金屬閘極所取代，例如在此高熱溫處理可以是於源極/汲極的形成過程中，激化源極/汲極的熱退火處理。虛設閘極堆疊510是形成於基板210上，且部份位於第一閘極 區460A內的第二鰭狀結構320與第二閘極區460B內的第三鰭狀結構440。於一實施方式中，虛設閘極堆疊510包含介電層512、電極層514以及閘極硬式遮罩(gate hard mask；GHM)516。虛設閘極堆疊510是藉由適合的程序完成，其中包含沉積與圖案化。圖案化的處理包含微影與蝕刻。於各種實施例中，沉積的處理包含化學氣相沉積法(Chemical vapor deposition；CVD)、物理氣相沉積法(Physical vapor deposition；PVD)、原子層沉積法(Atomic layer deposition；ALD)、熱氧化法、其他合適的方法或上述之組合。微影的處理包含光阻層的被覆(例如旋塗被覆)、軟烘烤、光罩對準、曝光、曝光後烘烤、顯影光阻層、漂洗、乾糙化(例如硬烤)、其他適合的處理以及/或上述之組合。蝕刻處理包含乾蝕刻、濕蝕刻、以及/或其他蝕刻方法(例如反應性離子蝕刻)。
介電層512包含氧化矽。替代地或附加地，介電層512可包含氮化矽、高介電材料或其他合適的材料。電極層514可包含多晶矽(polysilicon)。閘極硬式遮罩516包含合適的介電材料，例如氮化矽、氮氧化矽或碳化矽。側壁間隔物520可包含介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽或上述之組合。側壁間隔物520可包含多個層體。側壁間隔物520的傳統的形成方法包含於閘極堆疊510上形成一介電材料，接著非等向性地蝕刻介電材料。蝕刻介電材料的處理包含多步驟的蝕刻，以達到蝕刻上的選擇性、彈性以及預期過蝕刻的控制。
同時參照第1圖與第11A~11B圖，方法100進行到步驟124，步驟124於第一源極/汲極區450A內形成第一源極/汲極特徵610A，並於第二源極/汲極區450B內形成第二源極/汲極特徵610B。於一實施方式中，藉由凹陷第一源極/汲極區450A內之第一鰭狀結構220之上部份之一部份，而形成第一源極/汲極特徵610A，並藉由凹陷第二源極/汲極區450B內之第三鰭狀結構440之上部份之一部份，而形成第二源極/汲極特徵610B。於一實施方式中，第一鰭狀結構220與第三鰭狀結構440是於同一蝕刻步驟中凹陷。於另一實施方式中，第一鰭狀結構220與第三鰭狀結構440是於不同的蝕刻步驟中凹陷。於本實施方式中，為了達到流程整合的靈活性，凹陷的處理應控制使第三半導體材料層216之一部份保留於第一鰭狀結構220內，且第四半導體材料層430之一部份保留於第三鰭狀結構440內。
接著，第一源極/汲極特徵610A與第二源極/汲極特徵610B以磊晶成長方式形成於第一源極/汲極區450A內之凹陷的第一鰭狀結構220與第二源極/汲極區450B內之凹陷的第三鰭狀結構440。第一源極/汲極特徵610A與第二源極/汲極特徵610B包含鍺、矽、砷化鎵、鋁砷化鎵、矽鍺、磷砷化鎵或其他合適的材料。第一源極/汲極特徵610A與第二源極/汲極特徵610B可以經由一或多個磊晶步驟形成。第一源極/汲極特徵610A與第二源極/汲極特徵610B亦可以被摻雜，例如於磊晶製程中被原位摻雜(in-situ doped)。或者，第一源極/汲極特徵610A與第二源極/汲極 特徵610B可以不被原位摻雜，而是以植入製程(例如接面植入製程)方式摻雜第一源極/汲極特徵610A與第二源極/汲極特徵610B。
於一實施方式中，第一源極/汲極特徵610A是以由磊晶成長的矽層所形成，其中磊晶成長的矽層摻雜碳以形成Si：Cz，作為第一源極/汲極特徵610A的下部份，磊晶成長的矽層摻雜磷以形成Si：P，作為第一源極/汲極特徵610A的上部份，於此，z是碳成分的原子百分比。於一實施方式中，z的範圍為大約0.5%至大約1.5%。Si：Cz具有大約5奈米至大約15奈米之範圍的厚度，Si：P具有大約20奈米至大約35奈米之範圍的厚度。
於另一實施方式中，第二源極/汲極特徵610B是以由磊晶成長的矽鍺層所形成，其中磊晶成長的矽鍺層摻雜硼以形成SiGeαB，其中α是鍺成份的原子百分比。於一實施例中，α的範圍為大約60%至大約100%。
同時參照第1圖與第12A~12B圖，方法100進行到步驟126，步驟126於虛設閘極堆疊510的空隙之間、基板210上形成層間介電層720。層間介電層720包含氧化矽、氮氧化矽、具有低介電常數的介電材料或其他適合的介電材料。層間介電層720可包含單層或多層。層間介電層720可藉由適當的技術形成，例如化學氣相沉積法(Chemical vapor deposition；CVD)、原子層沉積法(Atomic layer deposition；ALD)和旋塗式玻璃(spin-on-glass；SOG)。其後，可以進行化學機械研磨(Chemical mechanical polishing；CMP)處理以移除多餘的層間介電層720並使鰭式場效電晶體裝置200之上表面平坦化。
同時參照第1圖與第12A~12B圖，方法100進行到步驟128，步驟128移除第一閘極區460A內的虛設閘極堆疊510以形成一或多個第一閘極凹槽810A，並移除第二閘極區460B內的虛設閘極堆疊510以形成一或多個第二閘極凹槽810B。第二鰭狀結構320的上部份露出於第一閘極凹槽810A，第三鰭狀結構440的上部份露出於第二閘極凹槽810B。虛設閘極堆疊510是藉由蝕刻處理(例如選擇性濕蝕刻或選擇性乾蝕刻)而移除，其中蝕刻處理被設計對於第一閘極凹槽810A內的第三半導體材料層216以及第二閘極凹槽810B內的第四半導體材料層430，具有合適的蝕刻選擇性。蝕刻處理可包含一或多個蝕刻步驟，蝕刻步驟具有各自的蝕刻劑。閘極硬式遮罩層516和間隔物520亦皆被移除。或者，可藉由一系列的處理程序，包含微影圖案化處理與蝕刻處理，移除虛設閘極堆疊510。
同時參照第1圖與第13A~13F圖，方法100進行到步驟130，步驟130於基板210上形成第一高介電/金屬閘極(high-k/metal gate；HK/MG)堆疊910A與第二高介電/金屬閘極(high-k/metal gate；HK/MG)堆疊910B，分別包覆第一閘極凹槽810A內的第二鰭狀結構320之一部份與第二閘極凹槽810B內的第三鰭狀結構440之一部份。第一高介電/金屬閘極堆疊910A與第二高介電/金屬閘極堆疊910B包含閘極介電層與位於閘極介電層上的閘極電極。於 一實施方式中，閘極介電層包含具有高介電常數的介電材料層(即高介電層之介電常數大於本實施方式中的熱氧化矽之介電常數)，閘極電極包含金屬、金屬合金或金屬矽化物。第一高介電/金屬閘極堆疊910A與第二高介電/金屬閘極堆疊910B的形成過程包含利用多個沉積方法形成各種閘極材料，以及化學機械研磨(Chemical mechanical polishing；CMP)方法以移除多餘的閘極材料，並使N型鰭式場效電晶體200A與P型鰭式場效電晶體200B的上表面平坦化。
於一實施方式中，閘極介電層包含介面層(interfacial layer；IL)，介面層可藉由適合的方法設置，例如原子層沉積(Atomic layer deposition；ALD)法、化學氣相沉積(Chemical vapor deposition；CVD)法、熱氧化法或臭氧氧化法。介面層包含氧化物、矽酸鉿和氮氧化物。具有高介電常數之介電層可藉由合適的方法設置於介面層之上，例如原子層沉積(Atomic layer deposition；ALD)法、化學氣相沉積(Chemical vapor deposition；CVD)法、金屬有機化學氣相沉積(Metal organic chemical vapor deposition；MOCVD)法、物理氣相沉積(Physical vapor deposition；PVD)法、其他適合的技術或上述之組合。具有高介電常數之介電層可包含氧化鑭(LaO)、氧化鋁(AlO)、氧化鋯(ZrO)、氧化鈦(TiO)、五氧化二鉭(Ta2O5)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3；STO)、鈦酸鋇(BaTiO3；BTO)、氧化鋇鋯(BaZrO)、氧化鉿鋯(HfZrO)、氧化鉿鑭 (HfLaO)、矽酸鉿(HfSiO)、矽酸鑭(LaSiO)、矽酸鋁(AlSiO)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、鈦酸鍶鋇((Ba,Sr)TiO3；BST)、氧化鋁(Al2O3)、氮化矽(Si3N4)、氮氧化矽(SiON)或其他合適的材料。閘極介電層包覆位於第一閘極區460A之第二鰭狀結構320之上部份與位於第二閘極區460B之第三鰭狀結構440之上部份。
金屬閘極電極可包含單層或多層結構，例如由具有提高裝置表現的功函數之金屬層(功函數金屬層)、襯墊層、潤濕層、黏著層與導電層所產生的各種組合，其中導電層可由金屬、金屬合金或金屬矽化物所組成。金屬閘極電極可包含鈦(Ti)、銀(Ag)、鋁(Al)、氮化鋁鈦(TiAlN)、碳化鉭(TaC)、氮碳化鉭(TaCN)、氮矽化鉭(TaSiN)、錳(Mn)、鋯(Zr)、氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、氮化鎢(WN)、銅(Cu)、鎢(W)、其他適合材料或上述之組合。金屬閘極電極可藉由原子沉積法(Atomic layer deposition；ALD)、物理氣相沉積法(Physical vapor deposition；PVD)、化學氣相沉積法(Chemical vapor deposition；CVD)或其他合適方法形成。金屬閘極電極可針對N型鰭式場效電晶體200A與P型鰭式場效電晶體200B而分別以不同的金屬層形成。可採用化學機械研磨(Chemical mechanical polishing；CMP)方法移除多餘的金屬閘極電極。
再回到第13C圖與第13D圖，於N型鰭式場效電晶體200A中，第一高介電/金屬閘極910A包覆第二鰭狀結構320之上部份，其中第二鰭狀結構320包含第三半導體 材料層216作為其上部份、具有半導體氧化物特徵324作為其外層之第二半導體材料層214作為其中央部份、以及第一半導體材料層212作為其下部份。襯墊405沿著第二鰭狀結構的側壁形成，而使其沿著第三半導體材料層216的下部份；沿著半導體氧化物特徵324以及沿著第一半導體材料層212。襯墊405之上表面高於第二半導體材料層214之上表面第一距離d1。凹陷之介電層410形成於每個第二鰭狀結構320之間。凹陷之介電層410的上表面高於襯墊405之上表面第三距離d3。
再回到第13E圖與第13F圖，於P型鰭式場效電晶體200B中，第二高介電/金屬閘極910B包覆第三鰭狀結構440之上部份，其中第三鰭狀結構440包含第四半導體材料層430作為其上部份、第三半導體材料層216作為其中上部份、第二半導體材料層214作為其中下部份、以及第一半導體材料層212作為其下部份。襯墊405沿著第三鰭狀結構440的側壁形成，以使其沿著第三半導體材料層216的下部份包覆；沿著第二半導體材料層214以及沿著第一半導體材料層212包覆。襯墊405之上表面高於第二半導體材料層214之上表面第一距離d1。凹陷之介電層410形成於每個第三鰭狀結構440之間，且凹陷之介電層410的上表面高於襯墊405之上表面第三距離d3。
當襯墊包含第一層體402與第二層體404時，第一層體402的上表面高於第二半導體材料層214第二距離d2，其中第二距離d2大於第一距離d1，但第一層體402的 上表面等於或低於凹陷之介電層410的上表面。
鰭式場效電晶體裝置200可以接著進行互補式金屬氧化物半導體或金屬氧化物半導體技術處理，以形成該技術領域中已知的各種特徵與區域。舉例而言，隨後的處理可於基板210上形成各式各樣的接點/導通孔/線和多層內連線特徵(例如金屬層和層間介電質)，配置與各式各樣的特徵互相連接以形成功能性電路，此功能性電路其中包含有一或多個鰭式場效電晶體。進一步而言，多層內連線包含垂直內連線，例如導通孔或接點，以及多層內連線包含水平內連線，例如金屬線。這些各式各樣的多層內連線特徵可以使用各種導電材料，包含銅、鎢以及/或矽化物。於一實施例中，可以採用金屬鑲嵌法和/或雙重金屬鑲嵌法以形成銅相關的多層內連線特徵。
在方法100之前、之中、之後，可以增加額外的操作，且針對該方法之其他實施方式，以上的部份操作可以被取代或取消。
基於以上所述，本揭露提供鰭式場效電晶體之多個結構。其結構運用襯墊包覆鰭狀結構，以延緩閘極區域內的向外擴散，並提供閘極區域的鰭狀結構緩衝層。鰭式場效電晶體之結構展示裝置性能上的進步。
本揭露提供鰭式場效電晶體裝置之一實施方式。鰭式場效電晶體裝置包含基板與第一鰭狀結構，基板具有第一閘極區，第一鰭狀結構位於基板上之第一閘極區內。第一鰭狀結構包含上半導體材料件、下半導體材料件以及襯 墊，下半導體材料件受到氧化物特徵圍繞，襯墊包覆下半導體材料件之氧化物特徵並向上延伸至包覆上半導體材料件之下部份。鰭式場效電晶體裝置亦包含介電層，介電層側向地鄰近上半導體材料件之中央部份。如此一來，上半導體材料件包含上部份，上部份不側向地鄰近介電層，亦不受襯墊包覆。
本揭露提供鰭式場效電晶體裝置之另一實施方式。鰭式場效電晶體裝置包含第二鰭狀結構，位於基板上且位於第二閘極區內。第二鰭狀結構包含上半導體材料件、中半導體材料件以及下半導體材料件，襯墊包覆下半導體材料件，並向上延伸至包覆中半導體材料件之下部份。鰭式場效電晶體裝置亦包含介電層與第二高介電/金屬閘極堆疊，介電層側向地鄰近中半導體材料件之一中部份，其中中半導體材料件包含上部份，上部份不側向地鄰近介電層，亦不受襯墊包覆，第二高介電/金屬閘極堆疊位於基板上，包覆位於第二閘極區的上半導體材料件與中半導體材料件之上部份。
本揭露提供鰭式場效電晶體裝置之一種製作方法。製作方法包含提供具有N型鰭式場效電晶體區域與P型鰭式場效電晶體區域之基板、形成多個第一鰭狀結構於N型鰭式場效電晶體區域與P型鰭式場效電晶體區域。第一鰭狀結構包含第一磊晶半導體材料層，作為其上部份；第二磊晶半導體材料層，作為其中央部份，第二磊晶半導體材料層之外層為半導體氧化物特徵；以及第三磊晶半導體 材料層，作為其下部份。製作方法亦包含形成圖案化氧化物硬式遮罩(OHM)於N型鰭式場效電晶體區域與P型鰭式場效電晶體區域，以露出位於N型鰭式場效電晶體區域之第一閘極區之第一鰭狀結構。製作方法亦包含退火以形成半導體氧化物特徵於位於第一閘極區且位於第一鰭狀結構之第二半導體材料層之外層。製作方法亦包含形成襯墊、設置介電層於第一鰭狀結構之間、在將硬式遮罩層覆蓋於N型鰭式場效電晶體區域之後使襯墊凹陷、並形成第二鰭狀結構於P型鰭式場效電晶體區域，其中襯墊包覆位於N型鰭式場效電晶體區域與P型鰭式場效電晶體區域內之第一鰭狀結構。製作方法亦包含在移除硬式遮罩層之後，使位於N型鰭式場效電晶體區域之襯墊凹陷，以及使位於N型鰭式場效電晶體區域與P型鰭式場效電晶體區域兩者之介電層凹陷。
以上大致敘述多個實施方式的特徵，如此一來，任何熟習此技藝者應可較佳地了解本揭露之態樣。任何熟習此技藝者可了解到，他們可將本揭露作為其他設計或改善處理程序的基礎，以實現與本揭露提到的多個實施方式相同目的以及/或達到與本揭露提到的多個實施方式相同的優點。任何熟習此技藝者也可了解到，這些相同的結構並未脫離本揭露之精神和範圍，且在不脫離本揭露之精神和範圍內，且他們可作各種之變化、更動與潤飾。
200A‧‧‧N型場效電晶體
212‧‧‧第一半導體材料層
214‧‧‧第二半導體材料層、矽鍺層
216‧‧‧第三半導體材料層、矽層
324‧‧‧矽鍺氧化物特徵、第二半導體氧化物特徵
405‧‧‧襯墊
410‧‧‧介電層
412‧‧‧介面
320‧‧‧第二鰭狀結構
460A‧‧‧第一閘極區
910A‧‧‧第一高介電/金屬閘極堆疊
t1‧‧‧第一厚度
d1‧‧‧第一距離
d3‧‧‧第三距離

Claims (10)

  1. 一種鰭式場效電晶體裝置，包含：一基板，具有一第一閘極區；一第一鰭狀結構，位於該基板上之該第一閘極區，該第一鰭狀結構包含：一上半導體材料件；一下半導體材料件，其中一氧化物特徵圍繞該下半導體材料件；以及一襯墊，包覆該下半導體材料件之該氧化物特徵，並向上延伸至包覆該上半導體材料件之一下部份；以及一介電層，側向地鄰近該上半導體材料件之一中央部份，其中該上半導體材料件包含一上部份，該上部份不側向地鄰近該介電層，亦不受該襯墊包覆。
  2. 如請求項1所述之裝置，更包含：一第一高介電/金屬閘極堆疊，包覆該上半導體材料件，包含包覆該上半導體材料件之該上部份。
  3. 如請求項1所述之裝置，其中該襯墊包含一第一層體與一第二層體，該第一層體包覆該下半導體材料件之該氧化物特徵，並向上延伸至包覆該上半導體材料件之該下部份，該第二層體包覆該第一層體。
  4. 如請求項1所述之裝置，更包含：一第二鰭狀結構，位於該基板上且位於一第二閘極區，該第二鰭狀結構包含：一上半導體材料件；一中半導體材料件；以及一下半導體材料件；該襯墊，包覆該下半導體材料件，並向上延伸至包覆該中半導體材料件之一下部份；該介電層，側向地鄰近該中半導體材料件之一中部份，其中該中半導體材料件包含一上部份，該上部份不側向地鄰近該介電層，亦不受該襯墊包覆；以及一第二高介電/金屬閘極堆疊，位於該基板上，包覆位於該第二閘極區的該上半導體材料件與該中半導體材料件之該上部份。
  5. 如請求項1所述之裝置，更包含：複數個第一源極與汲極區，由該第一閘極區分隔於該基板上；該第一鰭狀結構，包含一凹陷上半導體材料件於該些第一源極與汲極區；以及複數個第一源極/汲極特徵，位於該凹陷上半導體材料件之頂部。
  6. 一種鰭式場效電晶體裝置，包含： 一基板，具有一N型鰭式場效電晶體區域與一P型鰭式場效電晶體區域；一第一鰭狀結構，位於該基板上之該N型鰭式場效電晶體區域，該第一鰭狀結構包含：一磊晶矽(Si)層，作為該第一鰭狀結構之上部份；以及一磊晶矽鍺(SiGe)層，作為該第一鰭狀結構之下部份，該磊晶矽鍺層之外層具有一矽鍺氧化物(SiGeO)特徵；一襯墊，包覆該矽鍺氧化物(SiGeO)特徵，並向上延伸至包覆該磊晶矽(Si)層之一下部份；以及一介電層，側向地鄰近該磊晶矽(Si)層之一中央部份，其中上部份之該磊晶矽(Si)層包含一上部份，該上部份不側向地鄰近該介電層，亦不受該襯墊包覆，一第二鰭狀結構，位於該基板上之該P型鰭式場效電晶體區域，該第二鰭狀結構包含：一磊晶矽鍺(SiGe)層，作為該第二鰭狀結構之上部份；一磊晶矽(Si)層，作為該第二鰭狀結構之中部份；以及另一磊晶矽鍺(SiGe)層，作為該第二鰭狀結構之下部份；該襯墊，包覆較低之磊晶矽鍺(SiGe)層與中部份之該磊晶矽(Si)層，並向上延伸至包覆上部份之該磊晶 矽鍺(SiGe)層的一下部份；以及該介電層，側向地鄰近上部份之該磊晶矽鍺(SiGe)層之一中央部份，其中上部份之該磊晶矽鍺(SiGe)層包含一上部份，該上部份不側向地鄰近該介電層，亦不受該襯墊包覆。
  7. 如請求項6所述之裝置，更包含：一第一閘極區，位於該第一鰭狀結構之一部份；一第一高介電/金屬閘極堆疊，位於該基板上，包覆該第一鰭狀結構之上部份之該磊晶矽(Si)層之一部份；複數個第一源極與汲極區，由該第一閘極區分隔於該基板上；複數個第一源極/汲極特徵，位於該些第一源極/汲極區之凹陷的該磊晶矽(Si)層的頂部；一第二閘極區，位於該第二鰭狀結構之一部份；一第二高介電/金屬閘極堆疊，位於該基板上，包覆該第二鰭狀結構之上部份之該磊晶矽鍺(SiGe)層之一部份；複數個第二源極與汲極區，由該第二閘極區分隔於該基板上；以及複數個第二源極/汲極特徵，位於凹陷的該上部份磊晶矽鍺(SiGe)層的頂部。
  8. 一種用於製作鰭式場效電晶體裝置的方法，包含：提供具有一N型鰭式場效電晶體區域與一P型鰭式場效電晶體區域之一基板； 形成複數個第一鰭狀結構於該N型鰭式場效電晶體區域與該P型鰭式場效電晶體區域，每一該些第一鰭狀結構包含：一第一磊晶半導體材料層，作為其上部份；一第二磊晶半導體材料層，作為其中央部份；以及一第三磊晶半導體材料層，作為其下部份；形成一圖案化氧化物硬式遮罩於該N型鰭式場效電晶體區域與該P型鰭式場效電晶體區域，以露出位於該N型鰭式場效電晶體區域之一第一閘極區之該第一鰭狀結構；退火以形成一半導體氧化物特徵於該第一閘極區內之該第一鰭狀結構內之該第二半導體材料層之外層；形成一襯墊，該襯墊包覆位於該N型鰭式場效電晶體區域與該P型鰭式場效電晶體區域兩者之該些第一鰭狀結構；沉積一介電層於該些第一鰭狀結構之間；在將一硬式遮罩層覆蓋於該N型鰭式場效電晶體區域之後，使位於該P型鰭式場效電晶體區域之該襯墊凹陷；於將該硬式遮罩層覆蓋於該N型鰭式場效電晶體區域時，形成一第二鰭狀結構於該P型鰭式場效電晶體區域；在移除該硬式遮罩層之後，使位於該N型鰭式場效電晶體區域之該襯墊凹陷；以及使位於該N型鰭式場效電晶體區域與該P型鰭式場效電晶體區域兩者之該介電層凹陷。
  9. 如請求項8所述之方法，更包含：形成複數個虛設閘極於該第一閘極區與該第二鰭狀結構內之一第二閘極區；形成一第一源極/汲極特徵於該N型鰭式場效電晶體區域內之該第一鰭狀結構之一第一源極/汲極區域；形成一第二源極/汲極特徵於該P型鰭式場效電晶體區域內之該第二鰭狀結構之一第二源極/汲極區域；以第一高介電/金屬閘極取代位於該N型鰭式場效電晶體區域內之該些虛設閘極，該第一高介電/金屬閘極包覆位於該第一閘極區之該第一鰭狀結構之一上部份；以及以第二高介電/金屬閘極取代位於該P型鰭式場效電晶體區域內之該些虛設閘極，該第二高介電/金屬閘極包覆位於該第二閘極區之該第二鰭狀結構之一上部份。
  10. 如請求項8所述之方法，更包含：控制該襯墊之凹陷，使該襯墊之上表面高於該第二半導體材料層一第一高度；以及控制該介電層之凹陷，使該介電層之上表面高於該第二半導體材料層一第二高度，其中該第二高度大於該第一高度。
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US10325816B2 (en) 2019-06-18
KR20150126777A (ko) 2015-11-13
CN105047710A (zh) 2015-11-11
KR101799636B1 (ko) 2017-11-20
US20150311336A1 (en) 2015-10-29
TW201541645A (zh) 2015-11-01
US9698058B2 (en) 2017-07-04
US20160049338A1 (en) 2016-02-18
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US9178067B1 (en) 2015-11-03

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