CN105047710B - 用于finfet器件的结构和方法 - Google Patents

用于finfet器件的结构和方法 Download PDF

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CN105047710B
CN105047710B CN201410658546.6A CN201410658546A CN105047710B CN 105047710 B CN105047710 B CN 105047710B CN 201410658546 A CN201410658546 A CN 201410658546A CN 105047710 B CN105047710 B CN 105047710B
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fin structure
semiconductor material
layer
lining
wrapped
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CN105047710A (zh
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江国诚
冯家馨
张智胜
吴志强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了鳍式场效应晶体管(FinFET)器件的实施例。该器件包括具有第一栅极区域的衬底、位于第一栅极区域中的衬底上方的第一鳍结构。第一鳍结构包括上部半导体材料构件、被氧化物部件环绕的下部半导体材料构件以及包裹在下部半导体材料构件的氧化物部件周围并且向上延伸以包裹在上部半导体材料构件的下部周围的衬层。该器件还包括与上部半导体材料构件的下部横向邻近的介电层。因此，上部半导体材料构件包括既不与介电层横向邻近也不被衬层包裹的中部。本发明还提供了形成鳍式场效应晶体管(FinFET)器件的方法。

Description

用于FINFET器件的结构和方法
交叉引用
本申请要求2014年4月25日提交的美国临时专利申请第61/984,475号的优先权，其全部内容结合于此作为参考。
相关申请
本申请与2013年1月14日提交的标题为“Semiconductor Device andFabricating the Same”的美国专利申请第13/740,373号、2013年5月24日提交的标题为“FinFET Device and Method of Fabricating the Same”的美国专利申请第13/902,322号、2013年7月3日提交的标题为“Fin Structure of Semiconductor Device”的美国专利申请第13/934,992号以及2014年1月15日提交的标题为“Semiconductor Device andFormation Thereof”的美国专利申请第14/155,793号相关，其全部内容结合于此作为参考。
技术领域
本发明总体涉及半导体领域，更具体地，涉及FinFET器件。
背景技术
半导体集成电路(IC)工业已经经历了指数型增长。IC材料和设计中的技术进步产生了多代IC，其中每一代都具有比前一代更小且更复杂的电路。在IC的演化过程中，功能密度(即，每芯片面积的互连器件的数量)普遍增加，而几何尺寸(即，使用制造工艺可制造的最小部件(或线))减小。这种按比例缩小的工艺通常通过提高生产效率和降低相关成本来提供益处。
这种按比例缩小还增加了处理和制造IC的复杂度，并且为了实现这些进步，需要IC处理和制造中的类似发展。例如，已经引入三维晶体管(诸如，鳍式场效应晶体管(FinFET))来代替平面晶体管。尽管现有的FinFET器件及制造FinFET器件的方法通常足以满足它们的预期目的，但是它们并不是在所有方面都完全令人满意。
发明内容
根据本发明的一个方面，提供了一种鳍式场效应晶体管(FinFET)器件，包括：衬底，具有第一栅极区域；第一鳍结构，位于第一栅极区域中的衬底上方，第一鳍结构包括：上部半导体材料构件；下部半导体材料构件，被氧化物部件环绕；和衬层，包裹在下部半导体材料构件的氧化物部件周围，并且向上延伸以包裹在上部半导体材料构件的下部周围；以及介电层，与上部半导体材料构件的下部横向邻近，其中，上部半导体材料构件包括既不与介电层横向邻近也不被衬层包裹的中部。
优选地，该器件还包括：第一高k/金属栅叠件，包裹在上部半导体材料构件上方，包括包裹在上部半导体材料构件的中部上方。
优选地，衬层包括选自由氮化硅、氮氧化硅和氧化铝组成的组的一种或多种材料。
优选地，介电层的顶面以一距离位于衬层的顶面之上，该距离在约3nm至约10nm的范围内；以及介电层的顶面以一距离位于下部半导体材料构件的顶面之上，该距离在约5nm至约20nm的范围内。
优选地，衬层通过原子层沉积(ALD)来沉积，衬层的厚度在约至约的范围内。
优选地，上部半导体材料构件包括外延硅(Si)；下部半导体材料构件包括外延硅锗(SiGe)；以及氧化物部件包括氧化硅锗(SiGeO)。
优选地，衬层包括：第一层，包裹在下部半导体材料构件的氧化物部件周围并且向上延伸以包裹在上部半导体材料构件的下部周围；以及第二层，包裹在第一层上方。
优选地，第一层包括选自由硅和氮氧化硅组成的组的一种或多种材料；第二层包括选自由氮化硅、氮氧化硅和氧化铝组成的组的一种或多种材料；第一层的厚度在约至约的范围内；第二层的厚度在约至约的范围内；第一层的顶面位于介电层的顶面下方或者与介电层的顶面处于同一水平面；以及第二层的顶面以一距离位于介电层的顶面下方，该距离在约3nm至约10nm的范围内。
优选地，该器件还包括：第二鳍结构，位于第二栅极区域中的衬底上方，第二鳍结构包括：上部半导体材料构件；中间半导体材料构件；和下部半导体材料构件；衬层，包裹在下部半导体材料构件周围，并且向上延伸以包裹中间半导体材料构件的下部周围；介电层，与中间半导体材料构件的中部横向邻近，其中，中间半导体材料构件包括既不与介电层横向邻近也不被衬层包裹的上部；以及第二高k/金属栅叠层，位于衬底上方，包裹在第二栅极区域中的上部半导体材料构件以及中间半导体材料构件的上部上方。
优选地，上部半导体材料构件包括外延硅锗(SiGe)；中间半导体材料构件包括外延硅(Si)；以及下部半导体材料构件包括外延SiGe。
优选地，该器件还包括：第一源极和漏极(S/D)区域，被衬底上方的第一栅极区域分隔开；第一鳍结构，在第一S/D区域中具有凹进的上部半导体材料构件；以及第一源极/漏极部件，位于凹进的上部半导体材料构件的顶部上。
优选地，该器件还包括：第一源极和漏极(S/D)区域，被衬底上方的第二栅极区域分隔开；第二鳍结构，在第二S/D区域中具有凹进的上部半导体材料构件；以及第二源极/漏极部件，位于凹进的上部半导体材料构件的顶部上。
根据本发明的另一方面，提供了一种鳍式场效应晶体管(FinFET)器件，包括：衬底，具有n型鳍式场效应晶体管(NFET)区域和p型鳍式场效应晶体管(PFET)区域；第一鳍结构，位于NFET区域中的衬底上方，第一鳍结构包括：外延硅(Si)层，作为第一鳍结构的上部；和外延硅锗(SiGe)，并且氧化硅锗(SiGeO)部件位于外延SiGe的外层处，以作为第一鳍结构的下部；衬层，包裹在SiGeO部件周围，并且向上延伸以包裹在Si层的下部周围；以及介电层，与Si层的下部横向邻近，其中，上部Si层包括既不与介电层横向邻近也不被衬层包裹的中部，第二鳍结构，位于PFET区域中的衬底上方，第二鳍结构包括：外延SiGe层，作为第二鳍结构的上部；外延Si，作为第二鳍结构的中部的；和另一外延SiGe层，作为第二鳍结构的底部；衬层，包裹在下部SiGe层周围，并且向上延伸以包裹在中部Si层的下部周围；以及介电层，与中部Si层的上部横向邻近，其中，上部SiGe层既不与介电层横向邻近也不被衬层包裹。
优选地，衬层包括选自由氮化硅、氮氧化硅和氧化铝所组成的组的一种或多种材料。
优选地，衬层通过原子层沉积(ALD)沉积，衬层的厚度在约至约的范围内。
优选地，介电层的顶面以一距离位于衬层的顶面之上，该距离在约3nm至约10nm的范围内；以及介电层的顶面以一距离位于下部SiGe层的顶面之上，该距离在约5nm至约20nm的范围内。
优选地，该器件还包括：第一栅极区域，位于第一鳍结构的一部分中；第一高k/金属栅叠层，位于衬底上方，包裹在第一鳍结构的上部Si层的一部分上方；第一源极和漏极(S/D)区域，被衬底上方的第一栅极区域分隔开；第一源极/漏极部件，位于第一S/D区域中的凹进的上部Si层的顶部上；第二栅极区域，位于第二鳍结构的一部分中；第二高k/金属栅叠层，位于衬底上方，包裹在第二鳍结构的上部SiGe层以及中部Si层的一部分上方；第二S/D区域，被衬底上方的第二栅极区域分隔开；以及第二源极/漏极部件，位于凹进的上部SiGe层的顶部上。
根据本发明的又一方面，提供了一种方法，包括：提供衬底，衬底具有n型鳍式场效应晶体管(NFET)区域和p型鳍式场效应晶体管(PFET)区域；在NFET区域和PFET区域中形成第一鳍结构，第一鳍结构包括：第一外延半导体材料层，作为第一鳍结构的上部；第二外延半导体材料层，半导体氧化物部件位于第二外延半导体材料层的外层处，以作为第一鳍结构的中部；和第三外延半导体材料层，作为第一鳍结构的下部；以及在NFET区域和PFET区域上方形成图案化氧化硬掩模(OHM)，以暴露NFET区域的第一栅极区域中的第一鳍结构；施加退火，以在第一栅极区域中的第一鳍结构中的第二外延半导体材料层的外层处形成半导体氧化物部件；形成分别包裹在NFET区域和PFET区域中的第一鳍结构上方的衬层；在第一鳍结构之间沉积介电层；在用硬掩模层覆盖NFET区域之后，使PFET区域中的衬层凹进；在用硬掩模层覆盖NFET区域的同时，在PFET区域中形成第二鳍结构；在去除硬掩模层之后，使NFET区域中的衬层凹进；以及使NFET区域和PFET区域中的介电层都凹进。
优选地，该方法还包括：在第一栅极区域和第二鳍结构中的第二栅极区域中形成伪栅极；在NFET的第一鳍结构中的第一S/D区域中形成第一源极/漏极(S/D)部件；在PFET的第二鳍结构中的第二S/D区域中形成第二S/D部件；在NFET区域中用第一高k/金属栅极(HK/MG)代替伪栅极，包裹在第一栅极区域中的第一鳍结构的上部上方；以及在PFET区域中用第二HK/MG代替伪栅极，包裹在第二栅极区域中的第二鳍结构的上部上方。
优选地，该方法还包括：控制衬层的凹进，使得衬层的顶面以第一距离位于第二外延半导体材料层之上；以及控制介电层的凹进，使得介电层的顶面以第二距离位于第二外延半导体材料层之上，第二距离大于第一距离。
附图说明
当结合附图进行阅读时，根据以下详细的描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，图中的各个部件没有按比例绘制。事实上，为了讨论的清楚，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的用于制造FinFET器件的示例性方法的流程图。
图2A是根据一些实施例的正在经受处理的示例性FinFET器件的图解立体图。
图2B是处于根据图1的方法构造的制造阶段的沿着图2A中的线A-A截取的示例性FinFET器件的截面图。
图3A是根据一些实施例的正在经受处理的示例性FinFET器件的图解立体图。
图3B是处于根据图1的方法构造的制造阶段的沿着图3A中的线A-A截取的示例性FinFET器件的截面图。
图4A和图4B是根据一些实施例的正在经受处理的FinFET器件的图解立体图。
图5是处于根据图1的方法构造的制造阶段的沿着图4A中的线A-A截取的示例性FinFET器件的截面图。
图6A和图6B是根据一些实施例的正在经受处理的FinFET器件的图解立体图。
图7A和图7B是根据一些实施例的正在经受处理的FinFET器件的图解立体图。
图8A至图8B以及图9是处于根据图1的方法构造的制造阶段的沿着图7B中的线B-B截取的示例性FinFET器件的截面图。
图10A和图10B是根据一些实施例的正在经受处理的FinFET器件的图解立体图。
图10C和图10D是处于根据图1的方法构造的制造阶段的沿着图10A中的线A-A截取的示例性FinFET器件的截面图。
图10E是处于根据图1的方法构造的制造阶段的沿着图10B中的线B-B截取的示例性FinFET器件的截面图。
图11A和图11B是根据一些实施例的正在经受处理的FinFET器件的图解立体图。
图12A和图12B是根据一些实施例的正在经受处理的FinFET器件的图解立体图。
图13A和图13B是根据一些实施例的正在经受处理的FinFET器件的图解立体图。
图13C和图13D是处于根据图1的方法构造的制造阶段的沿着图13A中的线A-A截取的示例性FinFET器件的截面图。
图13E和图13F是处于根据图1的方法构造的制造阶段的沿着图13B中的线B-B截取的示例性FinFET器件的截面图。
具体实施方式
以下公开提供了许多用于实现本发明的不同特征的不同实施例或实例。以下描述部件或配置的具体实例以简化本发明。当然，这些仅仅是实例而不用于限制。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件可以形成额外的部件使得第一部件和第二部分可以不直接接触的实施例。此外，本发明可以在各个实例中重复参考标号和/或字母。这些重复是为了简化和清楚，而且其本身并不表示所讨论的各个实施例和/或结构之间的关系。
本发明针对但不限于鳍式场效应晶体管(FinFET)器件。例如，FinFET器件可以是互补金属氧化物半导体(CMOS)器件，CMOS器件包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)FinFET器件。以下公开将以FinFET为实例继续说明本发明的各个实施例。然而，应该理解，本申请不应限于特定类型的器件，除非具体声明。
图1是根据一些实施例的用于制造FinFET器件200的方法100的流程图。应该理解，可以在该方法之前、期间和之后实施额外的步骤，并且对于方法的其他实施例，可以替换或消除所描述的一些步骤。参照附图对FinFET器件200及其制造方法100共同地进行描述。
参照图1以及图2A至图2B，方法100开始于步骤102，提供衬底210。衬底210可包括体硅衬底。可选地，衬底210可包括：元素半导体，诸如，晶体结构的硅或锗；化合物半导体，诸如，硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；或它们的组合。
在另一实施例中，衬底210具有绝缘体上硅(SOI)结构，其中绝缘体层位于衬底中。示例性绝缘体层可以为埋氧层(BOX)。SOI衬底可使用注氧隔离(SIMOX)、晶圆接合和/或其他合适的方法来制造。
在本实施例中，衬底210包括第一半导体材料层212、设置在第一半导体材料层212上方的第二半导体材料层214、以及设置在第二半导体材料层214上方的第三半导体材料层216。第二和第三半导体材料层214和216彼此不同。第二半导体材料层214具有第一晶格常数，而第三半导体材料层216具有不同于第一晶格常数的第二晶格常数。在本实施例中，第二半导体材料层214包括硅锗(SiGe)，而第一和第三半导体材料层212和216均包括硅。在各个实例中，第一、第二和第三半导体材料层212、214、216可包括锗(Ge)、硅(Si)、砷化镓(GaAs)、砷化铝镓(AlGaAs)、硅锗(SiGe)、磷砷化镓(GaAsP)或其他合适的材料。在本实施例中，第二和第三半导体材料层214和216通过外延生长来沉积，被称为毯式沟道外延。在各个实例中，外延工艺包括CVD沉积技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延和/或其他合适的工艺。
根据本领域已知的设计需求，衬底210可包括各种掺杂部件。在一些实施例中，根据设计需求(例如，p型衬底或n型衬底)，衬底210可包括各种掺杂区域。在一些实施例中，掺杂区域可掺杂有p型或n型掺杂物。例如，掺杂区域可掺杂有：p型掺杂物，诸如，硼或BF2；n型掺杂物，诸如，磷或砷；和/或它们的组合。掺杂区域可被配置用于n型FinFET(NFET)，或者可选地，被配置用于p型FinFET(PFET)。
参照图1以及图3A至图3B，方法100进行至步骤104，在衬底210中形成第一鳍220和沟槽230。第一鳍220具有第一宽度w1，第一宽度w1在约4nm至约10nm的范围内。在一个实施例中，在衬底210上方形成图案化鳍式硬掩模(FHM)层222。图案化FHM层222包括氧化硅、氮化硅、氮氧化硅或任何其他合适的介电材料。图案化硬掩模层222可包括单个材料层或多个材料层。图案化FHM层222可通过以下步骤来形成：通过热氧化、化学汽相沉积(CVD)、原子层沉积(ALD)或其他任何适当的方法沉积材料层，通过光刻工艺形成图案化光刻胶(抗蚀剂)层，以及穿过图案化光刻胶层的开口来蚀刻材料层以形成图案化FHM层222。
示例性光刻工艺可包括形成光刻胶层、通过光刻曝光工艺曝光光刻胶、执行曝光后烘烤工艺以及使光刻胶层显影以形成图案化光刻胶层。光刻工艺可选择被其他技术替代，诸如，电子束写入、离子束写入、无掩模图案化或分子印刷。
然后，通过图案化FHM层222来蚀刻衬底210，以在衬底210中形成第一鳍220和沟槽230。在另一实施例中，图案化光刻胶层直接用作蚀刻工艺的蚀刻掩模，以在衬底210中形成第一鳍220和沟槽230。蚀刻工艺可包括湿蚀刻或干蚀刻。在一个实施例中，湿蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液或其他合适的溶液。相应的蚀刻工艺可通过各种蚀刻参数(诸如，所使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、源功率、RF偏置电压、RF偏置功率、蚀刻剂流速和/或其他蚀刻参数)来调整。例如，湿蚀刻溶液可包括NH4OH、KOH(氢氧化钾)、HF(氢氟酸)、TMAH(四甲基氢氧化铵)、其他合适的湿蚀刻溶液或它们的组合。干蚀刻工艺包括使用氯基化学物的偏置等离子体蚀刻工艺。其他干蚀刻剂气体包括CF4、NF3、SF6和He。干蚀刻还可以使用诸如DRIE(深反应离子蚀刻)的机制来各向异性地执行。
在本实施例中，蚀刻深度受到控制，使得第三和第二半导体材料层216和214完全暴露于沟槽230中，而第一半导体材料层212部分地暴露于沟槽230中。因此，第一鳍结构220形成为具有作为上部的第三半导体材料层216、作为中部的第二半导体材料层214和作为底部的第一半导体材料层212。
在一些实施例中，FinFET器件200包括NFET器件，其标示为参考标号200A并称为NFET器件200A。FinFET器件200还包括PFET器件，其标示为参考标号200B并称为PFET器件200B。
参照图1以及图4A至图4B，方法100进行至步骤106，在衬底210上方形成图案化氧化硬掩模(OHM)310，包裹第一鳍220的一部分。在本实施例中，在NFET 200A中，图案化OHM310覆盖衬底210中的第一区域312而暴露第二区域314。在PFET 200B中，图案化OHM 310覆盖整个第一鳍220。图案化OHM层310可包括氧化硅、氮化硅、氮氧化硅或其他任何合适的介电材料。图案化OHM层310可通过以下步骤形成：通过热氧化、化学CVD、ALD或其他任何适当的方法沉积材料层，通过光刻工艺形成图案化光刻胶(抗蚀剂)层，以及穿过图案化光刻胶层的开口蚀刻材料层以形成图案化OHM层310。
还参照图1、图4A和图5，方法100进行至步骤108，对FinFET器件200执行热氧化工艺。在一个实施例中，热氧化工艺在氧环境下进行。在另一实施例中，热氧化工艺在蒸气环境和氧环境的组合中进行。在NFET200A的第二区域314中，在热氧化工艺期间，第一、第二和第三半导体材料层212、214和216的至少外层被分别转换为第一、第二和第三半导体氧化物部件322、324和326。而在NFET 200A的第一区域312以及整个PFET200B中，图案化OHM 310防止第一鳍结构220被氧化。因此，热氧化工艺被称为选择性氧化。
在热氧化工艺之后，第二区域314中的第一鳍结构220具有与第一区域312中的第一鳍结构220不同的结构。为了更清楚地描述，第二区域314中的第一鳍结构220(具有第二半导体氧化物部件324)被称为第二鳍结构320。因此，第二鳍结构320具有作为其上部的第三半导体材料层216、作为其中部的第二半导体材料层214(第二半导体氧化物部件324位于第二半导体材料层214的外层)、以及作为其底部的第一半导体材料层。
在本实施例中，热氧化工艺受到控制，使得第二半导体材料层214比第一和第三半导体材料层212和216都氧化得快得多。换句话说，与第二半导体氧化物部件324相比，第一和第三半导体氧化物部件322和326非常薄。作为实例，在约400℃至约600℃范围内的温度以及在约1atm至约20atm的压力下，在H2O反应气体中执行对FinFET器件200的热氧化工艺。在氧化工艺之后，执行清洁工艺以去除第一和第三半导体氧化物部件322和326。可使用稀释氢氟酸(DHF)来执行清洁工艺。
在本实例中，第二半导体氧化物部件324在垂直方向上延伸，其中从第二半导体材料层214的顶面到底面的水平尺寸是变化的。在本实例中，第二半导体氧化物部件324的水平尺寸达到其最大值(被称为第一宽度w2)，并且在接近第二半导体氧化物部件324的顶面和底面时减小到几乎为零，从而产生截面图中的橄榄形。通过调整热氧化工艺、选择第二半导体材料层214的组成和厚度以及调整氧化温度，实现第二半导体氧化物部件324的目标第二宽度w2，这对第一鳍220中的第三半导体材料层216施加足够的应力，其中位于栅极区域下面的栅极沟道将被限定在第三半导体材料层216中，这将在后面进行描述。
在一个实施例中，第二半导体材料层214包括硅锗(SiGex1)，而第一和第三半导体材料层212和216包括硅(Si)。下标x1是原子百分比形式的第一Ge组分，并且其可以被调整以满足预定的体积膨胀目标。在一个实施例中，x1选择为在约20％至约80％的范围内。通过热氧化工艺来氧化SiGex1层214的外层，从而形成氧化硅锗(SiGeO)部件324。SiGeO部件324的第二宽度w2在约3nm至约10nm的范围内。SiGex1层214的中心部分变为第二Ge组成x2，x2远高于x1。中心部分的SiGex2的尺寸和形状随着诸如热氧化温度和时间的工艺条件而变化。而且，中心部分的第二Ge组成x2高于其他部分，诸如，顶部、底部、左侧部和右侧部。
参照图1以及图6A至图6B，方法100进行至步骤110，沉积衬层405以共形地包裹在NFET器件200A和PFET器件200B中的第一鳍结构220以及第二鳍结构320上方。首先，通过蚀刻工艺(诸如选择性湿蚀刻)去除图案化OHM层310。在本实施例中，衬层405包括氮化硅、氮氧化硅、氧化铝或其他合适的材料。衬层405具有在约至约范围内的第一厚度。在本实施例中，通过ALD沉积衬层405，以实现包裹在第一鳍结构220上方的足够的膜覆盖度。可选地，可通过CVD、物理汽相沉积(PVD)或其他合适的技术沉积衬层405。在一个实施例中，衬层405由两层形成，第一层402和沉积在第一层404上方的第二层404(未示出)。第一层402可包括Si和氮氧化硅，而第二层404可包括氮化硅和氧化铝。第一层402具有在约至约范围内的第二厚度，而第二层404具有在约至约范围内的第三厚度。在本实施例中，衬层405设计为防止第二半导体材料层214在下续或后续工艺中被氧化的缓冲层以及防止第二半导体材料层214的向外扩散的阻挡层，这将在下面进行详细描述。
参照图1以及图7A至图7B，方法100进行至步骤112，在NFET器件200A和PFET器件200B中，在衬底210上方沉积介电层410，包括填充到沟槽230中。介电层410可包括氧化硅、氮化硅、氮氧化硅、旋涂玻璃、旋涂聚合物或其他合适的材料或它们的组合。介电层410可通过CVD、物理汽相沉积(PVD)、ALD、热氧化、旋涂或其他合适的技术或它们的组合来沉积。如前所述，使衬层405覆盖第一鳍结构220和第二鳍结构320，这对在形成介电层410期间(诸如，在介电层410的热固化工艺中)所引发的不利影响提供了缓冲。
还参照图1以及图7A至图7B，方法100进行至步骤114，在衬底210上方形成图案化HM层415以覆盖NFET 200A但不覆盖PFET 200B。图案化HM层415可包括氮化硅、氮氧化硅、碳化硅或任何其他合适的介电材料。图案化HM层415可类似于步骤106中形成图案化OHM层310而形成。
参照图1和图8A，方法100进行至步骤116，使PFET 200B中的第一鳍结构220中的衬层405和第三半导体材料层216凹进，而NFET 200A被图案化HM层415所保护。通过合适的蚀刻工艺(诸如选择性湿蚀刻、选择性干蚀刻或它们的组合)使衬层405和第三半导体材料层216凹进。可选地，通过形成在PFET 200B上方的图案化光刻胶层使衬层405和第三半导体材料层216凹进。在本实施例中，控制凹进工艺以使得剩余衬层405的顶面位于剩余第三半导体材料层216的下方但以第一距离d1位于第二半导体材料层214之上。如前所述，第一距离d1被设计为足以阻止第二半导体材料214沿着介电层410与第三半导体材料层216的交界面412向上外扩散到第一鳍结构的上部，栅极沟道稍后将形成在第一鳍结构的上部。例如，第一距离d1足以阻止SiGe层214中的Ge沿着介电层410与Si层216的交界面412向上外扩散。在一个实施例中，第一距离d1在约2nm至约10nm的范围内。
在另一实施例中，如图8B所示，其中衬层由第一层402和第二层404形成，使第一层402凹进以使剩余第一层402的顶面以第二距离d2位于第二半导体材料层214之上，并且使第二层404凹进以使剩余第二层404的顶面以第一距离d1位于第二半导体材料层214之上。第二距离d2大于第一距离d1。在一个实施例中，第二距离d2在约5nn至约20nm的范围内。衬层的双层将进一步阻止第二半导体材料层214沿着介电层410与第三半导体材料层216的交界面412的向外扩散。
参照图1、图8A和图9，方法100进行至步骤118，在凹进的第三半导体材料层216上方形成第四半导体材料层430，以在PFET器件200B中形成第三鳍结构440，而NFET 200A被图案化HM层415所保护。第四半导体材料层430可通过外延生长沉积。外延工艺可包括CVD沉积技术、分子束外延和/或其他合适的工艺。第四半导体材料层430可包括锗(Ge)、硅(Si)、砷化镓(GaAs)、砷化铝镓(AlGaAs)、硅锗(SiGe)、磷砷化镓(GaAsP)或其他合适的材料。在本实施例中，第四半导体材料层430为SiGe。因此，第三鳍结构440形成为具有作为其上部的第四半导体材料层430、作为其中上部的第三半导体材料层216、作为其中下部的第二半导体材料层214以及作为其底部的第一半导体材料层212。
此后可以执行CMP工艺以去除过量的第四半导体材料层430并对PFET 200B的顶面进行平坦化。通过适当的蚀刻工艺(诸如湿蚀刻、干蚀刻或它们的组合)去除NFET 200A中的HM层415。
参照图1以及图10A至图10E，方法进行至步骤120，使NFET器件200A中的衬层405凹进并且使NFET器件200A和PFET器件200B中的介电层凹进。首先，通过适当的蚀刻工艺(诸如，选择性湿蚀刻或选择性干蚀刻)从NFET器件200A去除图案化HM层415。然后，通过适当的蚀刻工艺(诸如，选择性湿蚀刻、选择性干蚀刻或它们的组合)使衬层405凹进。在本实施例中，控制凹进工艺以使剩余衬层405的顶面位于剩余第三半导体材料层216的下方但以第一距离d1位于第二半导体材料层214之上。在衬层由第一层402和第二层404形成的另一实施例中，使第一层402凹进以使剩余第一层402的顶面以第二距离d2位于第二半导体材料层214之上。
然后，使NFET器件200A和PFET器件200B中的介电层410凹进，以暴露第一鳍结构220(NFET器件200A中)的上部和第三鳍结构(PFET器件200B中)的上部。在本实施例中，控制凹进工艺，以使凹进的介电层410的顶面以第三距离d3位于衬层405的顶面之上。在本实施例中，第三距离d3被设计为足以保持衬层405远离第一、第二和第三鳍结构的上部(栅极区域将形成在第一、第二和第三鳍结构的上部中)，从而避免衬层405对栅极区域的不利影响，诸如衬层405中的固定电荷。在一个实施例中，第三距离d3在约3nm到约10nm的范围内。可选地，在衬层由第一衬层402和第二衬层404形成的情况下，凹进的介电层410的顶面以第三距离d3位于第二层404的顶面之上。第一层402的顶面与凹进的介电层410的顶面处于同一水平面或位于其下方。
在一个实施例中，沟槽230中的凹进的介电层410形成浅沟槽隔离(STI)部件。
还参照图10A和图10B，在一些实施例中，第一、第二和第三鳍结构220、320和440包括源极/漏极(S/D)区域450和栅极区域460。在又一实施例中，S/D区域450的一个为源极区域，而S/D区域450的另一个为漏极区域。S/D区域450通过栅极区域460分隔开。为了更好地进行描述，NFET器件200A中的S/D区域和栅极区域被称为第一S/D区域450A和第一栅极区域460A；而PFET器件200B中的S/D区域和栅极区域被称为第二S/D区域450B和第二栅极区域460B。
在一个实施例中，第一S/D区域450A位于第一鳍结构220的一部分中，被位于部分第二鳍结构320中的第一栅极区域460分隔开。在PFET器件200B中，第三鳍结构440包括被第二栅极区域460B分隔开的第二S/D区域450B。
参照图1以及图11A至图11B，方法进行至步骤122，在第一和第二栅极区域460A和460B中形成栅叠件510以及在栅叠件510的侧壁上形成侧壁间隔件520。在使用后栅极工艺的一个实施例中，栅叠件510是伪栅极，并且将在随后的阶段被最终的栅叠件所代替。具体地，在源极/漏极形成期间的高温热工艺(诸如，用于S/D激活的热退火)之后，伪栅叠件510稍后将被高k介电层(HK)和金属栅电极(MG)所代替。伪栅叠件510形成在衬底210上并且部分地设置在第一栅极区域460A中的第二鳍结构320上方以及第二栅极区域460B中的第三鳍结构440上方。在一个实施例中，伪栅叠件510包括介电层512、电极层514和栅极硬掩模(GHM)516。伪栅叠件510通过合适的步骤(包括沉积和图案化)来形成。图案化工艺还包括光刻和蚀刻。在各个实例中，沉积包括CVD、物理汽相沉积(PVD)、ALD、热氧化、其他合适的技术或它们的组合。光刻工艺包括光刻胶(或抗蚀剂)涂布(例如，旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、使光刻胶显影、冲洗、干燥(例如，硬烘烤)、其他合适的工艺和/或它们的组合。蚀刻工艺包括干蚀刻、湿蚀刻和/或其他蚀刻方法(例如，反应离子蚀刻)。
介电层512包括氧化硅。可选地或额外地，介电层512可包括氮化硅、高k介电材料或其他合适的材料。电极层514可包括多晶体硅(多晶硅)。GHM 516包括合适的介电材料，诸如，氮化硅、氮氧化硅或碳化硅。侧壁间隔件520可包括介电材料，诸如，氧化硅、氮化硅、碳化硅、氮氧化硅或它们的组合。侧壁间隔件520可包括多层。侧壁间隔件520的典型形成方法包括在栅叠件510上方沉积介电材料，然后各向异性地回蚀介电材料。回蚀工艺可包括多步骤蚀刻，以获得蚀刻的选择性、灵活性和期望的过蚀刻控制。
再次参照图1以及图11A至图11B，方法100进行至步骤124，在第一S/D区域450A中形成第一S/D部件610A以及在第二S/D区域450B中形成第二S/D部件610B。在一个实施例中，第一S/D部件610A通过使第一S/D区域450A中的第一鳍220的上部的一部分凹进来形成，而第二S/D部件610B通过使第二S/D区域450B中的第三鳍440的上部的一部分凹进来形成。在一个实施例中，第一鳍结构220和第三鳍结构440在一次蚀刻工艺中凹进。在另一实施例中，第一鳍结构220和第三鳍结构440在两次不同的蚀刻工艺中凹进。在本实施例中，为了获得工艺集成灵活性，控制凹进工艺以使第三半导体材料层216的一部分保留在第一鳍结构220中并且使第四半导体材料层430的一部分保留在第三鳍结构440中。
然后，在第一S/D区域450A中的凹进的第一鳍结构220上以及第二S/D区域450B中的凹进的第三鳍结构440上外延生长第一S/D部件610A和第二S/D部件610B。第一和第二S/D部件610A和610B包括Ge、Si、GaAs、AlGaAs、SiGe、GaAsP或其他合适的材料。第一和第二S/D部件610A和610B可通过一次或多次外延或取向附生(epi)工艺形成。还可以在外延工艺期间掺杂(诸如，原位掺杂)第一和第二S/D部件610A和610B。可选地，不原位掺杂第一和第二S/D部件610A和610B，而执行注入工艺(即，结注入工艺)以掺杂第一和第二S/D部件610A和610B。
在一个实施例中，第一S/D部件610A通过外延生长掺杂有碳的Si层以形成作为第一S/D部件610A的下部的Si:Cz以及外延生长掺杂有磷的Si层以形成作为第一S/D部件610A的上部的Si:P来形成，其中，z是原子百分比形式的碳组成。在一个实施例中，z在约0.5％至约1.5％的范围内。Si:Cz具有在约5nm至约15nm范围内的厚度。Si:P具有在约20nm至约35nm范围内的厚度。
在另一实施例中，第二S/D部件610B通过外延生长掺杂有硼的SiGe层以形成SiGeαB来形成，其中，α是原子百分比形式的锗组成。在一个实施例中，α在约60％至约100％的范围内。
参照图1以及图12A至图12B，方法100进行至步骤126，在伪栅叠件510的间隙之间的衬底210上形成层间介电(ILD)层720。ILD层720包括氧化硅、氮氧化硅、低k介电材料或其他合适的介电材料。ILD层720可包括单层，或者可选地包括多层。ILD层720通过合适的技术形成，诸如CVD、ALD和旋涂(SOG)。此后可以执行化学机械抛光(CMP)工艺以去除过量的ILD层720，并且平坦化FinFET器件200的顶面。
还参照图1以及图12A至图12B，方法100进行至步骤128，去除第一栅极区域460A中的伪栅叠件510以形成一个或多个第一栅极沟槽810A以及去除第二栅极区域460B中的伪栅叠件510以形成一个或多个第二栅极沟槽810B。第二鳍结构320的上部暴露于第一栅极沟槽810A，而第三鳍结构440的上部暴露于第二栅极沟槽810B。通过蚀刻工艺(诸如选择性湿蚀刻或选择性干蚀刻)去除伪栅叠件510，蚀刻工艺被设计为相对于第一栅极沟槽810A中的第三半导体材料层216和第二栅极沟槽810B中的第四半导体材料层430具有足够的蚀刻选择性。蚀刻工艺可包括具有相应的蚀刻剂的一次或多次蚀刻步骤。也去除栅极硬掩模层516和间隔件520。可选地，可通过包括光刻图案化和蚀刻工艺的一系列工艺来去除伪栅极堆叠件510。
参照图1以及图13A至13F，方法进行至步骤130，在衬底210上方形成第一和第二高k/金属栅极(HK/MG)堆叠件910A和910B，分别包裹在第一栅极沟槽810A中的第二鳍320的一部分上方以及第二栅极沟槽810B中的第三鳍结构440的一部分上方。第一和第二HK/MG堆叠件910A和910B包括栅极介电层和栅极介电层上的栅电极。在一个实施例中，栅极介电层包括具有高介电常数的介电材料层(在本实施例中，HK介电层的介电常数大于热氧化硅的介电常数)，并且栅电极包括金属、金属合金或金属硅化物。第一和第二HK/MG堆叠件910A和910B的形成包括沉积以形成各种栅极材料以及CMP工艺以去除过量的栅极材料并且平坦化NFET器件200A和PFET器件200B的顶面。
在一个实施例中，栅极介电层包括通过合适的方法(诸如，原子层沉积(ALD)、CVD、热氧化或臭氧氧化)而沉积的界面层(IL)。IL包括氧化物、HfSiO和氮氧化物。HK介电层通过合适的技术(诸如，ALD、CVD、金属有机CVD(MOCVD)、物理汽相沉积(PVD)、其他合适的技术或它们的组合)沉积在IL上。HK介电层可包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)或其他合适的材料。栅极介电层包裹在第一栅极区域460A中的第二鳍结构320的上部以及第二栅极区域460B中的第三鳍结构440的上部上方。
金属栅(MG)电极可包括单层，或者可选地包括多层结构(诸如具有功函以增强器件性能的金属层(功函金属层)、衬层、润湿层、粘合层和导电层(金属、金属合金或金属硅化物)的各种组合)。MG电极可包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、任何合适的材料或它们的组合。MG电极可通过ALD、PVD、CVD或其他合适的工艺来形成。MG电极可针对NFET 200A和PFET200B分别以不同的金属层来形成。可执行CMP工艺以去除过量的MG电极。
再次参照图13C和图13D，在NFET器件200A中，第一HK/MG栅极910A包裹在第二鳍320的上部上方，其中第二鳍结构320包括作为其上部的半导体材料层216、作为其中部的第二半导体材料层214(半导体氧化物部件324位于第二半导体材料层214的外层)以及作为其底部的第一半导体材料层212。衬层405沿着第二鳍结构的侧壁形成，包裹在第三半导体材料216的下部、半导体氧化物部件324以及第一半导体材料层212的外沿。衬层405的顶面以第一距离d1位于第二半导体材料层214的顶面之上。凹进的介电层410形成在每个第二鳍结构320之间。凹进的介电层410的顶面以第三距离d3位于衬层405的顶面之上。
再次参照图13E和图13F，在PFET器件200B中，第二HK/MG栅极910B包裹在第三鳍440的上部上方，其中第三鳍包括作为其上部的第四半导体材料层430、作为其中上部的第三半导体材料层216、作为其中下部的第二半导体材料层214以及作为其底部的第一半导体材料层212。衬层405沿着第三鳍结构440的侧壁形成，包裹在第三半导体材料216的下部、第二半导体材料214以及第一半导体材料层212的外沿。衬层405的顶面以第一距离d1位于第二半导体材料层214的顶面之上。凹进的介电层410形成在每个第三鳍440之间，并且凹进的介电层410的顶面以第三距离d3位于衬层405的顶面之上。
当衬层包括第一层402和第二层404时，第一层402的顶面以第二距离d2位于第二半导体材料层214之上，第二距离d2大于第一距离d1，但第一层402的顶面与凹进的介电层410的顶面处于同一水平面或者低于凹进的介电层410的顶面。
FinFET器件200可经过进一步的CMOS或MOS技术处理以形成本领域已知的各种部件和区域。例如，随后的处理可在衬底210上形成各种接触件/通孔/线以及多层互连部件(例如，金属层和层间电介质)，它们被配置为连接各个部件以形成包括一个或多个FinFET鳍式场效应晶体管的功能电路。在又一实例中，多层互连件包括诸如通孔或接触件的垂直互连件以及诸如金属线的水平互连件。各种互连部件可包括各种导电材料，包括铜、钨和/或硅化物。在一个实例中，镶嵌和/或双镶嵌工艺用于形成含铜的多层互连结构。
可以在方法100之前、期间和之后实施额外的操作，并且对于方法的其他实施例，可以取代或消除上述一些操作。
基于上述内容，本发明提供了FinFET的结构。该结构采用包裹在鳍结构上方的衬层以阻止栅极区域中的向外扩散并且为栅极区域中的鳍结构提供缓冲。该结构展示出器件性能改进。
本发明提供了鳍式场效应晶体管(FinFET)器件的实施例。该器件包括具有第一栅极区域的衬底、位于第一栅极区域中的衬底上方的第一鳍结构。第一鳍结构包括上部半导体材料构件、被氧化物部件环绕的下部半导体材料构件以及包裹在下部半导体材料构件的氧化物部件周围并且向上延伸以包裹在上部半导体材料构件的下部周围的衬层。该器件还包括与上部半导体材料构件的下部横向邻近的介电层。因此，上部半导体材料构件包括既不与介电层横向邻近也不被衬层包裹的中部。
本发明还提供了鳍式场效应晶体管(FinFET)器件的另一实施例。该器件包括第二鳍结构，第二鳍结构位于第二栅极区域中的衬底上方。第二鳍结构包括上部半导体材料构件、中间半导体材料构件和下部半导体材料构件，衬层包裹在下部半导体材料构件周围并且向上延伸以包裹在中部半导体材料构件的下部周围。该器件还包括与中间半导体材料构件的中部横向邻近的介电层。中间半导体材料构件包括既不与介电层横向邻近也不被衬层包裹的上部，衬底上方的第二高k/金属栅叠件包裹在第二栅极区域中的上部半导体材料构件以及中间半导体材料构件的上部上方。
本发明还提供了用于制造FinFET的方法。该方法包括：提供衬底，衬底具有n型鳍式场效应晶体管(NFET)区域和p型鳍式场效应晶体管(PFET)区域；在NFET区域和PFET区域中形成第一鳍结构。第一鳍结构包括：作为其上部的第一外延半导体材料层；作为其中部的第二外延半导体材料层，半导体氧化物部件位于第二外延半导体材料层的外层；以及作为其底部的第三外延半导体材料层。该方法还包括：在NFET区域和PFET区域上方形成图案化氧化硬掩模(OHM)，以暴露NFET区域的第一栅极区域中的第一鳍结构。该方法还包括施加退火以在第一栅极区域中的第一鳍结构中的第二外延半导体材料层的外层处形成半导体氧化物部件。该方法还包括：在NFET区域和PFET区域中形成包裹在第一鳍上方的衬层；在第一鳍之间沉积介电层；在用硬掩模层覆盖NFET区域之后，使衬层凹进并在PFET区域中形成第二鳍结构。该方法还包括：在去除硬掩模层之后，使NFET区域中的衬层凹进；以及使NFET区域和PFET区域中的介电层凹进。
上面论述了多个实施例的特征使得本领域技术人员能够更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以容易地使用本公开作为基础来设计或修改用于执行与本文所介绍实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员还应该意识到，这种等同结构不背离本发明的精神和范围，并且可以在不背离本发明的精神和范围的情况下做出各种变化、替换和改变。

Claims (20)

1.一种鳍式场效应晶体管(FinFET)器件，包括：
衬底，具有第一栅极区域和第二栅极区域；
第一鳍结构，位于所述第一栅极区域中的所述衬底上方，所述第一鳍结构包括：
上部半导体材料构件；
下部半导体材料构件，被氧化物部件环绕；和
衬层，包裹在所述下部半导体材料构件的所述氧化物部件周围，并且向上延伸以包裹在所述上部半导体材料构件的下部周围；以及
介电层，与所述上部半导体材料构件的下部横向邻近，
其中，所述上部半导体材料构件包括既不与所述介电层横向邻近也不被所述衬层包裹的中部，
其中，所述介电层的顶面以第一距离位于所述衬层的顶面之上，所述第一距离在3nm至10nm的范围内。
2.根据权利要求1所述的器件，还包括：
第一高k/金属栅叠件，包裹在所述上部半导体材料构件上方，包括包裹在所述上部半导体材料构件的中部上方。
3.根据权利要求1所述的器件，其中，所述衬层包括选自由氮化硅、氮氧化硅和氧化铝组成的组的一种或多种材料。
4.根据权利要求1所述的器件，其中，
所述介电层的顶面以第二距离位于所述下部半导体材料构件的顶面之上，所述第二距离在5nm至20nm的范围内。
5.根据权利要求1所述的器件，其中，所述衬层通过原子层沉积(ALD)来沉积，所述衬层的厚度在至的范围内。
6.根据权利要求1所述的器件，其中，
所述上部半导体材料构件包括外延硅(Si)；
所述下部半导体材料构件包括外延硅锗(SiGe)；以及
所述氧化物部件包括氧化硅锗(SiGeO)。
7.根据权利要求1所述的器件，其中，所述衬层包括：第一层，包裹在所述下部半导体材料构件的氧化物部件周围并且向上延伸以包裹在所述上部半导体材料构件的下部周围；以及第二层，包裹在所述第一层上方。
8.根据权利要求7所述的器件，其中，
所述第一层包括选自由硅和氮氧化硅组成的组的一种或多种材料；
所述第二层包括选自由氮化硅、氮氧化硅和氧化铝组成的组的一种或多种材料；
所述第一层的厚度在至的范围内；
所述第二层的厚度在至的范围内；
所述第一层的顶面位于所述介电层的顶面下方；以及
所述第二层的顶面以一距离位于所述介电层的顶面下方，该距离在3nm至10nm的范围内。
9.根据权利要求1所述的器件，还包括：
第二鳍结构，位于所述第二栅极区域中的所述衬底上方，所述第二鳍结构包括：
上部半导体材料构件；
中间半导体材料构件；和
下部半导体材料构件；
所述衬层，包裹在所述第二鳍结构的所述下部半导体材料构件周围，并且向上延伸以包裹所述第二鳍结构的所述中间半导体材料构件的下部周围；
所述介电层，与所述第二鳍结构的所述中间半导体材料构件的中部横向邻近，
其中，所述第二鳍结构的所述中间半导体材料构件包括既不与所述介电层横向邻近也不被所述衬层包裹的上部；以及
第二高k/金属栅叠层，位于所述衬底上方，包裹在所述第二栅极区域中的所述第二鳍结构的所述上部半导体材料构件以及所述第二鳍结构的所述中间半导体材料构件的上部上方。
10.根据权利要求9所述的器件，其中，
所述第二鳍结构的所述上部半导体材料构件包括外延硅锗(SiGe)；
所述第二鳍结构的所述中间半导体材料构件包括外延硅(Si)；以及
所述第二鳍结构的所述下部半导体材料构件包括外延SiGe。
11.根据权利要求1所述的器件，还包括：
第一源极和漏极(S/D)区域，被所述衬底上方的所述第一栅极区域分隔开；
所述第一鳍结构，在所述第一源极和漏极区域中具有凹进的上部半导体材料构件；以及
第一源极/漏极部件，位于所述凹进的上部半导体材料构件的顶部上。
12.根据权利要求9所述的器件，还包括：
第二源极和漏极(S/D)区域，被所述衬底上方的所述第二栅极区域分隔开；
所述第二鳍结构，在所述第二源极和漏极区域中具有凹进的上部半导体材料构件；以及
第二源极/漏极部件，位于所述第二鳍结构的所述凹进的上部半导体材料构件的顶部上。
13.一种鳍式场效应晶体管(FinFET)器件，包括：
衬底，具有n型鳍式场效应晶体管NFET区域和p型鳍式场效应晶体管PFET区域；
第一鳍结构，位于所述NFET区域中的所述衬底上方，所述第一鳍结构包括：
外延硅(Si)层，作为所述第一鳍结构的上部；和
第一外延硅锗(SiGe)，并且氧化硅锗(SiGeO)部件位于所述第一外延硅锗的外层处，以作为所述第一鳍结构的下部；
衬层，包裹在所述氧化硅锗部件周围，并且向上延伸以包裹在所述外延硅层的下部周围；以及
介电层，与所述外延硅层的下部横向邻近，
其中，所述外延硅层包括既不与所述介电层横向邻近也不被所述衬层包裹的中部，
第二鳍结构，位于所述PFET区域中的所述衬底上方，所述第二鳍结构包括：
第二外延硅锗层，作为所述第二鳍结构的上部；
所述外延硅层，作为所述第二鳍结构的中部；和
所述第一外延硅锗层，作为所述第二鳍结构的底部；
所述衬层，包裹在作为所述第二鳍结构的底部的所述第一外延硅锗层周围，并且向上延伸以包裹在作为所述第二鳍结构的中部的所述外延硅层的下部周围；以及
所述介电层，与作为所述第二鳍结构的中部的所述外延硅层的上部横向邻近，
其中，所述第二外延硅锗层既不与所述介电层横向邻近也不被所述衬层包裹。
14.根据权利要求13所述的器件，其中，所述衬层包括选自由氮化硅、氮氧化硅和氧化铝所组成的组的一种或多种材料。
15.根据权利要求13所述的器件，其中，所述衬层通过原子层沉积(ALD)沉积，所述衬层的厚度在至的范围内。
16.根据权利要求13所述的器件，其中，
所述介电层的顶面以一距离位于所述衬层的顶面之上，该距离在3nm至10nm的范围内；以及
所述介电层的顶面以一距离位于所述第一外延硅锗层的顶面之上，该距离在5nm至20nm的范围内。
17.根据权利要求13所述的器件，还包括：
第一栅极区域，位于所述第一鳍结构的一部分中；
第一高k/金属栅叠层，位于所述衬底上方，包裹在所述第一鳍结构的所述外延硅层的一部分上方；
第一源极和漏极(S/D)区域，位于所述第一鳍结构的部分中并且被所述衬底上方的所述第一栅极区域分隔开；
第一源极/漏极部件，位于所述第一源极和漏极区域中的凹进的所述外延硅层的顶部上；
第二栅极区域，位于所述第二鳍结构的一部分中；
第二高k/金属栅叠层，位于所述衬底上方，包裹在所述第二鳍结构的所述第二外延硅锗层以及作为所述第二鳍结构的中部的所述外延硅层的一部分上方；
第二源极和漏极区域，位于所述第二鳍结构的部分中并且被所述衬底上方的所述第二栅极区域分隔开；以及
第二源极/漏极部件，位于凹进的所述第二外延硅锗层的顶部上。
18.一种形成鳍式场效应晶体管(FinFET)器件的方法，包括：
提供衬底，所述衬底具有n型鳍式场效应晶体管NFET区域和p型鳍式场效应晶体管PFET区域；
在所述NFET区域和所述PFET区域中形成第一鳍结构，所述第一鳍结构包括：
第一外延半导体材料层，作为所述第一鳍结构的上部；
第二外延半导体材料层，作为所述第一鳍结构的下部；以及
在所述NFET区域和所述PFET区域上方形成图案化氧化硬掩模(OHM)，以暴露所述NFET区域的第一栅极区域中的所述第一鳍结构；
施加退火，以在所述第一栅极区域中的所述第一鳍结构中的所述第二外延半导体材料层的外层处形成半导体氧化物部件；
形成分别包裹在所述NFET区域和所述PFET区域中的所述第一鳍结构上方的衬层；
在所述第一鳍结构之间沉积介电层；
在用硬掩模层覆盖所述NFET区域之后，使所述PFET区域中的所述衬层凹进；
在用所述硬掩模层覆盖所述NFET区域的同时，在所述PFET区域中形成第二鳍结构；
在去除所述硬掩模层之后，使所述NFET区域中的所述衬层凹进；以及
使所述NFET区域和所述PFET区域中的所述介电层都凹进。
19.根据权利要求18所述的方法，还包括：
在所述第一栅极区域和所述第二鳍结构中的第二栅极区域中形成伪栅极；
在所述NFET的所述第一鳍结构中的第一源极和漏极区域中形成第一源极/漏极(S/D)部件；
在所述PFET的所述第二鳍结构中的第二源极和漏极区域中形成第二源极和漏极部件；
在所述NFET区域中用第一高k/金属栅极(HK/MG)代替所述伪栅极，包裹在所述第一栅极区域中的所述第一鳍结构的上部上方；以及
在所述PFET区域中用第二高K/金属栅极代替所述伪栅极，包裹在所述第二栅极区域中的所述第二鳍结构的上部上方。
20.根据权利要求18所述的方法，还包括：
控制所述衬层的凹进，使得所述衬层的顶面以第一距离位于所述第二外延半导体材料层之上；以及
控制所述介电层的凹进，使得所述介电层的顶面以第二距离位于所述第二外延半导体材料层之上，所述第二距离大于所述第一距离。
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