US10056486B2 - Methods for fin thinning providing improved SCE and S/D EPI growth - Google Patents

Methods for fin thinning providing improved SCE and S/D EPI growth Download PDF

Info

Publication number
US10056486B2
US10056486B2 US15/079,142 US201615079142A US10056486B2 US 10056486 B2 US10056486 B2 US 10056486B2 US 201615079142 A US201615079142 A US 201615079142A US 10056486 B2 US10056486 B2 US 10056486B2
Authority
US
United States
Prior art keywords
fin
forming
cavity
width
thinning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US15/079,142
Other versions
US20170278965A1 (en
Inventor
Shesh Mani Pandey
Pei Zhao
Zhenyu Hu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Priority to US15/079,142 priority Critical patent/US10056486B2/en
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HU, ZHENYU, PANDEY, SHESH MANI, ZHAO, Pei
Publication of US20170278965A1 publication Critical patent/US20170278965A1/en
Application granted granted Critical
Publication of US10056486B2 publication Critical patent/US10056486B2/en
Assigned to WILMINGTON TRUST, NATIONAL ASSOCIATION reassignment WILMINGTON TRUST, NATIONAL ASSOCIATION SECURITY AGREEMENT Assignors: GLOBALFOUNDRIES INC.
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES INC.
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Definitions

  • the present disclosure relates generally to designing and fabricating integrated circuit (IC) devices.
  • the present disclosure is particularly applicable to forming silicon (Si) fins with improved short-channel performance and source/drain (S/D) formation in FinFET IC devices.
  • a width of a Si fin may be based on a required/desired short-channel performance (e.g. better with a narrow width) while the same width may negatively impact formation and characteristics of S/D regions in the Si fin leading to undesired performance issues.
  • FIG. 1A illustrates a top view of example Si fins 101 , in a substrate 103 , with a uniform width W across a gate/channel region 105 , and S/D regions 107 and 109 .
  • the width W may be optimized to improve short-channel effects (SCE) in the channel region, wherein a narrower width can provide for a better short-channel performance.
  • SCE short-channel effects
  • a narrower fin width may hinder formation of an optimum S/D epi width; thus, impacting drive current of the device.
  • FIG. 1B illustrates a cross-sectional view of the source 107 (or drain 109 ) regions along a cross-sectional reference line 1 B- 1 B′.
  • semiconductor material 111 e.g., Si, silicon-germanium
  • the epi growths 111 on the fins may help to reduce electrical resistance in the S/D regions, provide larger areas for electrical contacts to the S/D regions, and provide additional physical support/strength for the fins.
  • a volume of an epi growth 111 may be limited by the width of a fin 101 .
  • An aspect of the present disclosure is a method for thinning a channel region of a Si fin in a FinFET device.
  • An aspect of the present disclosure is a FinFET device including Si fins with different widths along each Si fin.
  • some technical effects may be achieved in part by a method including forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin within the cavity; and forming a high-k/metal gate in the cavity.
  • Another aspect includes forming a plurality of Si fins, parallel to and spaced from each other, in the Si layer; and for each Si fin: in a channel region over the Si fin, forming a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin within the cavity; and forming a high-k/metal gate in the cavity.
  • One aspect includes thinning by etching.
  • An additional aspect includes oxidizing an outer layer of each sidewall; and removing the oxidized layer.
  • One aspect includes thinning the sidewalls based on criteria to control short-channel effects. Another aspect includes thinning each sidewall by 2-20% of a width of each Si fin. A further aspect includes thinning each sidewall by 0.5-3 nm.
  • An additional aspect includes forming the S/D regions by epitaxially growing a layer of silicon-germanium at the opposite ends of each Si fin.
  • One aspect includes forming the S/D regions by epitaxially growing a layer of doped-silicon at the opposite ends of each Si fin.
  • Another aspect of the present disclosure includes a device including: a Si fin in a Si layer; S/D regions at opposite ends of the Si fin; and a high-k/metal gate in a channel region over the Si fin, wherein the Si fin in the channel region has a narrower width than widths of other regions of the Si fin.
  • a further aspect includes a plurality of Si fins, parallel to and spaced from each other, in the Si layer; S/D regions at opposite ends of each Si fin; and a high-k/metal gate in a channel region over each Si fin, wherein each Si fin in the channel region has a narrower width than widths of other regions of the Si fin.
  • An additional aspect includes a width of each Si fin in the channel region being based on short-channel performance criteria.
  • each Si fin in the channel region is 2-20% narrower than widths of other regions of each Si fin.
  • each Si fin in the channel region is 0.5-3 nm narrower than widths of other regions of each Si fin.
  • a further aspect includes the S/D regions including epitaxially grown silicon-germanium (eSiGe). Another aspect includes the S/D regions including epitaxially grown doped-silicon.
  • FIGS. 1A and 1B illustrate a top view of example Si fins and a cross-sectional view of the Si fins with epi growth, respectively;
  • FIGS. 2A, 2E, and 2G illustrate top views
  • FIGS. 2B through 2D, 2F , and 2 H illustrate cross-sectional views, of processes for thinning sections of Si fins, in accordance with an exemplary embodiment.
  • the present disclosure addresses the problems of insufficient SCE control or small epitaxial growth area for S/D regions attendant upon Si fins having a constant width.
  • the present disclosure addresses and solves such problems, for instance, by, inter alia, removing a layer from sidewalls of a fin in a gate/channel area based on criteria for controlling SCE.
  • FIG. 2A illustrates a top view of parallel Si fins 201 formed (e.g. by conventional FinFET device fabrication processes) on a Si layer 203 , wherein the quantity and spacing of the fins may depend on fabrication processes and a design of a target IC device. Different sections/regions of the fins 201 may be utilized to provide different functionality in a circuit element such as a transistor.
  • a channel region 205 may be utilized to implement a gate structure for controlling a flow of electrical current between S/D regions 207 and 209 at opposite end of the fins.
  • Each fin may have a substantially same fin width X across the channel and S/D regions.
  • Cross-sectional reference line 2 B- 2 B′ will be used to provide cross-sectional views in below figures and discussions.
  • FIG. 2B illustrates a cross-sectional view of a fin 201 a along the reference line 2 B- 2 B′.
  • a dummy gate structure including a dummy gate 211 (e.g. of polysilicon) over an oxide layer (not shown for illustrative convenience) and with a spacer 213 on each side may be formed on an upper surface 215 of the fin 201 a .
  • a dummy gate structure including a dummy gate 211 (e.g. of polysilicon) over an oxide layer (not shown for illustrative convenience) and with a spacer 213 on each side may be formed on an upper surface 215 of the fin 201 a .
  • semiconductor material 219 may be epitaxially grown on the upper surface 215 and sidewalls 217 of the fin 201 a , at the opposite ends of the fin in the S/D regions 207 and 209 .
  • the semiconductor material 219 may include eSiGe for a p-type device (e.g. PMOS) and doped-silicon for an n-type device (e.g. NMOS).
  • the dummy gate 211 and underlying oxide are removed (by conventional processes) to create a cavity 221 , over the fin 201 a , in a gate area 223 between the spacers 213 .
  • One or more processes may be utilized to thin/remove a layer from each sidewall of the fin in the gate area 223 .
  • FIG. 2E illustrates a top view of the fins 201 including fins 201 a , 201 b , and 201 c .
  • Fin 201 c is illustrated without the semiconductor material 219 for illustrative convenience to further illustrate a narrower/thinned width Yin the gate area 223 of the channel region 205 while the S/D regions 207 and 209 maintain the same prior width X
  • the fins 201 a/ 201 b include the same configuration as fin 201 c , but with the semiconductor material 219 in the S/D regions 207 and 209 .
  • the width Y may be achieved by thinning both sidewalls in the gate area 223 of each fin.
  • an etching process may be used to remove a layer of Si from a surface of the sidewall 217 .
  • the surface of each sidewall may be oxidized and then the oxidized layer may be removed.
  • a target width of a fin in the gate area may be based on criteria to control short-channel effects. For example, a sidewall in the gate area 223 may be thinned/recessed by 2-20% of a width of the fin, or each sidewall in the gate area may be thinned by 0.5-3 nm.
  • a high-k/metal gate 225 may be formed in the cavity 221 , of FIG. 2D , followed by conventional processes (e.g. forming an interlayer dielectric layer over the fins) to complete the fabrication of the IC device.
  • the high-k/metal gate 225 may be formed by depositing an interfacial layer (e.g. an oxide) and a high-k dielectric layer, followed by depositing one or more work function metal layers and filling a remainder of the cavity 221 with metal.
  • the high-k metal gate 225 may be formed across all of the fins.
  • FIG. 2G illustrates a top view of the fins including a high-k/metal gate 225 over the narrower gate area 223 of each fin to improve the SCE while the wider sections of the fins in the S/D regions 207 and 209 support the formation of better (e.g. more volume) S/D epi material 219 .
  • a cross-sectional reference line 2 H- 2 H′ will be used to provide a cross-sectional view in FIG. 2H .
  • FIG. 2H a cross-sectional view along the reference line 2 H- 2 H′ illustrates the fins 201 and the epi growth 219 on each fin.
  • a wider width, X, of the fins 201 can support a larger volume of epi growth 219 in the S/D regions of the fins.
  • the embodiments of the present disclosure can achieve several technical effects including a larger eSiGe volume for the S/D regions concurrently with improved SCE control, thereby improving transistor performance (for example by about 2.7% per nanometer).
  • This approach provides the advantages of independent optimization of the epi volume in the S/D regions on wider fin widths (e.g. providing more drive current), and a thinner fin width in a channel area (e.g. for better SCE).
  • the embodiments enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or other devices utilizing logic or high-voltage technology nodes.
  • the present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use SRAM cells (e.g., liquid crystal display (LCD) drivers, digital processors, etc.)

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin; and forming a high-k/metal gate in the cavity.

Description

TECHNICAL FIELD
The present disclosure relates generally to designing and fabricating integrated circuit (IC) devices. The present disclosure is particularly applicable to forming silicon (Si) fins with improved short-channel performance and source/drain (S/D) formation in FinFET IC devices.
BACKGROUND
With advancements in design and fabrication processes of IC devices, semiconductor manufacturers are able to increase the component density in integrated circuits and deliver smaller scaled IC devices that provide benefits such as improved performance, reduced power consumption, lower cost, etc. for a target product. Fabrication of the components in such devices may require smaller circuit elements, for example, interconnects, conductive lines, contacts, resistors, and the like. In some instances, a reduction in the size of a circuit element may be beneficial in some aspects while limiting in others. For example, in a FinFET device, a width of a Si fin may be based on a required/desired short-channel performance (e.g. better with a narrow width) while the same width may negatively impact formation and characteristics of S/D regions in the Si fin leading to undesired performance issues.
FIG. 1A illustrates a top view of example Si fins 101, in a substrate 103, with a uniform width W across a gate/channel region 105, and S/ D regions 107 and 109. As mentioned, the width W may be optimized to improve short-channel effects (SCE) in the channel region, wherein a narrower width can provide for a better short-channel performance. However, a narrower fin width may hinder formation of an optimum S/D epi width; thus, impacting drive current of the device.
FIG. 1B illustrates a cross-sectional view of the source 107 (or drain 109) regions along a cross-sectional reference line 1B-1B′. In FinFET devices, one or more epitaxy processes may be utilized to increase the size of fin sections in the S/D regions 107/109 where semiconductor material 111 (e.g., Si, silicon-germanium) may be grown/deposited (epi growth) on and around the fins in the S/D regions. The epi growths 111 on the fins may help to reduce electrical resistance in the S/D regions, provide larger areas for electrical contacts to the S/D regions, and provide additional physical support/strength for the fins. However, a volume of an epi growth 111 may be limited by the width of a fin 101.
Therefore, a need exists for methodology enabling formation of a Si fin with different widths and the resulting devices.
SUMMARY
An aspect of the present disclosure is a method for thinning a channel region of a Si fin in a FinFET device.
An aspect of the present disclosure is a FinFET device including Si fins with different widths along each Si fin.
Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
According to the present disclosure some technical effects may be achieved in part by a method including forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin within the cavity; and forming a high-k/metal gate in the cavity.
Another aspect includes forming a plurality of Si fins, parallel to and spaced from each other, in the Si layer; and for each Si fin: in a channel region over the Si fin, forming a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin within the cavity; and forming a high-k/metal gate in the cavity.
One aspect includes thinning by etching. An additional aspect includes oxidizing an outer layer of each sidewall; and removing the oxidized layer.
One aspect includes thinning the sidewalls based on criteria to control short-channel effects. Another aspect includes thinning each sidewall by 2-20% of a width of each Si fin. A further aspect includes thinning each sidewall by 0.5-3 nm.
An additional aspect includes forming the S/D regions by epitaxially growing a layer of silicon-germanium at the opposite ends of each Si fin. One aspect includes forming the S/D regions by epitaxially growing a layer of doped-silicon at the opposite ends of each Si fin.
Another aspect of the present disclosure includes a device including: a Si fin in a Si layer; S/D regions at opposite ends of the Si fin; and a high-k/metal gate in a channel region over the Si fin, wherein the Si fin in the channel region has a narrower width than widths of other regions of the Si fin.
A further aspect includes a plurality of Si fins, parallel to and spaced from each other, in the Si layer; S/D regions at opposite ends of each Si fin; and a high-k/metal gate in a channel region over each Si fin, wherein each Si fin in the channel region has a narrower width than widths of other regions of the Si fin.
An additional aspect includes a width of each Si fin in the channel region being based on short-channel performance criteria.
In another aspect, the width of each Si fin in the channel region is 2-20% narrower than widths of other regions of each Si fin.
In an additional aspect, the width of each Si fin in the channel region is 0.5-3 nm narrower than widths of other regions of each Si fin.
A further aspect includes the S/D regions including epitaxially grown silicon-germanium (eSiGe). Another aspect includes the S/D regions including epitaxially grown doped-silicon.
Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
FIGS. 1A and 1B illustrate a top view of example Si fins and a cross-sectional view of the Si fins with epi growth, respectively; and
FIGS. 2A, 2E, and 2G illustrate top views, and FIGS. 2B through 2D, 2F, and 2H illustrate cross-sectional views, of processes for thinning sections of Si fins, in accordance with an exemplary embodiment.
 DETAILED DESCRIPTION
For the purposes of clarity, in the following description, numerous specific details are set forth to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
The present disclosure addresses the problems of insufficient SCE control or small epitaxial growth area for S/D regions attendant upon Si fins having a constant width. The present disclosure addresses and solves such problems, for instance, by, inter alia, removing a layer from sidewalls of a fin in a gate/channel area based on criteria for controlling SCE.
FIG. 2A illustrates a top view of parallel Si fins 201 formed (e.g. by conventional FinFET device fabrication processes) on a Si layer 203, wherein the quantity and spacing of the fins may depend on fabrication processes and a design of a target IC device. Different sections/regions of the fins 201 may be utilized to provide different functionality in a circuit element such as a transistor. A channel region 205 may be utilized to implement a gate structure for controlling a flow of electrical current between S/ D regions 207 and 209 at opposite end of the fins. Each fin may have a substantially same fin width X across the channel and S/D regions. Cross-sectional reference line 2B-2B′ will be used to provide cross-sectional views in below figures and discussions.
FIG. 2B illustrates a cross-sectional view of a fin 201 a along the reference line 2B-2B′. Although in some of the figures and discussions below only one fin may be referred to and/or illustrated, the processes discussed may be applied to the other fins as well. In the channel region 205, a dummy gate structure including a dummy gate 211 (e.g. of polysilicon) over an oxide layer (not shown for illustrative convenience) and with a spacer 213 on each side may be formed on an upper surface 215 of the fin 201 a. In FIG. 2C, semiconductor material 219 may be epitaxially grown on the upper surface 215 and sidewalls 217 of the fin 201 a, at the opposite ends of the fin in the S/ D regions 207 and 209. The semiconductor material 219 may include eSiGe for a p-type device (e.g. PMOS) and doped-silicon for an n-type device (e.g. NMOS).
As illustrated in FIG. 2D, the dummy gate 211 and underlying oxide are removed (by conventional processes) to create a cavity 221, over the fin 201 a, in a gate area 223 between the spacers 213. One or more processes may be utilized to thin/remove a layer from each sidewall of the fin in the gate area 223.
FIG. 2E, illustrates a top view of the fins 201 including fins 201 a, 201 b, and 201 c. Fin 201 c is illustrated without the semiconductor material 219 for illustrative convenience to further illustrate a narrower/thinned width Yin the gate area 223 of the channel region 205 while the S/ D regions 207 and 209 maintain the same prior width X The fins 201 a/ 201 b include the same configuration as fin 201 c, but with the semiconductor material 219 in the S/ D regions 207 and 209. As illustrated, the width Y may be achieved by thinning both sidewalls in the gate area 223 of each fin. For instance, an etching process may be used to remove a layer of Si from a surface of the sidewall 217. Alternatively, the surface of each sidewall may be oxidized and then the oxidized layer may be removed. A target width of a fin in the gate area may be based on criteria to control short-channel effects. For example, a sidewall in the gate area 223 may be thinned/recessed by 2-20% of a width of the fin, or each sidewall in the gate area may be thinned by 0.5-3 nm.
In FIG. 2F, a high-k/metal gate 225 may be formed in the cavity 221, of FIG. 2D, followed by conventional processes (e.g. forming an interlayer dielectric layer over the fins) to complete the fabrication of the IC device. The high-k/metal gate 225 may be formed by depositing an interfacial layer (e.g. an oxide) and a high-k dielectric layer, followed by depositing one or more work function metal layers and filling a remainder of the cavity 221 with metal. The high-k metal gate 225 may be formed across all of the fins. FIG. 2G illustrates a top view of the fins including a high-k/metal gate 225 over the narrower gate area 223 of each fin to improve the SCE while the wider sections of the fins in the S/ D regions 207 and 209 support the formation of better (e.g. more volume) S/D epi material 219. A cross-sectional reference line 2H-2H′ will be used to provide a cross-sectional view in FIG. 2H.
In FIG. 2H, a cross-sectional view along the reference line 2H-2H′ illustrates the fins 201 and the epi growth 219 on each fin. As noted, a wider width, X, of the fins 201 can support a larger volume of epi growth 219 in the S/D regions of the fins.
The embodiments of the present disclosure can achieve several technical effects including a larger eSiGe volume for the S/D regions concurrently with improved SCE control, thereby improving transistor performance (for example by about 2.7% per nanometer). This approach provides the advantages of independent optimization of the epi volume in the S/D regions on wider fin widths (e.g. providing more drive current), and a thinner fin width in a channel area (e.g. for better SCE). Furthermore, the embodiments enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or other devices utilizing logic or high-voltage technology nodes. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use SRAM cells (e.g., liquid crystal display (LCD) drivers, digital processors, etc.)
In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.

Claims (8)

What is claimed is:
1. A method comprising:
forming a plurality of Si fins, parallel to and spaced from each other, in a Si layer;
forming a channel region over each Si fin including a dummy gate with a spacer on each side;
forming source/drain regions (S/D) by epitaxially growing a layer of a combination of silicon-germanium and doped-silicon on each side of the dummy gate, each Si fin having a substantially same fin width X across the channel and the S/D regions;
removing the dummy gate, forming a cavity;
thinning sidewalls of each Si fin within the cavity by oxidizing an outer layer of each sidewall and etching the oxidized layer, such that a width of each Si fin in the channel region is less than X, the width of each Si fin being measured in a direction perpendicular to a length direction of each Si fin and in a plane parallel to a top surface of each Si fin; and
forming a high-k/metal gate in the cavity.
2. The method according to claim 1, further comprising:
for each Si fin:
in a channel region over the Si fin, forming a dummy gate with a spacer on each side;
forming S/D regions at opposite ends of the Si fin;
removing the dummy gate, forming a cavity;
thinning sidewalls of the Si fin within the cavity; and
forming a high-k/metal gate in the cavity.
3. The method according to claim 2, comprising:
thinning the sidewalls based on criteria to control short-channel effects.
4. The method according to claim 2, comprising:
thinning each sidewall by 2-20% of a width of each Si fin.
5. The method according to claim 2, comprising:
thinning each sidewall by 0.5-3 nm.
6. A method comprising:
forming a plurality of silicon (Si) fins, parallel to and spaced from each other, in a Si layer; and
for each fin:
in a channel region over the Si fin, forming a dummy gate with a spacer on each side;
forming source/drain regions (S/D) by epitaxially growing a layer of a combination of silicon-germanium and doped-silicon on each side of the dummy gate, the Si fin having a substantially same fin width X across the channel and the S/D regions;
removing the dummy gate, forming a cavity;
thinning sidewalls of the Si fin within the cavity by oxidizing an outer layer of each sidewall and etching the oxidized layer, such that a width of Si fin in the channel region is less than X, the width of the Si fin being measured in a direction perpendicular to a length direction of the Si fin and in a plane parallel to a top surface of the Si fin, by etching or by oxidizing an outer layer of each sidewall and removing the oxidized layer, the thinning based, at least in part, on criteria to control short-channel effects; and
forming a high-k/metal gate in the cavity.
7. The method according to claim 6, comprising:
thinning a sidewall of each Si fin within the cavity by 2-20% of a width of the Si fin.
8. The method according to claim 6, comprising:
thinning a sidewall of each Si fin within the cavity by 0.5-3 nm.
US15/079,142 2016-03-24 2016-03-24 Methods for fin thinning providing improved SCE and S/D EPI growth Expired - Fee Related US10056486B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/079,142 US10056486B2 (en) 2016-03-24 2016-03-24 Methods for fin thinning providing improved SCE and S/D EPI growth

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/079,142 US10056486B2 (en) 2016-03-24 2016-03-24 Methods for fin thinning providing improved SCE and S/D EPI growth

Publications (2)

Publication Number Publication Date
US20170278965A1 US20170278965A1 (en) 2017-09-28
US10056486B2 true US10056486B2 (en) 2018-08-21

Family

ID=59897312

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/079,142 Expired - Fee Related US10056486B2 (en) 2016-03-24 2016-03-24 Methods for fin thinning providing improved SCE and S/D EPI growth

Country Status (1)

Country Link
US (1) US10056486B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10930768B2 (en) 2018-10-18 2021-02-23 Samsung Electronics Co., Ltd. Low current leakage finFET and methods of making the same
US10957786B2 (en) 2018-10-18 2021-03-23 Samsung Electronics Co., Ltd. FinFET with reduced extension resistance and methods of manufacturing the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627378B2 (en) * 2015-06-30 2017-04-18 International Business Machines Corporation Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding
CN108470766A (en) * 2018-03-14 2018-08-31 上海华力集成电路制造有限公司 Full cladding gridistor and its manufacturing method
WO2022016463A1 (en) * 2020-07-23 2022-01-27 华为技术有限公司 Fin field effect transistor and preparation method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
US20050051825A1 (en) * 2003-09-09 2005-03-10 Makoto Fujiwara Semiconductor device and manufacturing method thereof
US7915693B2 (en) * 2007-07-27 2011-03-29 Kabushiki Kaisha Toshiba Semiconductor device with fin and silicide structure
US20140151761A1 (en) * 2012-12-04 2014-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-Like Field Effect Transistor (FinFET) Channel Profile Engineering Method And Associated Device
US9112032B1 (en) * 2014-06-16 2015-08-18 Globalfoundries Inc. Methods of forming replacement gate structures on semiconductor devices
US9178067B1 (en) * 2014-04-25 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
US20050051825A1 (en) * 2003-09-09 2005-03-10 Makoto Fujiwara Semiconductor device and manufacturing method thereof
US7915693B2 (en) * 2007-07-27 2011-03-29 Kabushiki Kaisha Toshiba Semiconductor device with fin and silicide structure
US20140151761A1 (en) * 2012-12-04 2014-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-Like Field Effect Transistor (FinFET) Channel Profile Engineering Method And Associated Device
US9178067B1 (en) * 2014-04-25 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET device
US9112032B1 (en) * 2014-06-16 2015-08-18 Globalfoundries Inc. Methods of forming replacement gate structures on semiconductor devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10930768B2 (en) 2018-10-18 2021-02-23 Samsung Electronics Co., Ltd. Low current leakage finFET and methods of making the same
US10957786B2 (en) 2018-10-18 2021-03-23 Samsung Electronics Co., Ltd. FinFET with reduced extension resistance and methods of manufacturing the same

Also Published As

Publication number Publication date
US20170278965A1 (en) 2017-09-28

Similar Documents

Publication Publication Date Title
US10510853B2 (en) FinFET with two fins on STI
US20210210514A1 (en) Fins for metal oxide semiconductor device structures
US10170592B2 (en) Integrated circuit structure with substrate isolation and un-doped channel
US9953882B2 (en) Method for forming nanowires including multiple integrated devices with alternate channel materials
US8785285B2 (en) Semiconductor devices and methods of manufacture thereof
US8673718B2 (en) Methods of forming FinFET devices with alternative channel materials
US10103264B2 (en) Channel strain control for nonplanar compound semiconductor devices
US10056486B2 (en) Methods for fin thinning providing improved SCE and S/D EPI growth
US9306067B2 (en) Nonplanar device and strain-generating channel dielectric
US6709982B1 (en) Double spacer FinFET formation
US8716156B1 (en) Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process
US8896072B2 (en) Channel surface technique for fabrication of FinFET devices
US9293324B2 (en) Methods of forming semiconductor devices including an electrically-decoupled fin
US9461111B2 (en) Double/multiple fin structure for FinFET devices
KR20180041659A (en) Method for Vertical Gate-Last Process in the Fabrication of Vertical Nanowire MOSFETs
US9911601B2 (en) Epitaxial silicon germanium fin formation using sacrificial silicon fin templates
US9324868B2 (en) Epitaxial growth of silicon for FinFETS with non-rectangular cross-sections
US20080197384A1 (en) Field Effect Transistor Arrangement
US9373721B2 (en) Methods of forming a non-planar ultra-thin body semiconductor device and the resulting devices
JP2022552417A (en) Horizontal gate all-around (hGAA) nanowire and nanoslab transistors
US20180315832A1 (en) Method for late differential soi thinning for improved fdsoi performance and hci optimization
US9379186B1 (en) Fet structure for minimum size length/width devices for performance boost and mismatch reduction
CN104766867A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PANDEY, SHESH MANI;ZHAO, PEI;HU, ZHENYU;REEL/FRAME:038091/0054

Effective date: 20160317

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE

Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001

Effective date: 20181127

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001

Effective date: 20201022

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001

Effective date: 20201117

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001

Effective date: 20201117

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20220821