WO2022016463A1

WO2022016463A1 - Fin field effect transistor and preparation method

Info

Publication number: WO2022016463A1
Application number: PCT/CN2020/103855
Authority: WO
Inventors: 许俊豪; 贝尼斯坦特·弗朗西斯·莱昂内尔; 侯朝昭
Original assignee: 华为技术有限公司
Priority date: 2020-07-23
Filing date: 2020-07-23
Publication date: 2022-01-27
Also published as: CN115699270A

Abstract

Embodiments of the present application provide a fin field effect transistor and a preparation method, the fin field effect transistor comprising: a substrate, and an active region and a channel region which are formed on the substrate; and a fin formed on the substrate and passing through the active region and the channel region. The width of the fin in the channel region is less than the width of the fin in the active region. Adoption of the fin field effect transistor structure provided in the present application can improve the reliability of the fin field effect transistor while ensuring the switching speed.

Description

Fin-type field effect transistor and fabrication method

technical field

The embodiments of the present application relate to the technical field of semiconductor devices, and in particular, to a structure and a manufacturing method of a fin transistor.

Background technique

With the development of electronic devices toward the direction of low power consumption and high operating speed, the requirements for the cornerstone of electronic devices - field effect transistors are getting higher and higher. Field effect transistors began to gradually transition from planar field effect transistors to three-dimensional field effect transistors. Among them, Fin Field-Effect Transistor (FinFET, Fin Field-Effect Transistor), which is a representative of three-dimensional field effect transistors, has attracted more and more attention. FinFET adopts a multi-gate structure, which can improve the gate control ability and suppress the short-channel effect.

In the current FinFET structure, in order to stabilize the performance of the FinFET, the ratio between the length of the conductive channel of the FinFET (ie the gate length) and the width of the fin needs to be not lower than a certain critical value (eg 2.5). Usually, the length of the conductive channel is inversely correlated with the switching speed of the field effect transistor. In order to further improve the switching speed of FinFET, the length of the conductive channel is usually reduced. In this way, the thickness of the fin in the FinFET needs to be further thinned. Too thin fins will lead to problems such as increased source/drain expansion resistance and reduced source/drain effective stress. In addition, too thin fins are prone to breakage during production, reducing the production yield of FinFETs. Therefore, how to improve the reliability of the FinFET while ensuring the switching speed has become a problem to be solved.

SUMMARY OF THE INVENTION

The fin field effect transistor and the preparation method provided by the present application can improve the reliability of the short channel fin field effect transistor while ensuring the switching speed.

To achieve the above object, the application adopts the following technical solutions:

In a first aspect, embodiments of the present application provide a fin field effect transistor, the fin field effect transistor comprising: a substrate on which an active region and a channel region are formed; a fin formed on the on the substrate, and runs through the active region and the channel region; wherein, the width of the portion of the fin located in the channel region is smaller than the width of the portion of the fin located in the active region .

In this embodiment, by setting different widths of different parts of the fins, that is, reducing the width of the fins in the channel region, and keeping the width of the active regions of the fins unchanged, the short-channel FinFET structure can make conductive The ratio between the channel and the portion of the fin located in the conductive channel region is not lower than a certain critical value, and the width of the portion of the fin located in the active region can not be affected by the above ratio; in addition, the active region can also be maintained. The hardness of the fin portion of the region reduces the spreading resistance, thereby improving the reliability of the FinFET.

Based on the first aspect, in a possible implementation manner, the ratio of the width of the portion of the fin located in the channel region to the width of the portion of the fin located in the active region is 2:3.

In a specific implementation, the length of the channel region of the short-channel device is usually 10 nm-14 nm, and the width of the fin located in the active region is usually 7 nm. In order to stabilize the performance of the FinFET, it is usually necessary to set the ratio of the length of the channel region to the width of the portion of the fin located in the channel region to be 2.5:1. In order to satisfy this condition, satisfy the channel length in the range of 10nm-14nm, and facilitate process production, the width of the part of the fin in the channel region and the width of the part of the fin in the active region can be The width ratio is 2:3.

Based on the first aspect, in a possible implementation manner, the width of the portion of the fin located in the channel region is 4 nm, and the width of the portion of the fin located in the active region is 7 nm.

Based on the first aspect, in a possible implementation manner, the fin field effect transistor further includes a plurality of spacer structures; each spacer structure in the plurality of spacer structures is formed in the active region and between the channel region; wherein, along the width direction of the fin, each sidewall structure of the plurality of sidewall structures spans the fin.

Based on the first aspect, in a possible implementation manner, each of the spacer structures in the plurality of spacer structures includes multiple layers; wherein a side close to the channel region is a silicon oxide layer, and a side away from the spacer structure is a silicon oxide layer. One side of the channel region is a silicon nitride layer.

Based on the first aspect, in a possible implementation manner, the fin field effect transistor includes a plurality of the fins; and the plurality of the fins are arranged in sequence along the width direction of the fins at intervals.

Based on the first aspect, in a possible implementation manner, the active region includes a semiconductor structure; and the semiconductor destructure is formed on the fin on a side away from the substrate.

Based on the first aspect, in a possible implementation manner, a plurality of semiconductor structures are sequentially and spaced apart along the width direction of the fin; the outer surface of each semiconductor structure in the plurality of semiconductor structures is wrapped with a metal material .

Typically, a contact metal is deposited on the side of the semiconductor structure away from the substrate, and the contact metal is used to lead out the source and drain during packaging. By wrapping the metal material on the outer surface of the semiconductor structure, the contact resistance between the semiconductor structure and the contact metal can be reduced, so that the driving current of the FinFET can be improved.

Based on the first aspect, in a possible implementation manner, an insulating structure is provided between every two semiconductor structures in the plurality of semiconductor structures.

Based on the first aspect, in a possible implementation manner, the channel region includes a gate structure; the gate structure covers a portion of the fin in the channel region.

Based on the first aspect, in a possible implementation manner, the gate structure includes a gate dielectric layer and a gate metal layer; wherein, the gate dielectric layer is a high dielectric constant dielectric layer.

In a second aspect, an embodiment of the present application provides an electronic device including the fin field effect transistor described in the first aspect.

Specifically, the electronic device may be an unpackaged bare chip.

The electronic device may also be an electronic device, and the FinFET shown in the embodiments of the present application may be packaged in a tube case. The package may include, but is not limited to, a plastic package, a metal package (eg, a gold shell, a nickel shell), etc., and the source, drain and gate of the FinFET are drawn out from the outer surface of the package.

In addition, the electronic device may also be an integrated circuit product (such as a system-on-chip), wherein, in addition to the FinFET described in the embodiments of the present application, the integrated circuit product may also include other integrated circuits, so that the The shown FinFET cooperates with other integrated circuits to realize various circuit functions.

In a third aspect, an embodiment of the present application provides a method for fabricating a fin field effect transistor, the fabrication method comprising: providing a substrate, forming a fin on the substrate; forming an active region on the substrate and the channel region, the fin penetrates the active region and the channel region; the part of the fin located in the channel region is etched, so that the fin is located in the channel region The width of the portion is smaller than the width of the portion located in the active region.

Based on the third aspect, in a possible implementation manner, the forming the active region and the channel region on the substrate includes: depositing a first insulating material on the substrate and the fin, and etching etching the first insulating material to form a plurality of spacer structures separated from each other, each of the spacer structures in the plurality of spacer structures spans the fins along the width direction of the fins, to dividing the fin into a plurality of parts; growing semiconductor material on at least two non-adjacent parts of the plurality of parts of the fin respectively to form an active region; part of the fin where the semiconductor structure is not grown A channel region is formed.

Based on the third aspect, in a possible implementation manner, the step of growing a semiconductor material on at least two non-adjacent portions of the plurality of portions of the fin to form an active region includes: on the fin The sidewalls of at least two non-adjacent portions of the fins are wrapped with a second insulating material; and the portion of the fins wrapped with the second insulating material is etched to reduce the wrapping of the fins with the second insulating material. The height of the portion of the second insulating material along the thickness direction of the substrate; the semiconductor structure is grown in the space region defined by the second insulating material and on the portion of the fin that wraps the second insulating material, to form an active region.

Based on the third aspect, in a possible implementation manner, the method further includes: etching the second insulating material to expose the outer surface of the semiconductor structure; and wrapping a metal material on the outer surface of the semiconductor structure.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. , for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative labor.

1 is a schematic structural diagram of a fin in a fin field effect transistor provided by an embodiment of the present application;

2A is a cross-sectional view along AA' of the fin field effect transistor shown in FIG. 1 provided by an embodiment of the present application;

2B is a cross-sectional view of the fin field effect transistor shown in FIG. 1 along BB' provided by an embodiment of the present application;

3A is a schematic structural diagram of a fin field effect transistor in a conventional technology;

Figure 3B is a cross-sectional view along CC' and DD' of the fin field effect transistor shown in Figure 3A;

4 is a schematic structural diagram of a semiconductor structure deposited in a fin field effect transistor provided by an embodiment of the present application;

5 is a schematic diagram of an overall structure of a fin field effect transistor provided by an embodiment of the present application;

6 is another structural schematic diagram of the semiconductor structure deposited in the fin field effect transistor provided by the embodiment of the present application;

7 is a schematic structural diagram of the fin field effect transistor shown in FIG. 6 along EE' provided by an embodiment of the present application;

FIG. 8 is another schematic diagram of the overall structure of the fin field effect transistor provided by the embodiment of the present application;

9 is a flowchart of a method for fabricating the fin field effect transistor shown in FIG. 5 provided by an embodiment of the present application;

10A-FIG. 10E are schematic diagrams of each structure in the preparation process of the fin field effect transistor shown in FIG. 5;

11 is a flowchart of a method for fabricating the fin field effect transistor shown in FIG. 8 provided by an embodiment of the present application;

FIGS. 12A-12E are schematic diagrams of each structure during the fabrication process of the fin field effect transistor shown in FIG. 8 .

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

References herein to "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Likewise, words such as "a" or "an" do not denote a quantitative limitation, but rather denote the presence of at least one.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate an example, illustration or illustration. Any embodiments or designs described in the embodiments of the present application as "exemplary" or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present the related concepts in a specific manner. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "plurality" refers to two or more. For example, a plurality of fins refers to two or more fins.

Please refer to FIG. 1 , which is a schematic structural diagram of a fin field effect transistor provided by an embodiment of the present application.

In FIG. 1 , FinFET 100 includes substrate 10 and fins 11 .

The fins 11 and the substrate 10 are of the same material. In a specific process, the substrate may be etched to form the fins 11 . The semiconductor materials commonly used for the substrate 10 and the fins 11 may specifically include but are not limited to: silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), silicon carbide (SiC) ), indium phosphide (InP), zinc selenide (ZnSe), or other Group VI, III-V or II-VI semiconductor materials.

In the FinFET 100 as shown in FIG. 1 , one or more fins 11 may be included. The fins 11 extend along the first direction X shown in FIG. 1 , therefore, the first direction X can also be regarded as the length direction of the fins 11 , and the second direction Y perpendicular to the first direction X can be regarded as the width direction of the fins 11 . When the FinFET includes a plurality of fins, the plurality of fins are sequentially arranged along the second direction Y shown in FIG. 1 . The figure schematically shows a situation where the FinFET includes three fins 11 . The plurality of fins protrude from a side close to the substrate 10 to a side away from the substrate 10 . It can be understood that, the embodiment of the present application does not limit the number of fins, which may include more or less fins.

In FIG. 1, along the first direction X, the FinFET 100 is divided into a plurality of regions by a plurality of spacer structures 13, and the plurality of regions include a first active region A1, a second active region A2, and the first active region The channel region C between the region A1 and the second active region A2. The first active region A1 and the second active region A2 may be regions where a source electrode or a drain electrode is formed, respectively. The channel region C is used to form the gate. Similarly, the fin 11 is also divided into a plurality of parts by the spacers 13 , including the first part 110 in the first active region A1 and the second active region A2 , and the second part in the channel region C 111. The second portion 111 is in the channel region C of the FinFET 100 .

In this embodiment, the first active region A1 and the second active region A2 may be understood as regions on the substrate 10 where the semiconductor structure 14 shown in FIG. 4 is formed, and the semiconductor structure 14 has dopants, In addition, the first active region A1 and the second active region A2 are usually formed with contact metal 16 such as shown in FIG. 5 , and the contact metal 16 is used to lead out the source or drain . The materials, shapes, etc. of the semiconductor structure 14 and the contact metal 16 may refer to the specific description below.

It should be noted that, in the specific process, the spacer structure 13 is formed by directly depositing the above-mentioned insulating material on the fins 11 and the insulating layer 12 . The sidewall structure 13 spanning the fins 11 wraps the part of the fins it spans. From the outside, a plurality of sidewall structures 13 separate the fins into the first active area A1 and the second active area A1. The first portion 110 of the active region A2, and the second portion 111 of the channel region C. Wherein, for the materials of the side wall structure 13, reference may be made to the specific description below.

In the embodiment of the present invention, the width of the first portion 110 of the fin 11 is different from the width of the second portion 111 . Wherein, the width of the second portion 111 of the fin 11 is smaller than the width of the first portion 110 . As shown in FIGS. 2A and 2B , FIG. 2A is a cross-sectional view of the FinFET 100 taken along AA' shown in FIG. 1 , and FIG. 2B is a cross-sectional view of the FinFET 100 taken along BB' shown in FIG. 1 . As can be seen from FIGS. 2A and 2B , the width of the second portion 111 of the fin 11 is smaller than the width of the first portion 110 .

It should be noted that, in an actual product, each first portion 110 of the fin 11 is grown with a semiconductor structure forming a source electrode and a drain electrode (the semiconductor structure 14 shown in FIG. 4 ). In order to increase the width of the fin 11 For good illustration, the semiconductor structure grown on the fin is not shown in FIG. 1 .

Generally, in order to reduce the switching speed of the FinFET, that is, the threshold voltage of the FinFET, it is necessary to shorten the length of the conductive channel, that is, to shorten the distance between the first active region A1 and the second active region A2, or to shorten the The length of the channel region C in the first direction X. In addition, in order to improve the performance of the FinFET, it is necessary to make the ratio between the length and the width of the second portion 111 of the fin in the channel region C not lower than a certain critical value. As such, when the conductive channel is shortened, the width of the fin 11 needs to be reduced. In the conventional FinFET structure, along the second direction Y, each part of the fin 11 is generally set to have the same width. As shown in FIG. 3A, FIG. 3A schematically shows a schematic diagram of a fin structure in a conventional FinFET structure, and FIG. 3B is a cross-sectional view of the FinFET taken along CC' and DD' shown in FIG. 3A. In a specific process practice, it is usually necessary to grow a semiconductor structure on the first part 110 of the fin 11, and to form a source electrode and a drain electrode by doping phosphorus ions or boron ions. Fins that are too thin usually bring more problems, such as increasing the spread resistance of the first active area A1 and the second active area A2, causing the variation difference of the FinFET to increase, the first active area A1 and the second active area A2. Problems such as stress reduction in the active region A2. In addition, during the production process, the height of the fins 11 along the third direction Z increases continuously, which makes the ratio between the height of the fins 11 along the third direction Z and the width along the second direction Y become larger and larger. , resulting in the fin 11 being easily broken during the production process of the FinFET, which seriously reduces the production yield of the FinFET.

In this embodiment, by setting different widths of different parts of the fins 11, and by reducing the width of the second parts 111 of the fins 11 located in the conductive channel region C, the first active region A1 of the fins 11 is kept in the first active region A1. and the width of the first portion 110 of the second active region A2 remains unchanged, so that in the short-channel FinFET structure, the ratio of the length of the conductive channel to the width of the fin portion located in the conductive channel region is not lower than a certain At the same time, the fin parts in the first active area A1 and the second active area A2 can maintain sufficient width, so as to maintain the fin 11 part of the first active area A1 and the second active area A2 strength, reduce the expansion resistance, and improve the reliability of the FinFET.

In a possible implementation of this embodiment, when the length of the channel region C along the first direction X is 10 nm, in order to ensure that the ratio of the length of the channel region C to the width of the second portion 111 of the fin 11 is approximately 2.5:1, at this time, the width of the second part 111 of the fin 11 can be set to 4 nm; when the width of the first part 110 of the fin 11 is 7 nm, along the second direction Y, the width of the second part 111 of the fin 11 is 7 nm. The ratio between the width and the width of the first portion 110 may be 4:7. When the length of the channel region C along the first direction X is 14 nm, in order to ensure that the ratio of the length of the channel region C to the width of the second portion 111 of the fin 11 is approximately 2.5:1, the The width of the second part 111 is set to 5 nm; when the width of the first part 110 of the fin 11 is 7 nm, along the second direction Y, the ratio between the width of the second part 111 of the fin 11 and the width of the first part 110 can be 5:7. In an actual product, the width of the first portion 110 of the fin 11 is usually 7 nm. In order to satisfy the length of the channel region C in the range of 10nm-14nm, and to accurately control the etching process of the fins 11, the length of the channel region C is in the range of 10nm-14nm, and the fins 11 along the first part 110 When the width of the fin 11 is 7 nm, the ratio between the width of the second portion 111 of the fin 11 and the width of the first portion 110 can be set to 2:3. In addition, the ratio between the width of the second part 111 of the fin 11 and the width of the first part 110 may also be 4:7, and the ratio between the width of the second part 111 of the fin 11 and the width of the first part 110 may also be 5:7 etc. It should be noted that the widths of the first portion and the second portion of the fin 11 may be determined according to the width of the conductive channel region, which is not specifically limited herein. In some other scenarios, for example, when the length of the channel region C is 10 nm and the width of the first part 110 of the fin 11 is 5 nm, the ratio between the width of the second part 111 of the fin 11 and the width of the first part 110 is also Can be 4:5.

Continuing to refer to FIG. 1 , the FinFET 100 shown in FIG. 1 further includes an insulating layer 12 , and the material of the insulating layer 12 includes but is not limited to: silicon oxide, sapphire, or any material of their combination. The thickness of the insulating layer 12 along the third direction Z is less than or equal to the height of the fins 11 protruding from the substrate 10 . The insulating layer 12 isolates the plurality of fins.

In addition, in FIG. 1 , the spacer structure 13 in the FinFET 100 is deposited on the above-mentioned insulating layer 12 and the fins 11 , and the spacer structure 13 spans the fins 11 along the second direction Y. As shown in FIG. As can be seen from FIG. 1 , in the third direction Z, the height of the sidewall structures 13 is greater than the height of the protrusions of the fins 11 . The material for forming the spacer structure 13 may include, but is not limited to, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or any combination thereof. In addition, the sidewall structure 13 may be, for example, a structure formed of multiple layers of materials. For example, the side close to the channel region is a silicon oxide layer, and the side away from the channel region is a silicon nitride layer.

In this embodiment, the FinFET 100 further includes a gate structure 15 , and the gate structure 15 is formed in the channel region C between the first active region A1 and the second active region A2 , as shown in FIG. 4 . The gate structure 15 wraps the second portion of the fin 11 in the channel region. The wrapping here means that among the surfaces of the fin extending along the first direction X, except the surface contacting the substrate, the other surfaces are covered by the gate material. Thus, the FinFET is made to form a multi-gate structure. The multi-gate structure here means that one gate structure is formed between every two fins 11 . Specifically, the gate structure 15 may include a gate dielectric layer and a gate metal layer. The gate dielectric layer is deposited on the insulating layer 12 and the fins 11 in the conductive channel region. The gate dielectric layer can be a high dielectric constant (HK, High-K) dielectric layer, and its specific materials can include but are not limited to: lanthanum oxide (LaO), aluminum oxide (ALO), zirconium oxide (ZrO), Titanium oxide (TiO), silicon oxide (SiO) and other materials. A gate metal layer is deposited over the gate dielectric layer, and the gate metal layer may include an N-gate metal layer forming an N-type field effect transistor, or a P-gate metal layer forming a P-type field effect transistor. Wherein, the material of the N gate metal layer may include but not limited to: titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), Manganese (Mn), etc.; the material of the P gate metal layer may include, but is not limited to: Titanium Nitride (TiN), Tantalum Nitride (TaN), Ruthenium (Ru), Molybdenum (Mo), Aluminum (Al), Tungsten Nitride (WN) )Wait. The top surface of the gate metal layer is flush with the top surface of the spacer structure 13 , as shown in FIG. 5 .

In this embodiment, the source electrode and the drain electrode may be formed by epitaxially growing a semiconductor material on the first portion 110 of the fin 11 . The semiconductor material may be, for example, a single-element semiconductor material such as germanium (Ge) or silicon (Si), a mixed semiconductor material of germanium and silicon, or gallium arsenide (GaAs), gallium aluminum arsenide (AlGaAs) The compound semiconductor material can also be a semiconductor alloy such as silicon germanium (SiGe) and gallium arsenide phosphide (GaAsP). During epitaxial growth of semiconductor materials, the source and drain electrodes can be formed by in-situ doping. For example, boron ions can be doped in situ to form P-type FinFETs, or phosphorus or arsenic ions can be doped in situ to form N-type FinFETs. The semiconductor structure 14 formed by the semiconductor material grown on the first portion 110 of the fin 11 is shown in FIG. 4 . It should be noted that FIG. 4 only illustrates the semiconductor structure 14 formed in the first active area A1, and the semiconductor structure formed in the second active area A2 may be the same as the semiconductor structure formed in the first active area A1 shown in FIG. 4 . The shape and material of the semiconductor structure are the same and are not shown in FIG. 4 .

In addition, the FinFET 100 further includes a first insulating structure 17 deposited around the epitaxially grown semiconductor structure 14 to protect the semiconductor structure 14 . The material of the first insulating structure 17 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., wherein, along the third direction Z, the bottom surface of the first insulating structure 17 is in contact with the insulating layer 12, and the top surface is in contact with the insulating layer 12. The gate structure 15 is flush, as shown in FIG. 5 .

Further, FinFET 100 also includes contact metal 16 deposited over epitaxially grown semiconductor structure 14 . The contact metal 16 is used to extract the source and drain electrodes. The material contacting the metal may include, but is not limited to, metal copper, nickel, aluminum or an alloy formed by any combination thereof, for example. As shown in FIG. 5 , the bottom of the contact metal 16 is in contact with the semiconductor structure 14 (eg, wraps the top surface of the semiconductor structure 14 ), and the top surface of the contact metal 16 is flush with the gate structure 15 and the second insulating layer 17 .

In the FinFET structures shown in FIGS. 4 and 5 , the epitaxially grown semiconductor structure 14 is an irregular geometry, such as a polygon as shown in FIG. 4 , or a prism. In addition, the grown semiconductor structures 14 are all connected together.

Please continue to refer to FIG. 6 to FIG. 8 , which are schematic structural diagrams of still another FinFET provided by an embodiment of the present application. In the FinFET structure shown in FIGS. 6-8 , a plurality of mutually insulated semiconductor structures 14 may be included, wherein each semiconductor structure is a regular geometric body, such as a rectangular parallelepiped shown in FIG. 6 , and in some other implementations , can also be a cube, etc. At this time, the semiconductor structure 14 may be formed by using an insulating layer to define the position and shape of semiconductor growth.

In addition, in the FinFET structure shown in FIG. 6 , the surfaces of the individual semiconductor structures 14 are also wrapped with metal materials 141 respectively. For example, the metal material wrapping each independent semiconductor structure 14 may include, but not limited to, copper, nickel, aluminum or an alloy formed by any combination thereof, and the like. The meaning of wrapping here is that, except for the side in contact with the insulating layer 12 , the side in contact with the sidewall structure 13 , and the side opposite to the side in contact with the sidewall structure 13 , the other sides of each independent semiconductor structure are covered with metal materials. pack. As shown in FIG. 7, FIG. 7 is a cross-sectional view of the FinFET shown in FIG. 6 along EE'. By wrapping the metal material on the outer surface of the semiconductor structure 14, the contact resistance between the semiconductor structure 14 and the contact metal 16 as shown in FIG. 8 can be reduced, so that the driving current of the FinFET can be increased.

Further, in the FinFET structure shown in FIG. 8 , along the second direction Y, a second insulating structure 18 is also filled between every two semiconductor structures 14 . Each second insulating structure 18 is deposited on the insulating layer 12 . In each of the formed second insulating structures 18 , along the third direction Z, the lower surface thereof is in contact with the insulating layer 12 , and the top surface may be flush with the top surface of the semiconductor structure 14 , as shown in FIG. 8 . It should be noted that, in the process of forming the second insulating structure 18 as shown in FIG. 8 , the insulating material is directly deposited on the semiconductor structure 14 and the insulating layer 12 , and then the insulating material on the top of the semiconductor structure 14 is etched. At this time, along the second direction Y, the gap between the first insulating structure 17 and the semiconductor structure 16 is also filled with the above-mentioned second insulating structure 18 . In another possible implementation manner, when there is no gap between the first insulating structure 17 and the semiconductor structure 14 along the second direction Y, the second insulating structure 17 and the semiconductor structure 16 may not be provided between the first insulating structure 17 and the semiconductor structure 16 . Insulating structure 18 .

Please continue to refer to FIG. 8 . The FinFET shown in FIG. 8 further includes a substrate 10 , a fin 11 , a spacer structure 13 , an insulating layer 12 , a gate structure 14 , a contact metal 16 and a first insulating structure 17 . The structures and materials of the substrate 10 , the fins 11 , the spacer structure 13 , the insulating layer 12 , the gate structure 14 , the contact metal 16 and the first insulating structure 17 are the same as those of the FinFET shown in FIG. 1 , FIG. 4 and FIG. 5 . The structure and materials are the same. For details, refer to the related descriptions of the FinFET structures shown in FIG. 1 , FIG. 4 and FIG. 5 , which will not be repeated here.

The embodiments of the present application also include an electronic device, which includes the FinFET shown in the above-mentioned embodiments. Specifically, the electronic device may be an unpackaged bare chip or an electronic device, and the FinFET shown in the embodiments of the present application may be packaged in a tube case. The package may include, but is not limited to, a plastic package, a metal package (eg, a gold shell, a nickel shell), etc., and the source, drain and gate of the FinFET are drawn out from the outer surface of the package. In addition, the electronic device may also be an integrated circuit product (such as a system-on-chip), wherein, in addition to the FinFET described in the embodiments of the present application, the integrated circuit product may also include other integrated circuits, so that the The shown FinFET cooperates with other integrated circuits to realize various circuit functions.

Based on the above structures of each FinFET, an embodiment of the present application further provides a method for fabricating a FinFET, and the structure of a FinFET fabricated by the method for fabricating a FinFET is shown in FIG. 5 . For the process flow of manufacturing the FinFET, reference may be made to the flow 900 shown in FIG. 9 . The process flow 900 includes the following steps:

In step 901, a substrate is provided, and a fin structure is formed on the substrate.

The substrate may be a semiconductor material, and the semiconductor material may specifically include but not be limited to: silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), silicon carbide (SiC), Indium Phosphide (InP), Zinc Selenide (ZnSe) or other Group VI, III-V or II-VI semiconductor materials.

In a specific process, a patterned mask layer may be formed on the substrate 10, the substrate 10 is etched by using the patterned mask layer as a mask, and the unetched portion forms a plurality of fins 11 , the etched part forms a plurality of trenches. Specifically, a groove is formed between every two fins 11 . As shown in Figure 10A. Specifically, various etching methods such as dry etching or wet etching can be used to etch the above-mentioned substrate 10 to form a plurality of fins 11 and trenches.

Then, an insulating material is deposited in the trench between every two fins 11 to form an insulating layer 12 , so that every two fins 11 are insulated from each other. As shown in Figure 10B.

Step 902, forming a dummy gate structure and a spacer structure on the fin and the insulating layer.

Specifically, a semiconductor material such as polysilicon may be deposited in the middle of the fin 11 to form the dummy gate structure 151 . It should be noted that, since the polysilicon material needs to be etched later to deposit a metal gate, the gate formed by the deposited polysilicon material is referred to as a dummy gate here.

Then, the spacer structures 13 are formed on the sidewalls of the dummy gate structures 151 . The material of the spacer structure 13 may include, but is not limited to, silicon nitride, silicon carbide, silicon oxynitride, and the like. Wherein, the spacer structure 13 can be completed by dielectric deposition and etching processes. The spacer structure 13 may include two parts spanning a plurality of fins, one part is used to block the first active region A1 and the dummy gate structure 151 forming the source electrode, and the other part is used to block the second part forming the drain electrode The source region A2 and the dummy gate structure 151 . At this time, the second part 111 of the fin 11 is wrapped by the dummy gate structure, and the first part 110 of the fin 11 is exposed to the outside. As shown in Figure 10C.

Step 903, growing a semiconductor structure on the exposed portion of the fin.

The semiconductor structure 14 is formed on the exposed first portion 110 of the fin, and the formed semiconductor structure is shown in FIG. 4 .

Specifically, the exposed first portion 110 of the fin may be etched back first, so as to reduce the height of the first portion 110 of the fin along the third direction Z. As shown in FIG.

Then, semiconductor material is grown on the exposed portion of the fin structure by a growth process to form the semiconductor structure 14 . The semiconductor material can be, for example, a single-element semiconductor material such as germanium (Ge) or silicon (Si), a compound semiconductor material such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or a silicon germanium material (SiGe), gallium arsenide phosphide (GaAsP) semiconductor alloy.

In a possible implementation manner, the semiconductor material may be grown by in-situ doping, and then the semiconductor material may be annealed at high temperature to form the semiconductor structure 14 .

In another possible implementation, the semiconductor material can be grown first in a non-doped manner, and then ions are implanted into the semiconductor material by ion implantation. A semiconductor structure 14 is formed.

When the formed FinFET device is P-type, the doped ions can be trivalent ions such as boron ions; when the formed FinFET device is N-type, the doped ions can be pentavalent ions such as phosphorus ions.

In step 904, insulating materials are deposited on the first active region and the second active region, respectively, to form an insulating structure.

Specifically, the insulating material may include, but is not limited to, materials such as silicon oxide or oxynitride. The insulating material may be deposited by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like.

Then, excess insulating material may be removed by a chemical mechanical polishing (CMP) process to form insulating structures 17 . The insulating structure 17 is flush with the side of the dummy gate structure 151 away from the substrate, as shown in FIG. 10D .

In step 905, the dummy gate structure is etched to expose the portion of the fin located in the channel region.

A patterned mask layer is formed on the first insulating structure 17 and the dummy gate structure 151, and the dummy gate structure 151 shown in FIG. 10D is etched, thereby exposing the second portion 111 of the fin located in the channel region. In addition, after the dummy gate structure 151 is etched, the bottom insulating layer 12 is exposed.

In step 906, the exposed fin structure is etched to reduce the width of the fin portion located in the channel region.

In a specific process, a patterned mask layer may be formed on the exposed second portion 111 of the fin, and the fin may be etched by dry etching, wet etching, or the like. The etched structure of the second portion 111 of the fin is shown in FIG. 10E .

In this embodiment, the fins 11 are not completely etched, and the purpose of the etching is to reduce the width of the fins 11 along the second direction Y. Therefore, in a preferred implementation manner, an atomic layer etching (ALE) method is used to etch the fin structure. In this way, the etching amount of the fins 11 can be precisely controlled, so that while the width of the fins 11 in the second direction y can be reduced, the etching amount of the fins in the third direction Z can also be reduced.

In this embodiment, about 1/3 of the fin material can be etched away. For example, when the width of the fin 11 formed in step 901 along the second direction Y is 7 nm, this step can be etched by 2 nm to 3 nm, so that the width of the fin 11 along the second direction Y is about 4 nm to 5 nm.

Step 907, forming a gate structure in the channel region.

In a specific process, an HK dielectric layer may be deposited in the channel region first. Specific materials of the HK dielectric layer may include, but are not limited to, Lao, ALO, ZrO, TiO, SiO and other materials.

Then, metal is deposited on the HK dielectric layer by methods such as PVD and CVD, and then the excess metal material is removed by a CMP process, so that the metal is flush with the side of the sidewall structure 13 away from the substrate, thereby forming the gate structure 15, As shown in Figure 10E. The metal material may include an N-gate metal material forming an N-type field effect transistor, or a P-gate metal material forming a P-type field effect transistor. Wherein, the N gate metal material may include but not limited to: Ti, Ag, Al, TiAlN, TaCN, TaSiN, Mn, etc.; the P gate metal material may include but not limited to: TiN, TaN, Ru, Mo, Al, WN, etc.

In step 908, the insulating structure is etched, metal material is deposited, and contact metal is formed to lead out the source electrode and the drain electrode.

The insulating structure 17 over the semiconductor structure 14 is etched to expose the upper surface of the semiconductor structure 14 away from the substrate.

Then, a metal material is deposited on the exposed semiconductor structure 14 , and the excess metal material is removed by a CMP process to form a contact metal 16 . The side of the contact metal 16 that is not in contact with the semiconductor structure 14 may be flush with the spacer structure 13 . Finally, the FinFET structure shown in FIG. 5 is formed.

In this embodiment, after the dummy gate structure is etched to expose the fin structure, the fin is etched to reduce the width of the fin. It can be seen from the above process steps that the step of thinning the fin is after forming the source electrode and the drain electrode. The fins in the first active region and the second active region are not thinned, and the original thickness remains unchanged during the production process, thereby ensuring the stress of the fins in the first active region and the second active region. In addition, during the production process, the production yield can also be improved. Thus, it is beneficial to improve the reliability of the FinFET.

Please continue to refer to FIG. 11 , which shows another method for fabricating a FinFET provided by an embodiment of the present application. The structure of the FinFET fabricated by the FinFET fabricating method is shown in FIG. 8 . For the process flow of manufacturing the FinFET, reference may be made to the flow 1100 shown in FIG. 11 . The technological process includes the following steps:

In step 1101, a substrate is provided, and a fin structure is formed on the substrate.

Step 1102, forming a dummy gate structure and a spacer structure on the fin and the insulating layer.

The specific process of step 1101 and step 1102 and the structure after the above two steps are completed are the same as the specific implementation shown in step 901 and step 902, you can refer to the specific implementation of step 901 and step 902 shown in FIG. 9, and will not be repeated here.

Step 1103, wrapping insulating material on both side walls of the exposed fins.

Specifically, insulating materials may be deposited on the first active region A1 and the second active region A2, respectively.

Then, the deposited insulating material is etched, so that the two sidewalls of the exposed first portion 110 of each fin are wrapped with the insulating material 142 .

It should be noted that, when the insulating material is deposited on the first active region A1 and the second active region A2, it is in contact with the spacer structure 13 respectively. In order to reduce the number of process steps, the insulating material in the contact portion with the spacer structure 13 may not be used. Etching is performed, that is, a layer of sidewall is further attached to the sidewall of the sidewall structure 13 , as shown in FIG. 12A . It can be understood that the material of the sidewall to which the sidewall structure 13 is attached is the same as the insulating material 142 wrapped by the fins.

In specific practice, the deposited insulating material may include, but is not limited to, silicon oxide or oxynitride and other materials. In addition, the insulating material deposited in step 1103 may be the same material as that for forming the spacer structure 13 .

Step 1104 , etch back the exposed fins, and grow a semiconductor structure on the etched fins.

Specifically, the first part 110 and the first part 110 exposed by the fin 11 may be etched back first, so as to reduce the height of the first part 110 of the fin 110 along the third direction Z. The height of the etched first portion 110 along the third direction Z is not lower than the upper surface of the insulating layer 12 . The upper surface of the insulating layer 12 is the side of the insulating layer away from the substrate 10 along the third direction Z.

In practice, the upper surface of the exposed first portion 110 of the fin can be etched to be flush with the insulating layer 12 .

Then, the semiconductor material is confined within the insulating material 142 for growth, so that the formed semiconductor structure can be a plurality of regular geometric structures. In addition, the formed semiconductor structures 14 are insulated from each other, as shown in FIG. 12B .

The specific process of growing the semiconductor material refers to step 903, which will not be repeated here.

Step 1105 , depositing insulating materials on the first active region and the second active region, respectively, to form a first insulating structure.

In step 1106, the dummy gate structure is etched to expose the portion of the fin located in the channel region.

In step 1107, the exposed fins are etched to reduce the width of the fin portions located in the channel region.

Step 1108, forming a gate structure in the channel region.

The specific process of step 5-step 8 and the structure after the above two steps are completed are the same as the specific implementation shown in step 904-step 907, please refer to the specific implementation of step 904-step 907 shown in FIG. The structure after the end of step 1108 is shown in FIG. 12C .

Step 1109 , etching the first insulating structure and the insulating material limiting the growth position of each semiconductor structure to expose the outer surface of each semiconductor structure.

The structure after this step is completed is shown in Figure 12D.

Step 1110, wrapping a metal material on the outer surface of the semiconductor structure.

The wrapped metal material may include, but is not limited to, copper, nickel, aluminum or alloys formed by any combination thereof, and the like.

In a specific process, metal materials may be deposited on the insulating layers 12 of the first active region A1 and the second active region A2 respectively, and the deposited metal materials cover the semiconductor structures 14 . Then, the metal material is etched, and only the part wrapping the outer surface of the semiconductor structure 14 remains, and the rest is etched away. After the metal material is etched, the insulating layer 12 between each two semiconductor structures 14 is exposed. The structure after step 1110 is shown in FIG. 12E .

Step 1111, forming a second insulating structure between every two semiconductor structures.

Specifically, after step 1110, insulating materials may be further deposited on the first active area A1 and the second active area A2, respectively. The deposited insulating material is then etched to expose the top surface of each semiconductor structure 14 , as shown in FIG. 6 . At this time, a second insulating structure 18 is formed between every two semiconductor structures. Wherein, the bottom surface of the second insulating structure 18 located between every two semiconductor structures 14 is in contact with the insulating layer 12 , and the top surface may be flush with the top surface of the semiconductor structure 14 .

It should be noted that, in the process of forming the second insulating structure 18 as shown in FIG. 6 , the insulating material is directly deposited on the semiconductor structure 14 and the insulating layer 12 , and then the insulating material on the top of the semiconductor structure 14 is etched At this time, along the second direction Y, the gap between the first insulating structure 17 and the semiconductor structure 16 is also filled with the above-mentioned second insulating structure 18 . In another possible implementation manner, when there is no gap between the first insulating structure 17 and the semiconductor structure 16 along the second direction Y, the second insulating structure 17 and the semiconductor structure 16 may not be provided with a second gap. Insulating structure 18 .

Step 1112, depositing a metal material on the top surface of the semiconductor structure and the top surface of the second insulating structure to form a contact metal to lead out the source electrode and the drain electrode.

Specifically, a metal material is deposited on the exposed semiconductor structure 14 , and the excess metal material is removed by a CMP process to form the contact metal 16 . The side of the contact metal 16 which is not in contact with the semiconductor structure 14 may be flush with the spacer structure 13 . Finally, the FinFET structure shown in FIG. 8 is formed. The deposited metal material may include, but is not limited to, copper, nickel, aluminum, or alloys formed by any combination thereof, and the like.

It can be seen from the process flow shown in FIG. 11 that, different from the process flow shown in FIG. 9 , in the process flow shown in FIG. 11 , when growing the semiconductor structure, the semiconductor material is limited to the sealing surface formed by the insulating material. In the space, the semiconductor structure can be made to have a regular structure. In addition, the outer surface of the semiconductor structure is also wrapped with a metal material, so that the contact resistance of the transistor can be reduced and the driving current of the transistor can be improved.

In addition, the embodiments of the present application also provide a method for preparing a semiconductor wafer. The wafer is used to form a first fin field effect transistor and a second fin field effect transistor.

The first fin field effect transistor may be the fin field effect transistor shown in FIG. 5 or the fin field effect transistor shown in FIG. 8 . The width of the fin portion located in the channel region of the first fin field effect transistor is lower than the width of the fin portion located in the first active region and the second active region. In the second fin field effect transistor, the widths of each part of the fin are the same. In a specific process, part of the fins in the channel region on the wafer may be etched, and after this step is completed, gate structures are deposited on all the channel regions on the wafer. Thus, the first fin field effect transistor and the second fin field effect transistor can be formed on the wafer.

In this way, two different types of FinFETs can be fabricated on the same wafer for electronic devices with different threshold voltage requirements and leakage current requirements.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present application. Scope.

Claims

A fin field effect transistor, characterized in that it comprises:

a substrate, on which an active region and a channel region are formed;

a fin, formed on the substrate and passing through the active region and the channel region;

in,

The width of the portion of the fin located in the channel region is smaller than the width of the portion of the fin located in the active region.
The fin field effect transistor according to claim 1, wherein the fin field effect transistor further comprises a plurality of spacer structures;

Each spacer structure in the plurality of spacer structures is formed between the active region and the channel region; wherein,

In the direction of the width of the fins, each sidewall structure of the plurality of sidewall structures spans the fins.
The fin field effect transistor according to claim 1 or 2, wherein the fin field effect transistor comprises a plurality of the fins;

The plurality of the fins are sequentially and spaced apart along the width direction of the fins.
The fin field effect transistor according to any one of claims 1-3, wherein the active region comprises a semiconductor structure;

The semiconductor structure is formed on the fin away from the substrate.
The fin field effect transistor according to claim 4, wherein the active region comprises a plurality of semiconductor structures, and the plurality of semiconductor structures are sequentially spaced along the width direction of the fin;

The outer surface of each semiconductor structure of the plurality of semiconductor structures is wrapped with a metal material.
The fin field effect transistor according to claim 5, wherein an insulating structure is disposed between every two semiconductor structures in the plurality of semiconductor structures.
The fin field effect transistor according to any one of claims 1-6, wherein the channel region comprises a gate structure;

The gate structure covers the portion of the fin in the channel region.
An electronic device, characterized in that, the electronic device comprises the fin field effect transistor according to any one of claims 1-7.
A preparation method of a fin field effect transistor, characterized in that the method comprises:

providing a substrate on which fins are formed;

forming an active region and a channel region on the substrate, the fin penetrating the active region and the channel region;

The part of the fin located in the channel region is etched, so that the width of the part of the fin located in the channel region is smaller than the width of the part located in the active region.
The preparation method according to claim 9, wherein the forming an active region and a channel region on the substrate comprises:

depositing a first insulating material on the substrate and the fin, and etching the first insulating material to form a plurality of spacer structures separated from each other, each of the plurality of spacer structures straddling the fin along the width direction of the fin to divide the fin into a plurality of parts;

separately growing semiconductor material over at least two non-adjacent portions of the plurality of portions of the fin to form active regions;

The portion of the fin where the semiconductor structure is not grown forms a channel region.
The preparation method according to claim 10, wherein the step of growing a semiconductor material on at least two non-adjacent portions of the plurality of portions of the fin to form an active region comprises:

wrapping a second insulating material on the sidewalls of at least two non-adjacent portions of the fin portion;

etching the portion of the fin that wraps the second insulating material to reduce the height of the portion of the fin that wraps the second insulating material along the thickness direction of the substrate;

A semiconductor structure is grown within the space region defined by the second insulating material, on the portion of the fin that wraps the second insulating material, to form an active region.
The preparation method according to claim 11, wherein the method further comprises:

etching the second insulating material to expose the outer surface of the semiconductor structure;

A metal material is wrapped around the outer surface of the semiconductor structure.