WO2022016463A1 - Transistor à effet de champ à ailette et procédé de préparation - Google Patents

Transistor à effet de champ à ailette et procédé de préparation Download PDF

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Publication number
WO2022016463A1
WO2022016463A1 PCT/CN2020/103855 CN2020103855W WO2022016463A1 WO 2022016463 A1 WO2022016463 A1 WO 2022016463A1 CN 2020103855 W CN2020103855 W CN 2020103855W WO 2022016463 A1 WO2022016463 A1 WO 2022016463A1
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Prior art keywords
fin
field effect
effect transistor
semiconductor
channel region
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PCT/CN2020/103855
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English (en)
Chinese (zh)
Inventor
许俊豪
贝尼斯坦特·弗朗西斯·莱昂内尔
侯朝昭
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华为技术有限公司
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Priority to PCT/CN2020/103855 priority Critical patent/WO2022016463A1/fr
Priority to CN202080101476.8A priority patent/CN115699270A/zh
Publication of WO2022016463A1 publication Critical patent/WO2022016463A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Definitions

  • the embodiments of the present application relate to the technical field of semiconductor devices, and in particular, to a structure and a manufacturing method of a fin transistor.
  • Fin Field-Effect Transistor Fin Field-Effect Transistor
  • FinFET Fin Field-Effect Transistor
  • the ratio between the length of the conductive channel of the FinFET (ie the gate length) and the width of the fin needs to be not lower than a certain critical value (eg 2.5).
  • a certain critical value eg 2.5.
  • the length of the conductive channel is inversely correlated with the switching speed of the field effect transistor.
  • the length of the conductive channel is usually reduced.
  • the thickness of the fin in the FinFET needs to be further thinned. Too thin fins will lead to problems such as increased source/drain expansion resistance and reduced source/drain effective stress.
  • too thin fins are prone to breakage during production, reducing the production yield of FinFETs. Therefore, how to improve the reliability of the FinFET while ensuring the switching speed has become a problem to be solved.
  • the fin field effect transistor and the preparation method provided by the present application can improve the reliability of the short channel fin field effect transistor while ensuring the switching speed.
  • embodiments of the present application provide a fin field effect transistor, the fin field effect transistor comprising: a substrate on which an active region and a channel region are formed; a fin formed on the on the substrate, and runs through the active region and the channel region; wherein, the width of the portion of the fin located in the channel region is smaller than the width of the portion of the fin located in the active region .
  • the short-channel FinFET structure can make conductive
  • the ratio between the channel and the portion of the fin located in the conductive channel region is not lower than a certain critical value, and the width of the portion of the fin located in the active region can not be affected by the above ratio; in addition, the active region can also be maintained.
  • the hardness of the fin portion of the region reduces the spreading resistance, thereby improving the reliability of the FinFET.
  • the ratio of the width of the portion of the fin located in the channel region to the width of the portion of the fin located in the active region is 2:3.
  • the length of the channel region of the short-channel device is usually 10 nm-14 nm
  • the width of the fin located in the active region is usually 7 nm.
  • the width of the part of the fin in the channel region and the width of the part of the fin in the active region can be The width ratio is 2:3.
  • the width of the portion of the fin located in the channel region is 4 nm, and the width of the portion of the fin located in the active region is 7 nm.
  • the fin field effect transistor further includes a plurality of spacer structures; each spacer structure in the plurality of spacer structures is formed in the active region and between the channel region; wherein, along the width direction of the fin, each sidewall structure of the plurality of sidewall structures spans the fin.
  • each of the spacer structures in the plurality of spacer structures includes multiple layers; wherein a side close to the channel region is a silicon oxide layer, and a side away from the spacer structure is a silicon oxide layer.
  • One side of the channel region is a silicon nitride layer.
  • the fin field effect transistor includes a plurality of the fins; and the plurality of the fins are arranged in sequence along the width direction of the fins at intervals.
  • the active region includes a semiconductor structure; and the semiconductor destructure is formed on the fin on a side away from the substrate.
  • a plurality of semiconductor structures are sequentially and spaced apart along the width direction of the fin; the outer surface of each semiconductor structure in the plurality of semiconductor structures is wrapped with a metal material .
  • a contact metal is deposited on the side of the semiconductor structure away from the substrate, and the contact metal is used to lead out the source and drain during packaging.
  • the contact resistance between the semiconductor structure and the contact metal can be reduced, so that the driving current of the FinFET can be improved.
  • an insulating structure is provided between every two semiconductor structures in the plurality of semiconductor structures.
  • the channel region includes a gate structure; the gate structure covers a portion of the fin in the channel region.
  • the gate structure includes a gate dielectric layer and a gate metal layer; wherein, the gate dielectric layer is a high dielectric constant dielectric layer.
  • an embodiment of the present application provides an electronic device including the fin field effect transistor described in the first aspect.
  • the electronic device may be an unpackaged bare chip.
  • the electronic device may also be an electronic device, and the FinFET shown in the embodiments of the present application may be packaged in a tube case.
  • the package may include, but is not limited to, a plastic package, a metal package (eg, a gold shell, a nickel shell), etc., and the source, drain and gate of the FinFET are drawn out from the outer surface of the package.
  • the electronic device may also be an integrated circuit product (such as a system-on-chip), wherein, in addition to the FinFET described in the embodiments of the present application, the integrated circuit product may also include other integrated circuits, so that the The shown FinFET cooperates with other integrated circuits to realize various circuit functions.
  • integrated circuit product such as a system-on-chip
  • an embodiment of the present application provides a method for fabricating a fin field effect transistor, the fabrication method comprising: providing a substrate, forming a fin on the substrate; forming an active region on the substrate and the channel region, the fin penetrates the active region and the channel region; the part of the fin located in the channel region is etched, so that the fin is located in the channel region The width of the portion is smaller than the width of the portion located in the active region.
  • the forming the active region and the channel region on the substrate includes: depositing a first insulating material on the substrate and the fin, and etching etching the first insulating material to form a plurality of spacer structures separated from each other, each of the spacer structures in the plurality of spacer structures spans the fins along the width direction of the fins, to dividing the fin into a plurality of parts; growing semiconductor material on at least two non-adjacent parts of the plurality of parts of the fin respectively to form an active region; part of the fin where the semiconductor structure is not grown A channel region is formed.
  • the step of growing a semiconductor material on at least two non-adjacent portions of the plurality of portions of the fin to form an active region includes: on the fin The sidewalls of at least two non-adjacent portions of the fins are wrapped with a second insulating material; and the portion of the fins wrapped with the second insulating material is etched to reduce the wrapping of the fins with the second insulating material.
  • the method further includes: etching the second insulating material to expose the outer surface of the semiconductor structure; and wrapping a metal material on the outer surface of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a fin in a fin field effect transistor provided by an embodiment of the present application
  • FIG. 2A is a cross-sectional view along AA' of the fin field effect transistor shown in FIG. 1 provided by an embodiment of the present application;
  • FIG. 2B is a cross-sectional view of the fin field effect transistor shown in FIG. 1 along BB' provided by an embodiment of the present application;
  • 3A is a schematic structural diagram of a fin field effect transistor in a conventional technology
  • Figure 3B is a cross-sectional view along CC' and DD' of the fin field effect transistor shown in Figure 3A;
  • FIG. 4 is a schematic structural diagram of a semiconductor structure deposited in a fin field effect transistor provided by an embodiment of the present application;
  • FIG. 5 is a schematic diagram of an overall structure of a fin field effect transistor provided by an embodiment of the present application.
  • FIG. 6 is another structural schematic diagram of the semiconductor structure deposited in the fin field effect transistor provided by the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of the fin field effect transistor shown in FIG. 6 along EE' provided by an embodiment of the present application;
  • FIG. 8 is another schematic diagram of the overall structure of the fin field effect transistor provided by the embodiment of the present application.
  • FIG. 9 is a flowchart of a method for fabricating the fin field effect transistor shown in FIG. 5 provided by an embodiment of the present application.
  • FIG. 10A-FIG. 10E are schematic diagrams of each structure in the preparation process of the fin field effect transistor shown in FIG. 5;
  • FIG. 11 is a flowchart of a method for fabricating the fin field effect transistor shown in FIG. 8 provided by an embodiment of the present application;
  • FIGS. 12A-12E are schematic diagrams of each structure during the fabrication process of the fin field effect transistor shown in FIG. 8 .
  • references herein to "first,” “second,” and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Likewise, words such as “a” or “an” do not denote a quantitative limitation, but rather denote the presence of at least one.
  • words such as “exemplary” or “for example” are used to indicate an example, illustration or illustration. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • the meaning of "plurality” refers to two or more. For example, a plurality of fins refers to two or more fins.
  • FIG. 1 is a schematic structural diagram of a fin field effect transistor provided by an embodiment of the present application.
  • FinFET 100 includes substrate 10 and fins 11 .
  • the fins 11 and the substrate 10 are of the same material.
  • the substrate may be etched to form the fins 11 .
  • the semiconductor materials commonly used for the substrate 10 and the fins 11 may specifically include but are not limited to: silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), silicon carbide (SiC) ), indium phosphide (InP), zinc selenide (ZnSe), or other Group VI, III-V or II-VI semiconductor materials.
  • one or more fins 11 may be included.
  • the fins 11 extend along the first direction X shown in FIG. 1 , therefore, the first direction X can also be regarded as the length direction of the fins 11 , and the second direction Y perpendicular to the first direction X can be regarded as the width direction of the fins 11 .
  • the FinFET includes a plurality of fins, the plurality of fins are sequentially arranged along the second direction Y shown in FIG. 1 .
  • the plurality of fins protrude from a side close to the substrate 10 to a side away from the substrate 10 . It can be understood that, the embodiment of the present application does not limit the number of fins, which may include more or less fins.
  • the FinFET 100 is divided into a plurality of regions by a plurality of spacer structures 13, and the plurality of regions include a first active region A1, a second active region A2, and the first active region The channel region C between the region A1 and the second active region A2.
  • the first active region A1 and the second active region A2 may be regions where a source electrode or a drain electrode is formed, respectively.
  • the channel region C is used to form the gate.
  • the fin 11 is also divided into a plurality of parts by the spacers 13 , including the first part 110 in the first active region A1 and the second active region A2 , and the second part in the channel region C 111.
  • the second portion 111 is in the channel region C of the FinFET 100 .
  • the first active region A1 and the second active region A2 may be understood as regions on the substrate 10 where the semiconductor structure 14 shown in FIG. 4 is formed, and the semiconductor structure 14 has dopants,
  • the first active region A1 and the second active region A2 are usually formed with contact metal 16 such as shown in FIG. 5 , and the contact metal 16 is used to lead out the source or drain .
  • the materials, shapes, etc. of the semiconductor structure 14 and the contact metal 16 may refer to the specific description below.
  • the spacer structure 13 is formed by directly depositing the above-mentioned insulating material on the fins 11 and the insulating layer 12 .
  • the sidewall structure 13 spanning the fins 11 wraps the part of the fins it spans. From the outside, a plurality of sidewall structures 13 separate the fins into the first active area A1 and the second active area A1.
  • the first portion 110 of the active region A2, and the second portion 111 of the channel region C are materials of the side wall structure 13, reference may be made to the specific description below.
  • the width of the first portion 110 of the fin 11 is different from the width of the second portion 111 .
  • the width of the second portion 111 of the fin 11 is smaller than the width of the first portion 110 .
  • FIGS. 2A and 2B FIG. 2A is a cross-sectional view of the FinFET 100 taken along AA' shown in FIG. 1
  • FIG. 2B is a cross-sectional view of the FinFET 100 taken along BB' shown in FIG. 1 .
  • the width of the second portion 111 of the fin 11 is smaller than the width of the first portion 110 .
  • each first portion 110 of the fin 11 is grown with a semiconductor structure forming a source electrode and a drain electrode (the semiconductor structure 14 shown in FIG. 4 ).
  • the semiconductor structure grown on the fin is not shown in FIG. 1 .
  • each part of the fin 11 is generally set to have the same width. As shown in FIG.
  • FIG. 3A schematically shows a schematic diagram of a fin structure in a conventional FinFET structure
  • FIG. 3B is a cross-sectional view of the FinFET taken along CC' and DD' shown in FIG. 3A.
  • Fins that are too thin usually bring more problems, such as increasing the spread resistance of the first active area A1 and the second active area A2, causing the variation difference of the FinFET to increase, the first active area A1 and the second active area A2. Problems such as stress reduction in the active region A2.
  • the height of the fins 11 along the third direction Z increases continuously, which makes the ratio between the height of the fins 11 along the third direction Z and the width along the second direction Y become larger and larger. , resulting in the fin 11 being easily broken during the production process of the FinFET, which seriously reduces the production yield of the FinFET.
  • the first active region A1 of the fins 11 is kept in the first active region A1. and the width of the first portion 110 of the second active region A2 remains unchanged, so that in the short-channel FinFET structure, the ratio of the length of the conductive channel to the width of the fin portion located in the conductive channel region is not lower than a certain
  • the fin parts in the first active area A1 and the second active area A2 can maintain sufficient width, so as to maintain the fin 11 part of the first active area A1 and the second active area A2 strength, reduce the expansion resistance, and improve the reliability of the FinFET.
  • the width of the second part 111 of the fin 11 can be set to 4 nm; when the width of the first part 110 of the fin 11 is 7 nm, along the second direction Y, the width of the second part 111 of the fin 11 is 7 nm.
  • the ratio between the width and the width of the first portion 110 may be 4:7.
  • the width of the second part 111 is set to 5 nm; when the width of the first part 110 of the fin 11 is 7 nm, along the second direction Y, the ratio between the width of the second part 111 of the fin 11 and the width of the first part 110 can be 5:7.
  • the width of the first portion 110 of the fin 11 is usually 7 nm.
  • the length of the channel region C is in the range of 10nm-14nm, and the fins 11 along the first part 110
  • the ratio between the width of the second portion 111 of the fin 11 and the width of the first portion 110 can be set to 2:3.
  • the ratio between the width of the second part 111 of the fin 11 and the width of the first part 110 may also be 4:7, and the ratio between the width of the second part 111 of the fin 11 and the width of the first part 110 may also be 5:7 etc.
  • the widths of the first portion and the second portion of the fin 11 may be determined according to the width of the conductive channel region, which is not specifically limited herein. In some other scenarios, for example, when the length of the channel region C is 10 nm and the width of the first part 110 of the fin 11 is 5 nm, the ratio between the width of the second part 111 of the fin 11 and the width of the first part 110 is also Can be 4:5.
  • the FinFET 100 shown in FIG. 1 further includes an insulating layer 12 , and the material of the insulating layer 12 includes but is not limited to: silicon oxide, sapphire, or any material of their combination.
  • the thickness of the insulating layer 12 along the third direction Z is less than or equal to the height of the fins 11 protruding from the substrate 10 .
  • the insulating layer 12 isolates the plurality of fins.
  • the spacer structure 13 in the FinFET 100 is deposited on the above-mentioned insulating layer 12 and the fins 11 , and the spacer structure 13 spans the fins 11 along the second direction Y. As shown in FIG. As can be seen from FIG. 1 , in the third direction Z, the height of the sidewall structures 13 is greater than the height of the protrusions of the fins 11 .
  • the material for forming the spacer structure 13 may include, but is not limited to, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or any combination thereof.
  • the sidewall structure 13 may be, for example, a structure formed of multiple layers of materials. For example, the side close to the channel region is a silicon oxide layer, and the side away from the channel region is a silicon nitride layer.
  • the FinFET 100 further includes a gate structure 15 , and the gate structure 15 is formed in the channel region C between the first active region A1 and the second active region A2 , as shown in FIG. 4 .
  • the gate structure 15 wraps the second portion of the fin 11 in the channel region.
  • the wrapping here means that among the surfaces of the fin extending along the first direction X, except the surface contacting the substrate, the other surfaces are covered by the gate material.
  • the FinFET is made to form a multi-gate structure.
  • the multi-gate structure here means that one gate structure is formed between every two fins 11 .
  • the gate structure 15 may include a gate dielectric layer and a gate metal layer.
  • the gate dielectric layer is deposited on the insulating layer 12 and the fins 11 in the conductive channel region.
  • the gate dielectric layer can be a high dielectric constant (HK, High-K) dielectric layer, and its specific materials can include but are not limited to: lanthanum oxide (LaO), aluminum oxide (ALO), zirconium oxide (ZrO), Titanium oxide (TiO), silicon oxide (SiO) and other materials.
  • a gate metal layer is deposited over the gate dielectric layer, and the gate metal layer may include an N-gate metal layer forming an N-type field effect transistor, or a P-gate metal layer forming a P-type field effect transistor.
  • the material of the N gate metal layer may include but not limited to: titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), Manganese (Mn), etc.;
  • the material of the P gate metal layer may include, but is not limited to: Titanium Nitride (TiN), Tantalum Nitride (TaN), Ruthenium (Ru), Molybdenum (Mo), Aluminum (Al), Tungsten Nitride (WN) )Wait.
  • the top surface of the gate metal layer is flush with the top surface of the spacer structure 13 , as shown in FIG. 5 .
  • the source electrode and the drain electrode may be formed by epitaxially growing a semiconductor material on the first portion 110 of the fin 11 .
  • the semiconductor material may be, for example, a single-element semiconductor material such as germanium (Ge) or silicon (Si), a mixed semiconductor material of germanium and silicon, or gallium arsenide (GaAs), gallium aluminum arsenide (AlGaAs)
  • the compound semiconductor material can also be a semiconductor alloy such as silicon germanium (SiGe) and gallium arsenide phosphide (GaAsP).
  • the source and drain electrodes can be formed by in-situ doping.
  • FIG. 4 The semiconductor structure 14 formed by the semiconductor material grown on the first portion 110 of the fin 11 is shown in FIG. 4 . It should be noted that FIG. 4 only illustrates the semiconductor structure 14 formed in the first active area A1, and the semiconductor structure formed in the second active area A2 may be the same as the semiconductor structure formed in the first active area A1 shown in FIG. 4 . The shape and material of the semiconductor structure are the same and are not shown in FIG. 4 .
  • the FinFET 100 further includes a first insulating structure 17 deposited around the epitaxially grown semiconductor structure 14 to protect the semiconductor structure 14 .
  • the material of the first insulating structure 17 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., wherein, along the third direction Z, the bottom surface of the first insulating structure 17 is in contact with the insulating layer 12, and the top surface is in contact with the insulating layer 12.
  • the gate structure 15 is flush, as shown in FIG. 5 .
  • FinFET 100 also includes contact metal 16 deposited over epitaxially grown semiconductor structure 14 .
  • the contact metal 16 is used to extract the source and drain electrodes.
  • the material contacting the metal may include, but is not limited to, metal copper, nickel, aluminum or an alloy formed by any combination thereof, for example.
  • the bottom of the contact metal 16 is in contact with the semiconductor structure 14 (eg, wraps the top surface of the semiconductor structure 14 ), and the top surface of the contact metal 16 is flush with the gate structure 15 and the second insulating layer 17 .
  • the epitaxially grown semiconductor structure 14 is an irregular geometry, such as a polygon as shown in FIG. 4 , or a prism.
  • the grown semiconductor structures 14 are all connected together.
  • FIG. 6 to FIG. 8 are schematic structural diagrams of still another FinFET provided by an embodiment of the present application.
  • a plurality of mutually insulated semiconductor structures 14 may be included, wherein each semiconductor structure is a regular geometric body, such as a rectangular parallelepiped shown in FIG. 6 , and in some other implementations , can also be a cube, etc.
  • the semiconductor structure 14 may be formed by using an insulating layer to define the position and shape of semiconductor growth.
  • the surfaces of the individual semiconductor structures 14 are also wrapped with metal materials 141 respectively.
  • the metal material wrapping each independent semiconductor structure 14 may include, but not limited to, copper, nickel, aluminum or an alloy formed by any combination thereof, and the like. The meaning of wrapping here is that, except for the side in contact with the insulating layer 12 , the side in contact with the sidewall structure 13 , and the side opposite to the side in contact with the sidewall structure 13 , the other sides of each independent semiconductor structure are covered with metal materials. pack.
  • FIG. 7 is a cross-sectional view of the FinFET shown in FIG. 6 along EE'.
  • a second insulating structure 18 is also filled between every two semiconductor structures 14 .
  • Each second insulating structure 18 is deposited on the insulating layer 12 .
  • the lower surface thereof is in contact with the insulating layer 12 , and the top surface may be flush with the top surface of the semiconductor structure 14 , as shown in FIG. 8 .
  • the insulating material is directly deposited on the semiconductor structure 14 and the insulating layer 12 , and then the insulating material on the top of the semiconductor structure 14 is etched.
  • the gap between the first insulating structure 17 and the semiconductor structure 16 is also filled with the above-mentioned second insulating structure 18 .
  • the second insulating structure 17 and the semiconductor structure 16 may not be provided between the first insulating structure 17 and the semiconductor structure 16 . Insulating structure 18 .
  • the FinFET shown in FIG. 8 further includes a substrate 10 , a fin 11 , a spacer structure 13 , an insulating layer 12 , a gate structure 14 , a contact metal 16 and a first insulating structure 17 .
  • the structures and materials of the substrate 10 , the fins 11 , the spacer structure 13 , the insulating layer 12 , the gate structure 14 , the contact metal 16 and the first insulating structure 17 are the same as those of the FinFET shown in FIG. 1 , FIG. 4 and FIG. 5 .
  • the structure and materials are the same. For details, refer to the related descriptions of the FinFET structures shown in FIG. 1 , FIG. 4 and FIG. 5 , which will not be repeated here.
  • the embodiments of the present application also include an electronic device, which includes the FinFET shown in the above-mentioned embodiments.
  • the electronic device may be an unpackaged bare chip or an electronic device, and the FinFET shown in the embodiments of the present application may be packaged in a tube case.
  • the package may include, but is not limited to, a plastic package, a metal package (eg, a gold shell, a nickel shell), etc., and the source, drain and gate of the FinFET are drawn out from the outer surface of the package.
  • the electronic device may also be an integrated circuit product (such as a system-on-chip), wherein, in addition to the FinFET described in the embodiments of the present application, the integrated circuit product may also include other integrated circuits, so that the The shown FinFET cooperates with other integrated circuits to realize various circuit functions.
  • integrated circuit product such as a system-on-chip
  • an embodiment of the present application further provides a method for fabricating a FinFET, and the structure of a FinFET fabricated by the method for fabricating a FinFET is shown in FIG. 5 .
  • the process flow of manufacturing the FinFET reference may be made to the flow 900 shown in FIG. 9 .
  • the process flow 900 includes the following steps:
  • step 901 a substrate is provided, and a fin structure is formed on the substrate.
  • the substrate may be a semiconductor material, and the semiconductor material may specifically include but not be limited to: silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), silicon carbide (SiC), Indium Phosphide (InP), Zinc Selenide (ZnSe) or other Group VI, III-V or II-VI semiconductor materials.
  • a patterned mask layer may be formed on the substrate 10, the substrate 10 is etched by using the patterned mask layer as a mask, and the unetched portion forms a plurality of fins 11 , the etched part forms a plurality of trenches. Specifically, a groove is formed between every two fins 11 . As shown in Figure 10A. Specifically, various etching methods such as dry etching or wet etching can be used to etch the above-mentioned substrate 10 to form a plurality of fins 11 and trenches.
  • Step 902 forming a dummy gate structure and a spacer structure on the fin and the insulating layer.
  • a semiconductor material such as polysilicon may be deposited in the middle of the fin 11 to form the dummy gate structure 151 . It should be noted that, since the polysilicon material needs to be etched later to deposit a metal gate, the gate formed by the deposited polysilicon material is referred to as a dummy gate here.
  • the spacer structures 13 are formed on the sidewalls of the dummy gate structures 151 .
  • the material of the spacer structure 13 may include, but is not limited to, silicon nitride, silicon carbide, silicon oxynitride, and the like. Wherein, the spacer structure 13 can be completed by dielectric deposition and etching processes.
  • the spacer structure 13 may include two parts spanning a plurality of fins, one part is used to block the first active region A1 and the dummy gate structure 151 forming the source electrode, and the other part is used to block the second part forming the drain electrode The source region A2 and the dummy gate structure 151 .
  • the second part 111 of the fin 11 is wrapped by the dummy gate structure, and the first part 110 of the fin 11 is exposed to the outside. As shown in Figure 10C.
  • Step 903 growing a semiconductor structure on the exposed portion of the fin.
  • the semiconductor structure 14 is formed on the exposed first portion 110 of the fin, and the formed semiconductor structure is shown in FIG. 4 .
  • the exposed first portion 110 of the fin may be etched back first, so as to reduce the height of the first portion 110 of the fin along the third direction Z. As shown in FIG.
  • the semiconductor material can be, for example, a single-element semiconductor material such as germanium (Ge) or silicon (Si), a compound semiconductor material such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or a silicon germanium material (SiGe), gallium arsenide phosphide (GaAsP) semiconductor alloy.
  • a single-element semiconductor material such as germanium (Ge) or silicon (Si)
  • a compound semiconductor material such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or a silicon germanium material (SiGe), gallium arsenide phosphide (GaAsP) semiconductor alloy.
  • the semiconductor material may be grown by in-situ doping, and then the semiconductor material may be annealed at high temperature to form the semiconductor structure 14 .
  • the semiconductor material can be grown first in a non-doped manner, and then ions are implanted into the semiconductor material by ion implantation.
  • a semiconductor structure 14 is formed.
  • the doped ions can be trivalent ions such as boron ions; when the formed FinFET device is N-type, the doped ions can be pentavalent ions such as phosphorus ions.
  • step 904 insulating materials are deposited on the first active region and the second active region, respectively, to form an insulating structure.
  • the insulating material may include, but is not limited to, materials such as silicon oxide or oxynitride.
  • the insulating material may be deposited by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like.
  • insulating structures 17 may be formed by a chemical mechanical polishing (CMP) process to form insulating structures 17 .
  • CMP chemical mechanical polishing
  • step 905 the dummy gate structure is etched to expose the portion of the fin located in the channel region.
  • a patterned mask layer is formed on the first insulating structure 17 and the dummy gate structure 151, and the dummy gate structure 151 shown in FIG. 10D is etched, thereby exposing the second portion 111 of the fin located in the channel region.
  • the bottom insulating layer 12 is exposed.
  • step 906 the exposed fin structure is etched to reduce the width of the fin portion located in the channel region.
  • a patterned mask layer may be formed on the exposed second portion 111 of the fin, and the fin may be etched by dry etching, wet etching, or the like.
  • the etched structure of the second portion 111 of the fin is shown in FIG. 10E .
  • the fins 11 are not completely etched, and the purpose of the etching is to reduce the width of the fins 11 along the second direction Y. Therefore, in a preferred implementation manner, an atomic layer etching (ALE) method is used to etch the fin structure. In this way, the etching amount of the fins 11 can be precisely controlled, so that while the width of the fins 11 in the second direction y can be reduced, the etching amount of the fins in the third direction Z can also be reduced.
  • ALE atomic layer etching
  • the fin material can be etched away.
  • this step can be etched by 2 nm to 3 nm, so that the width of the fin 11 along the second direction Y is about 4 nm to 5 nm.
  • Step 907 forming a gate structure in the channel region.
  • an HK dielectric layer may be deposited in the channel region first.
  • Specific materials of the HK dielectric layer may include, but are not limited to, Lao, ALO, ZrO, TiO, SiO and other materials.
  • the metal material may include an N-gate metal material forming an N-type field effect transistor, or a P-gate metal material forming a P-type field effect transistor.
  • the N gate metal material may include but not limited to: Ti, Ag, Al, TiAlN, TaCN, TaSiN, Mn, etc.
  • the P gate metal material may include but not limited to: TiN, TaN, Ru, Mo, Al, WN, etc.
  • step 908 the insulating structure is etched, metal material is deposited, and contact metal is formed to lead out the source electrode and the drain electrode.
  • the insulating structure 17 over the semiconductor structure 14 is etched to expose the upper surface of the semiconductor structure 14 away from the substrate.
  • a metal material is deposited on the exposed semiconductor structure 14 , and the excess metal material is removed by a CMP process to form a contact metal 16 .
  • the side of the contact metal 16 that is not in contact with the semiconductor structure 14 may be flush with the spacer structure 13 .
  • the FinFET structure shown in FIG. 5 is formed.
  • the fin is etched to reduce the width of the fin. It can be seen from the above process steps that the step of thinning the fin is after forming the source electrode and the drain electrode.
  • the fins in the first active region and the second active region are not thinned, and the original thickness remains unchanged during the production process, thereby ensuring the stress of the fins in the first active region and the second active region.
  • the production yield can also be improved. Thus, it is beneficial to improve the reliability of the FinFET.
  • FIG. 11 shows another method for fabricating a FinFET provided by an embodiment of the present application.
  • the structure of the FinFET fabricated by the FinFET fabricating method is shown in FIG. 8 .
  • For the process flow of manufacturing the FinFET reference may be made to the flow 1100 shown in FIG. 11 .
  • the technological process includes the following steps:
  • step 1101 a substrate is provided, and a fin structure is formed on the substrate.
  • Step 1102 forming a dummy gate structure and a spacer structure on the fin and the insulating layer.
  • step 1101 and step 1102 and the structure after the above two steps are completed are the same as the specific implementation shown in step 901 and step 902, you can refer to the specific implementation of step 901 and step 902 shown in FIG. 9, and will not be repeated here.
  • Step 1103 wrapping insulating material on both side walls of the exposed fins.
  • insulating materials may be deposited on the first active region A1 and the second active region A2, respectively.
  • the deposited insulating material is etched, so that the two sidewalls of the exposed first portion 110 of each fin are wrapped with the insulating material 142 .
  • the insulating material when the insulating material is deposited on the first active region A1 and the second active region A2, it is in contact with the spacer structure 13 respectively. In order to reduce the number of process steps, the insulating material in the contact portion with the spacer structure 13 may not be used. Etching is performed, that is, a layer of sidewall is further attached to the sidewall of the sidewall structure 13 , as shown in FIG. 12A . It can be understood that the material of the sidewall to which the sidewall structure 13 is attached is the same as the insulating material 142 wrapped by the fins.
  • the deposited insulating material may include, but is not limited to, silicon oxide or oxynitride and other materials.
  • the insulating material deposited in step 1103 may be the same material as that for forming the spacer structure 13 .
  • Step 1104 etch back the exposed fins, and grow a semiconductor structure on the etched fins.
  • the first part 110 and the first part 110 exposed by the fin 11 may be etched back first, so as to reduce the height of the first part 110 of the fin 110 along the third direction Z.
  • the height of the etched first portion 110 along the third direction Z is not lower than the upper surface of the insulating layer 12 .
  • the upper surface of the insulating layer 12 is the side of the insulating layer away from the substrate 10 along the third direction Z.
  • the upper surface of the exposed first portion 110 of the fin can be etched to be flush with the insulating layer 12 .
  • the semiconductor material is confined within the insulating material 142 for growth, so that the formed semiconductor structure can be a plurality of regular geometric structures.
  • the formed semiconductor structures 14 are insulated from each other, as shown in FIG. 12B .
  • step 903 The specific process of growing the semiconductor material refers to step 903, which will not be repeated here.
  • Step 1105 depositing insulating materials on the first active region and the second active region, respectively, to form a first insulating structure.
  • step 1106 the dummy gate structure is etched to expose the portion of the fin located in the channel region.
  • step 1107 the exposed fins are etched to reduce the width of the fin portions located in the channel region.
  • Step 1108 forming a gate structure in the channel region.
  • step 5-step 8 and the structure after the above two steps are completed are the same as the specific implementation shown in step 904-step 907, please refer to the specific implementation of step 904-step 907 shown in FIG.
  • the structure after the end of step 1108 is shown in FIG. 12C .
  • Step 1109 etching the first insulating structure and the insulating material limiting the growth position of each semiconductor structure to expose the outer surface of each semiconductor structure.
  • Step 1110 wrapping a metal material on the outer surface of the semiconductor structure.
  • the wrapped metal material may include, but is not limited to, copper, nickel, aluminum or alloys formed by any combination thereof, and the like.
  • metal materials may be deposited on the insulating layers 12 of the first active region A1 and the second active region A2 respectively, and the deposited metal materials cover the semiconductor structures 14 . Then, the metal material is etched, and only the part wrapping the outer surface of the semiconductor structure 14 remains, and the rest is etched away. After the metal material is etched, the insulating layer 12 between each two semiconductor structures 14 is exposed. The structure after step 1110 is shown in FIG. 12E .
  • Step 1111 forming a second insulating structure between every two semiconductor structures.
  • insulating materials may be further deposited on the first active area A1 and the second active area A2, respectively.
  • the deposited insulating material is then etched to expose the top surface of each semiconductor structure 14 , as shown in FIG. 6 .
  • a second insulating structure 18 is formed between every two semiconductor structures.
  • the bottom surface of the second insulating structure 18 located between every two semiconductor structures 14 is in contact with the insulating layer 12 , and the top surface may be flush with the top surface of the semiconductor structure 14 .
  • the insulating material is directly deposited on the semiconductor structure 14 and the insulating layer 12 , and then the insulating material on the top of the semiconductor structure 14 is etched At this time, along the second direction Y, the gap between the first insulating structure 17 and the semiconductor structure 16 is also filled with the above-mentioned second insulating structure 18 .
  • the second insulating structure 17 and the semiconductor structure 16 may not be provided with a second gap. Insulating structure 18 .
  • Step 1112 depositing a metal material on the top surface of the semiconductor structure and the top surface of the second insulating structure to form a contact metal to lead out the source electrode and the drain electrode.
  • a metal material is deposited on the exposed semiconductor structure 14 , and the excess metal material is removed by a CMP process to form the contact metal 16 .
  • the side of the contact metal 16 which is not in contact with the semiconductor structure 14 may be flush with the spacer structure 13 .
  • the FinFET structure shown in FIG. 8 is formed.
  • the deposited metal material may include, but is not limited to, copper, nickel, aluminum, or alloys formed by any combination thereof, and the like.
  • the semiconductor material is limited to the sealing surface formed by the insulating material.
  • the semiconductor structure can be made to have a regular structure.
  • the outer surface of the semiconductor structure is also wrapped with a metal material, so that the contact resistance of the transistor can be reduced and the driving current of the transistor can be improved.
  • the embodiments of the present application also provide a method for preparing a semiconductor wafer.
  • the wafer is used to form a first fin field effect transistor and a second fin field effect transistor.
  • the first fin field effect transistor may be the fin field effect transistor shown in FIG. 5 or the fin field effect transistor shown in FIG. 8 .
  • the width of the fin portion located in the channel region of the first fin field effect transistor is lower than the width of the fin portion located in the first active region and the second active region.
  • the widths of each part of the fin are the same.
  • part of the fins in the channel region on the wafer may be etched, and after this step is completed, gate structures are deposited on all the channel regions on the wafer.
  • the first fin field effect transistor and the second fin field effect transistor can be formed on the wafer.

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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Des modes de réalisation de la présente invention concernent un transistor à effet de champ à ailette et un procédé de préparation, le transistor à effet de champ à ailette comprenant : un substrat, et une région active et une région de canal qui sont formées sur le substrat ; et une ailette formée sur le substrat et traversant la région active et la région de canal. La largeur de l'ailette dans la région de canal est inférieure à la largeur de l'ailette dans la région active. L'adoption de la structure de transistor à effet de champ à ailette selon la présente invention peut améliorer la fiabilité du transistor à effet de champ à ailette tout en garantissant la vitesse de commutation.
PCT/CN2020/103855 2020-07-23 2020-07-23 Transistor à effet de champ à ailette et procédé de préparation WO2022016463A1 (fr)

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PCT/CN2020/103855 WO2022016463A1 (fr) 2020-07-23 2020-07-23 Transistor à effet de champ à ailette et procédé de préparation
CN202080101476.8A CN115699270A (zh) 2020-07-23 2020-07-23 鳍式场效应晶体管和制备方法

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130105867A1 (en) * 2011-10-31 2013-05-02 Chih-Jung Wang Method of fabricating field effect transistor with fin structure and field effect transistor with fin structure fabricated therefrom
CN104576385A (zh) * 2013-10-14 2015-04-29 中国科学院微电子研究所 一种FinFET结构及其制造方法
CN104701171A (zh) * 2013-12-05 2015-06-10 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN107123598A (zh) * 2016-02-25 2017-09-01 台湾积体电路制造股份有限公司 鳍式场效应晶体管及其制造方法
US20170278965A1 (en) * 2016-03-24 2017-09-28 Globalfoundries Inc. Methods for fin thinning providing improved sce and s/d epi growth
CN109755320A (zh) * 2017-11-08 2019-05-14 台湾积体电路制造股份有限公司 半导体器件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130105867A1 (en) * 2011-10-31 2013-05-02 Chih-Jung Wang Method of fabricating field effect transistor with fin structure and field effect transistor with fin structure fabricated therefrom
CN104576385A (zh) * 2013-10-14 2015-04-29 中国科学院微电子研究所 一种FinFET结构及其制造方法
CN104701171A (zh) * 2013-12-05 2015-06-10 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN107123598A (zh) * 2016-02-25 2017-09-01 台湾积体电路制造股份有限公司 鳍式场效应晶体管及其制造方法
US20170278965A1 (en) * 2016-03-24 2017-09-28 Globalfoundries Inc. Methods for fin thinning providing improved sce and s/d epi growth
CN109755320A (zh) * 2017-11-08 2019-05-14 台湾积体电路制造股份有限公司 半导体器件

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