TWI525713B - 非平面鰭式電晶體製造技術 - Google Patents

非平面鰭式電晶體製造技術 Download PDF

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TWI525713B
TWI525713B TW101134273A TW101134273A TWI525713B TW I525713 B TWI525713 B TW I525713B TW 101134273 A TW101134273 A TW 101134273A TW 101134273 A TW101134273 A TW 101134273A TW I525713 B TWI525713 B TW I525713B
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transistor
barrier material
ion implantation
material layer
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沙布哈許Ｍ 喬斯
麥克 哈登多夫
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英特爾公司
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Description

非平面鰭式電晶體製造技術
本發明係關於電晶體製造技術，特別是關於非平面鰭式電晶體之製造技術。
發明背景
本文說明之實施例大致上係有關於微電子裝置之製造領域，更明確言之，係有關於非平面電晶體的製造技術。
依據本發明之一實施例，係特地提出一種方法包含於一非平面電晶體內在多個電晶體鰭上形成一共形阻擋材料層；去除該共形阻擋材料層的一部分以暴露出該等多個電晶體鰭中之至少一者；在該至少一個暴露出之電晶體鰭上執行一離子植入；及去除該共形阻擋材料層。
100‧‧‧非平面電晶體
102‧‧‧基體
104‧‧‧絕緣區域
1121-2‧‧‧電晶體鰭
1141-2‧‧‧頂面
1161-2、1181-2‧‧‧側壁
1321-3‧‧‧電晶體閘極
1341-2‧‧‧閘極介電質層
1361-3‧‧‧閘極電極
142‧‧‧阻擋材料層
144、146‧‧‧箭頭
148‧‧‧共形阻擋材料層
200‧‧‧流程圖
210-260‧‧‧處理方塊
H‧‧‧高度
本文揭示之主旨係特別指出且於說明書的結論部分獨特地請求專利。本文揭示之前述及其它特徵從後文詳細說明部分及隨附之申請專利範圍結合附圖將變得更加顯然易明。須瞭解附圖僅闡釋依據本文揭示的若干實施例，因此不得視為限制其範圍。將透過使用附圖以額外特定規格及細節描述本文揭示，使得更容易確定本文揭示之優點，附圖中：圖1為非平面電晶體之透視圖。
圖2例示說明如技藝界已知之非平面鰭式電晶體的體現技術之頂視平面圖。
圖3例示說明如技藝界已知之非平面鰭式電晶體的體現技術之側視剖面圖。
圖4例示說明依據本文揭示之一實施例，沈積一共形阻擋層在多個非平面鰭式電晶體上之側視剖面圖。
圖5例示說明依據本文揭示之一實施例，圖4的該共形阻擋層之一部分已被去除及暴露出非平面鰭式電晶體係以摻雜劑植入之側視剖面圖。
圖6為依據本文揭示之一實施例使用一共形阻擋層以植入擇定的非平面鰭式電晶體的方法之流程圖。
詳細說明
於後文詳細說明部分中，參考附圖且以例示說明顯示其中可實施本案所請主旨的特定實施例。此等實施例係以足夠細節描述以使得熟諳技藝人士實現該主旨。但須瞭解各個實施例雖然相異但非必要為彼此互斥。舉例言之，此處未悖離本案所請主旨的精髓及範圍，關聯一個實施例所述特定特徵、結構、或特性可在其它實施例中體現。於本說明書中述及「一個實施例」或「一實施例」表示關聯該實施例所述之一特定特徵、結構、或特性係含括於涵蓋於本發明的至少一個體現。因此，片語「一個實施例」或「一實施例」的使用並非必要係指同一個實施例。此外，須瞭解未悖離本案所請主旨的精髓及範圍，在各個所揭示 之實施例內部的個別元件之位置或排列可經修正。因此後文詳細說明部分並非取作限制性意義，主旨之範圍僅受隨附之申請專利範圍連同隨附之申請專利範圍的完整相當物之範圍所界定。於附圖中，類似的元件符號係指數幅圖式間相同的或相似的元件或功能，及其中所述元件並非必要彼此照比例繪製，反而個別元件可放大或縮小以便更容易瞭解於本文說明脈絡的各元件。
於非平面電晶體諸如三閘極電晶體及FinFET的製造中，非平面半導體本體可用來形成具有極小型閘極長度(例如小於約30奈米)的能夠完全耗盡的電晶體。此等半導體本體通常為鰭形，因此俗稱作電晶體「鰭」。例如於三閘極電晶體中，該等電晶體鰭具有一頂面及形成在一龐大半導體基體或絕緣體上矽基體上的兩相對的側壁。閘極介電質可形成在該半導體本體的頂面及側壁上，及一閘極電極可形成在該半導體本體的頂面上的閘極介電質上方，及相鄰於該半導體本體的側壁上的閘極介電質。如此，因閘極介電質及閘極電極係相鄰於該半導體本體的三面，故形成三個分開通道及閘極。由於形成三個分開通道，故當該電晶體被導通時該半導體本體可被完全耗盡。至於finFET電晶體，該閘極材料及電極只接觸該半導體本體的側壁，因而形成兩個分開通道(而非於三閘極電晶體的三個)。
本文揭示之實施例係有關於該等非平面電晶體內部的鰭之摻雜，其中一共形阻擋材料層可用以達成非平面鰭式電晶體內部的實質上均勻摻雜。
圖1為形成在一基體上，含括多個閘極形成在電晶體鰭上的多個非平面電晶體1001及1002(顯示為「集合」)。於本文揭示之一實施例中，基體102可為單晶矽基體。基體102也可為其它型別的基體，諸如絕緣體上矽(SOI)、鍺、砷化鎵、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、銻化鎵等，其中之任一者可與矽組合。
顯示為三閘極電晶體的非平面電晶體1001及1002各自包括電晶體鰭1121及1122，在電晶體鰭1121及1122以及非平面電晶體1001及1002間可具有絕緣區域104，諸如矽氧化物(SiO2)。如熟諳技藝人士所將瞭解，絕緣區域104可藉任一種已知之製法形成。
電晶體鰭1121及1122各自可具有一頂面1141及1142及一對橫向相對的側壁，分別為側壁1161及1162及兩相對側壁1181及1182。
如圖1進一步顯示，於電晶體鰭1121及1122各自上方可形成至少一個電晶體閘極1321、1322、1323。電晶體閘極1321、1322、1323分別地可藉在電晶體鰭側壁1161及1162及兩相對電晶體鰭側壁1181及1182上方及鄰近形成閘極介電質層1341及1342而製成。閘極電極1361、1362、1363可分別地形成在閘極介電質層1341及1342上。於本文揭示之一個實施例中，電晶體鰭1121及1122分別地係於實質上垂直電晶體閘極1321、1322、1323之方向行進。
閘極介電質層1341及1342可從任一種眾所周知的閘極介電質材料製成，包括但非限於二氧化矽(SiO2)、氧 氮化矽(SiOxNy)、氮化矽(Si3N4)、及高k介電質材料諸如氧化鉿、氧化鉿矽、氧化鑭、氧化鑭鋁、氧化鋯、氧化鋯矽、氧化鉭、氧化鈦、氧化鋇鍶鈦、氧化鋇鈦、氧化鍶鈦、氧化釔、氧化鋁、氧化鉛鈧鉭、及鈮酸鉛鋅。如熟諳技藝人士將瞭解，閘極介電質層1341及1342可藉眾所周知的技術製成，諸如沈積閘極電極材料，諸如化學氣相沈積(CVD)、物理氣相沈積(PVD)、原子層沈積(ALD)，及然後使用眾所周知的微影術及蝕刻技術而圖案化該閘極電極材料。
閘極電極1361、1362、1363可由任一種適當的閘極電極材料製成。於本文揭示之一實施例中，閘極電極1361、1362、1363可從下列材料製成，包括但非限於多晶矽、鎢、釕、鈀、鉑、鈷、鎳、鉿、鋯、鈦、鉭、鋁、碳化鈦、碳化鋯、碳化鉭、碳化鉿、碳化鋁、其它金屬碳化物、金屬氮化物、及金屬氧化物。如熟諳技藝人士將瞭解，閘極電極1361、1362、1363可藉眾所周知的技術製成，諸如藉全面性沈積閘極電極材料，及然後使用眾所周知的微影術及蝕刻技術而圖案化該閘極電極材料。
源極區及汲極區(圖中未顯示)可分別地形成在閘極電極1361、1362、1363的兩相對側的電晶體鰭1121及1122中。該等源極區及汲極區可藉摻雜電晶體鰭1121及1122形成。如熟諳技藝人士將瞭解，摻雜係將雜質導入半導體材料中用以改變其傳導性及電子性質的方法。此項目的通常係藉P型離子(例如硼)或N型離子(例如磷)的離子植入達成，合稱作「摻雜劑」。
為了達成沿電晶體鰭1121及1122的高度H(參考圖3)之一均勻摻雜，摻雜劑可以與電晶體鰭1121及1122的任一側(例如朝向側壁1161/1162及朝向側壁1181/1182)夾角而植入電晶體鰭1121及1122。藉由以與電晶體鰭1121及1122的任一側夾角而植入摻雜劑，摻雜劑主要係經由橫向相對的側壁對植入，例如電晶體鰭側壁1161及1181及兩相對電晶體鰭側壁1162及1182(參考圖1)。如熟諳技藝人士將瞭解，從電晶體鰭1121及1122各側邊的相同植入可達成橫過電晶體鰭1121及1122之高度H的均勻摻雜(參考圖3)，此點對非平面電晶體(例如圖1之非平面電晶體1001及1002)的最佳效能具有關鍵重要性。須瞭解植入可垂直於基體102，亦即實質上直接植入電晶體鰭頂面1141及1142。
如圖2及圖3所示，於植入摻雜劑之習知方法中，不欲植入摻雜劑的區(顯示為電晶體鰭1121)可以相當厚的阻擋材料層142諸如光阻材料覆蓋。為求清晰，如圖1所示，絕緣區域104或基體102中之任一者皆係例示說明於圖2及3，及閘極電極係僅只標示為元件136。
阻擋材料層142可使用已知之沈積及光刻技術形成，其中該阻擋材料層142可沈積於整個結構上方，接著為使用光刻技術形成蝕刻阻罩，及部分阻擋材料層142被蝕刻去除以暴露期望區(亦即電晶體鰭1122)。但雖然阻擋材料層142可成功地阻擋電晶體鰭1121的植入，但阻擋材料層142的相當厚度也可能遮掩且阻擋期望植入的電晶體鰭1122的若干植入。受阻擋的離子植入係以虛線箭頭146例示說明。 不受阻擋的離子植入係以實線箭頭144例示說明。
如圖3可知，電晶體鰭1122的植入被部分阻擋(亦即箭頭146)可能導致沿電晶體鰭1122高度H的非期望之不均勻摻雜。此項議題的一個解決方案係在暴露區與非暴露區間利用較大間距，使得對電晶體鰭1122的植入的阻擋不會出現。但如熟諳技藝人士將瞭解，此種解決方案係與持續地縮小微電子裝置的尺寸的期望相反。
圖4及5例示說明本文揭示之一個實施例。如圖4所示，阻擋層148可共形地沈積在電晶體鰭1121及1122上。如熟諳技藝人士將瞭解，共形沈積將導致共形阻擋材料層148在電晶體鰭1121及1122表面上具有實質上相等厚度(例如分別於側壁1161及1181頂面1141上，及於側壁1162及1182頂面1142上)。為求清晰，如圖1所示，絕緣區域104及基體102皆非如圖4及5之例示說明，閘極電極係單純標示為元件136。
共形阻擋材料層148可包含可阻擋擇定的摻雜劑植入之任一種材料。於一個實施例中，共形阻擋材料層148可為介電質材料，包括但非限於二氧化矽、氮化矽、碳化矽、氧氮化矽、氧碳化矽、氰化矽、及氧氰化矽。如將瞭解，其它材料諸如金屬，包括原子層沈積的氮化鈦也可用作為共形阻擋材料層148。共形阻擋材料層148可以已知之共形沈積技術製成，包括但非限於化學氣相沈積(CVD)、原子層沈積(ALD)等。須瞭解共形阻擋材料層148須夠厚以阻擋植體材料。於一個實施例中，共形阻擋材料層148可大於 約2奈米。此外，共形阻擋材料層148須夠薄以在電晶體鰭(例如元件1141及1142)間形成一共形層。舉例言之，若電晶體鰭分隔40奈米，則共形阻擋材料層148的厚度須小於約20奈米。
如圖5所示，部分共形阻擋材料層148可被去除以暴露出期望用於植入的電晶體鰭(例如電晶體鰭1122)。如熟諳技藝人士將瞭解，此項目的可藉以光刻技術形成蝕刻阻罩且蝕刻去除共形阻擋材料層148的擇定部分達成。
如圖5可知，許可沿電晶體鰭1122高度H的均勻摻雜，原因在於摻雜劑離子可從電晶體鰭1122兩側(例如朝向側壁1161/1162及朝向側壁1181/1182)均勻地植入。受阻擋的離子植入係以虛線箭頭146例示說明。不受阻擋的離子植入係以實線箭頭144例示說明。
於摻雜劑離子植入期間，使用共形阻擋材料層148的一種方法之一實施例係例示說明於圖圖6的流程圖200。如於方塊210定義，一共形阻擋層可形成在非平面電晶體的電晶體鰭上。如於方塊220定義，光阻材料可在該共形阻擋層上的至少一區圖案化。如於方塊230定義，於未藉該光阻材料覆蓋的至少一區中，該共形阻擋層諸如可藉蝕刻去除以暴露出欲藉離子植入而摻雜的至少一個電晶體鰭。如於方塊240定義，該光阻材料可被去除。如於方塊250定義，該至少一個電晶體鰭然後藉離子植入摻雜。如於方塊260定義，然後去除該共形阻擋材料層。
須瞭解本文揭示之主旨並非必要限於圖4及5例 示說明的特定應用。如熟諳技藝人士將瞭解，該主旨可應用至其它微電子裝置製造用途。又復，該主旨也可用在微電子裝置製造領域以外的任何適當應用。
已經以細節敘述本發明之實施例，須瞭解由隨附之申請專利範圍界定的本發明不欲受前文詳細說明部分陳述的特定細節所限，原因在於未悖離其精髓及範圍可能做出多項顯見的變化。
1001-2‧‧‧非平面電晶體
102‧‧‧基體
104‧‧‧絕緣區域
1121-2‧‧‧電晶體鰭
1141-2‧‧‧頂面
1161-2、1181-2‧‧‧側壁
1321-3‧‧‧電晶體閘極
1341-2‧‧‧閘極介電質層
1361-3‧‧‧閘極電極

Claims (26)

  1. 一種用以形成一非平面電晶體之方法，其包含：形成包覆圍繞該非平面電晶體中的多個電晶體鰭之一閘極；於該等多個電晶體鰭上形成一共形阻擋材料層；去除該共形阻擋材料層的一部分，以暴露出該等多個電晶體鰭中之至少一者；在該至少一個暴露出之電晶體鰭上執行一離子植入，以在該閘極之相對側上形成一源極區域及一汲極區域；及去除該共形阻擋材料層。
  2. 如申請專利範圍第1項之方法，其中形成一共形阻擋層係包含形成一共形介電質阻擋材料層。
  3. 如申請專利範圍第2項之方法，其中形成一共形介電質阻擋層係包含形成一共形介電質阻擋材料層。
  4. 如申請專利範圍第1項之方法，其中去除該共形阻擋材料層的一部分，以暴露出該等多個電晶體鰭中之至少一者係包含：圖案化於該共形阻擋材料層的至少一個部分上之一光阻材料；蝕刻於未被該光阻材料覆蓋之區域中的該共形阻擋材料層；及去除該光阻材料。
  5. 如申請專利範圍第1項之方法，其中在該至少一個暴露 出之電晶體鰭上執行一離子植入，係包含在該至少一個暴露出之電晶體鰭上執行一夾角離子植入。
  6. 如申請專利範圍第5項之方法，其中在該至少一個暴露出之電晶體鰭上執行一夾角離子植入，係包含在該至少一個暴露出之電晶體鰭的相對側壁上執行一夾角離子植入。
  7. 如申請專利範圍第1項之方法，其中在該至少一個暴露出之電晶體鰭上執行一離子植入，係包含在該至少一個暴露出之電晶體鰭上執行一P型離子植入。
  8. 如申請專利範圍第1項之方法，其中在該至少一個暴露出之電晶體鰭上執行一離子植入，係包含在該至少一個暴露出之電晶體鰭上執行一N型離子植入。
  9. 一種用以形成一非平面電晶體之方法，該非平面電晶體具有多個電晶體鰭，該方法包含：形成包覆圍繞該等多個電晶體鰭之一閘極；在該等多個電晶體鰭上形成一共形阻擋材料層，使得該等多個電晶體鰭中之至少一者係由該共形阻擋材料層所覆蓋，且該等多個電晶體鰭中之至少一者係未被該共形阻擋材料層所覆蓋；及在未被該共形阻擋材料層所覆蓋的該至少一個電晶體鰭上執行一離子植入，以在該閘極之相對側上形成一源極區域及一汲極區域。
  10. 如申請專利範圍第9項之方法，其中形成該共形阻擋材料層係包含： 在該等多個電晶體鰭上沈積該共形阻擋材料層；及去除該共形阻擋材料層的一部分以暴露出該等多個電晶體鰭中之至少一者。
  11. 如申請專利範圍第10項之方法，其中去除該共形阻擋材料層的一部分以暴露出該等多個電晶體鰭中之至少一者係包含：圖案化於該共形阻擋材料層的至少一個部分上之一光阻材料；及蝕刻於未被該光阻材料覆蓋之區域中的該共形阻擋材料層。
  12. 如申請專利範圍第9項之方法，其係進一步包含：去除該共形阻擋材料層。
  13. 如申請專利範圍第9項之方法，其中形成一共形阻擋材料層係包含形成一共形介電質阻擋材料層。
  14. 如申請專利範圍第9項之方法，其中在該至少一個暴露出之電晶體鰭上執行一離子植入，係包含在該至少一個暴露出之電晶體鰭上執行一夾角離子植入。
  15. 如申請專利範圍第14項之方法，其中在該至少一個暴露出之電晶體鰭上執行一夾角離子植入，係包含在該至少一個暴露出之電晶體鰭的相對側壁上執行一夾角離子植入。
  16. 如申請專利範圍第9項之方法，其中在該至少一個暴露出之電晶體鰭上執行一離子植入，係包含在該至少一個暴露出之電晶體鰭上執行一P型離子植入。
  17. 如申請專利範圍第9項之方法，其中在該至少一個暴露出之電晶體鰭上執行一離子植入，係包含在該至少一個暴露出之電晶體鰭上執行一N型離子植入。
  18. 一種微電子裝置，其係包含：具有多個電晶體鰭之至少一個非平面電晶體，該至少一個非平面電晶體包含：一閘極，其係包覆圍繞該等多個電晶體鰭而形成；及一源極區域及一汲極區域，其形成於該閘極之相對側上，其中：該等多個電晶體鰭中之至少一者具有沿該電晶體鰭的該高度之一實質上均勻的離子摻雜，該摻雜係藉一種程序執行，該程序係包含：在該等多個電晶體鰭上形成一共形阻擋材料層，使得該等多個電晶體鰭中之至少一者係由該共形阻擋材料層所覆蓋，且該等多個電晶體鰭中之至少一者係未被該共形阻擋材料層所覆蓋；及在未被該共形阻擋材料層所覆蓋的該至少一個電晶體鰭上執行一離子植入，以形成該源極區域及該汲極區域。
  19. 如申請專利範圍第18項之微電子裝置，其中形成該共形阻擋材料層係包含：在該等多個電晶體鰭上沈積該共形阻擋材料層；及去除該共形阻擋材料層的一部分以暴露出該等多 個電晶體鰭中之至少一者。
  20. 如申請專利範圍第19項之微電子裝置，其中去除該共形阻擋材料層的一部分以暴露出該等多個電晶體鰭中之至少一者係包含：圖案化於該共形阻擋材料層的至少一個部分上之一光阻材料；蝕刻於未被該光阻材料覆蓋之區域中的該共形阻擋材料層。
  21. 如申請專利範圍第18項之微電子裝置，其係進一步包含：去除該共形阻擋材料層。
  22. 如申請專利範圍第18項之微電子裝置，其中形成一共形阻擋材料層係包含形成一共形介電質阻擋材料層。
  23. 如申請專利範圍第18項之微電子裝置，其中在該至少一個暴露出之電晶體鰭上執行一離子植入，係包含在該至少一個暴露出之電晶體鰭上執行一夾角離子植入。
  24. 如申請專利範圍第23項之微電子裝置，其中在該至少一個暴露出之電晶體鰭上執行一夾角離子植入，係包含在該至少一個暴露出之電晶體鰭的相對側壁上執行一夾角離子植入。
  25. 如申請專利範圍第18項之微電子裝置，其中在該至少一個暴露出之電晶體鰭上執行一離子植入，係包含在該至少一個暴露出之電晶體鰭上執行一P型離子植入。
  26. 如申請專利範圍第18項之微電子裝置，其中在該至少一個暴露出之電晶體鰭上執行一離子植入，係包含在該至 少一個暴露出之電晶體鰭上執行一N型離子植入。
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TW201324622A (zh) 2013-06-16
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EP2761648A4 (en) 2015-06-24
EP2761648B1 (en) 2020-06-10
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EP2761648A1 (en) 2014-08-06
KR101647324B1 (ko) 2016-08-10

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