CN104347502A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN104347502A
CN104347502A CN201310471462.7A CN201310471462A CN104347502A CN 104347502 A CN104347502 A CN 104347502A CN 201310471462 A CN201310471462 A CN 201310471462A CN 104347502 A CN104347502 A CN 104347502A
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nanowires
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CN104347502B (zh
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江国诚
徐廷鋐
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract

本发明提供了一种半导体器件及其制造方法。该方法包括提供包括衬底的前体，衬底具有第一和第二金属氧化物半导体（MOS）区。第一和第二MOS区分别包括第一和栅极区、半导体层堆叠件以及源极/漏极区。该方法还包括横向暴露并且氧化第一栅极区中的半导体层堆叠件以形成第一外氧化层和第一内纳米线组，以及暴露第一内纳米线组。第一高k/金属栅极（HK/MG）堆叠件包裹着第一内纳米线组。该方法还包括横向暴露并且氧化第二栅极区中的半导体层堆叠件以形成第二外氧化层和第二内纳米线组，以及暴露第二内纳米线组。第二HK/MG堆叠件包裹着第二内纳米线组。

Description

半导体器件及其制造方法
本申请与2013年8月1日提交的美国专利申请第13/957,102号相关，在此通过引用将其成为本申请的一部分。
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及半导体器件及其制造方法。
背景技术
半导体集成电路（IC）工业已经经历了指数型增长。IC材料和设计的技术进步已经产生了多代IC，其中，每一代都比上一代具有更小和更复杂的电路。在IC的发展过程中，功能密度（例如，每芯片面积上互连器件的数量）已经普遍增加，而几何尺寸（例如，通过制造工艺可制造的最小部件（或线））已经减小。这种按比例缩小的工艺通常通过提高生产效率和降低相关成本来提供益处。
按比例缩小也增加了加工和制造IC的复杂性，为了实现这些进步，对IC加工和制造中的类似发展也产生了需求。例如，三维晶体管已经被引入以替代平面晶体管。虽然现有的半导体器件和制造半导体器件的方法已经基本满足预期目的，但是它们不是在所有方面都完全令人满意。例如，将三维纳米结构引入栅极沟道提高了半导体器件工艺发展中的挑战。期望在这个领域具有改进。
发明内容
根据本发明的一个方面，提供了一种制造集成电路器件的方法，包括：提供前体，前体包括：具有第一金属氧化物半导体（MOS）区和第二MOS区的衬底、第一栅极区和第一源极/漏极区、以及第二栅极区和第二源极/漏极区，第一栅极区和第一源极/漏极区形成于第一MOS区中，第一栅极区包括半导体层堆叠件，第二栅极区和第二源极/漏极区形成于第二MOS区中，第二栅极区包括半导体层堆叠件，其中，半导体层堆叠件包括交替设置在衬底上方的一个或多个第一层以及一个或多个第二层；横向暴露第一栅极区中的半导体层堆叠件；氧化第一栅极区中的半导体层堆叠件以形成第一外氧化层和第一内纳米线组，第一内纳米线组中的第一纳米线从第一源极区延伸至相应的第一漏极区；去除第一外氧化层以暴露第一栅极区中的第一内纳米线组；形成包裹第一内纳米线组的第一高k/金属栅极（HK/MG）堆叠件；横向暴露第二栅极区中的半导体层堆叠件；氧化第二栅极区的半导体层堆叠件以形成第二外氧化层和第二内纳米线组，第二内纳米线组中的第二纳米线从第二源极区延伸至相应的第二漏极区；去除第二外氧化层以暴露第二栅极区中的第二内纳米线组；以及形成包裹第二内纳米线组的第二HK/MG堆叠件。
优选地，第一MOS区是P型金属氧化物半导体（PMOS）区。
优选地，第二MOS区是N型金属氧化物半导体（NMOS）区。
优选地，该方法还包括：在氧化第二栅极区的半导体层堆叠件中的第二层之前，去除第一层。
优选地，第一MOS区是NMOS区，而第二MOS区是PMOS区。
优选地，该方法还包括：在氧化第一栅极区的半导体层堆叠件中的第二层之前，去除第一层。
优选地，该方法还包括：通过以n型掺杂剂掺杂PMOS区中的半导体层堆叠件下面的部分衬底，形成第一抗穿通（APT）区。
优选地，该方法还包括：通过以p型掺杂剂掺杂NMOS区中的半导体层堆叠件下面的部分衬底，形成第二APT区。
优选地，第一内纳米线组包括在第一栅极区中平行且横向对齐的多个第一内纳米线。
优选地，第二内纳米线组包括包括在第二栅极区中平行且横向对齐的多个第二内纳米线。
优选地，第一内纳米线包括锗（Ge）。
优选地，第二内纳米线包括硅（Si）。
优选地，该方法还包括：在第一源极/漏极区和第二源极/漏极区中分别形成第一源极/漏极部件和第二源极/漏极部件。
根据本发明的另一方面，提供了一种集成电路器件，包括：衬底，衬底具有N型金属氧化物半导体（NMOS）区和P型金属氧化物半导体（PMOS）区；位于NMOS区中的第一栅极区和第一源极部件，第一源极部件通过第一栅极区与相应的第一漏极部件分开；以及位于PMOS区中的第二栅极区和第二源极部件，第二源极部件通过第二栅极区与相应的第二漏极部件分开，其中，第一栅极区包括具有第一半导体材料的多个第一纳米线组，第一纳米线组从第一源极部件延伸至相应的第一漏极部件，其中，第二栅极区包括具有第二半导体材料的多个第二纳米线组，第二纳米线组从第二源极部件延伸至相应的第二漏极部件，以及其中，NMOS区和PMOS区均包括位于纳米线组之间的至少一个器件内隔离区以及位于NMOS区和PMOS区中的每一个的一侧的至少一个器件间隔离区，器件间隔离区的深度大于器件内隔离区的深度。
优选地，第一半导体材料包括Si。
优选地，第二半导体材料包括SiGe。
优选地，该器件还包括：第一抗穿通（APT）区，形成于第一纳米线组的下方，第一APT注入有p型掺杂剂；以及第二APT区，形成于第二纳米线组的下方，第二APT注入有n型掺杂剂。
优选地，器件内隔离区的深度在40nm至60nm之间。
优选地，器件间隔离区的深度在60nm至120nm之间。
根据本发明的又一方面，提供了一种集成电路器件，包括：衬底，包括金属氧化物半导体（MOS）区；栅极区，设置在衬底上方；以及源极部件，通过栅极区与对应的漏极部件分开，其中，栅极区包括从源极部件延伸至相应的漏部件的多个纳米线组，其中，纳米线组包括选自由Si和SiGe组成的组的半导体材料，以及其中，MOS区包括位于纳米线组之间的至少一个器件内隔离区和位于MOS区的一侧的至少一个器件间隔离区，器件间隔离区的深度大于器件内隔离区的深度。
附图说明
当结合附图阅读时，根据以下详细说明来最佳理解本发明。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了论述的清楚，各个部件的尺寸可被任意增大或减小。
图1是根据本发明各个方面的制造集成电路（IC）器件中的N型金属氧化物半导体（NMOS）区和P型金属氧化物半导体（PMOS）区的方法实例的流程图。
图2A是根据本发明的一些实施例的器件前体的示意性立体图。
图2B和图2C分别是根据本发明的一些实施例的沿着图2A中的线A-A和线B-B得到的器件前体的截面图。
图3A是根据图1的方法构造的处在中间阶段的IC器件中的金属氧化物半导体（MOS）区的示意性立体图。
图3B和图4A至图6A是根据图1的方法构造的处于各个制造阶段的半导体器件沿着图3A中的线A-A得到的截面图。
图3C和图4B-6B是根据图1的方法构造的处于各个制造阶段的半导体器件沿着图3A中的线B-B得到的截面图。
图5C至图6C是根据图1的方法构造的处于各个制造阶段的半导体器件沿着图3A中的线C-C得到的截面图。
图7A至图15A是根据图1的方法构造的处于各个制造阶段的IC器件的NMOS区和PMOS区沿着图3A中的线A-A得到的截面图。
图7B至图15B是根据图1的方法构造的处于各个制造阶段的IC器件的NMOS区和PMOS区沿着图3A中的线B-B得到的截面图。
具体实施方式
为了执行本发明的不同特征，下面的公开提供了很多不同的实施例或实例。下面描述了组件和布置的特定实例以简化本发明。当然，这些仅仅是实例而不旨在限定。例如，在下面的说明书中，第一部件形成于第二部件上方或上面可包括第一部件和第二部件以直接接触的方式形成的实施例，也可包括附加的部件形成于第一部件和第二部件之间，使得第一部件和第二部件以不直接接触的方式形成的实施例。此外，本发明在各个实例中可能重复参考数字和/或字母。这种重复是为了简化和清楚的目的，但其本身并不表明论述的各个实施例和/或结构之间的关系。
此外，为了便于描述附图中所示的一个元件或部件与另一个元件或部件的关系，在此使用诸如“下方”、“下面”、“下部的”、“上面”、“上部的”等空间相关术语。除了附图中描述的方位，空间相关术语旨在包含器件在使用或操作中的不同方位。例如，如果附图中的器件被翻转过来，那么被描述为在其他元件或部件“下面”或“下方”的元件将被定位为在其他元件或部件“上面”。因此，示例性的术语“下面”可包含上面和下面的两个方位。装置可另外被调整（旋转90度或其他方位），而在此使用的空间相关描述符可同样地作相应地解释。
本发明针对但不限于包括p型金属氧化物半导体（PMOS）器件和N型金属氧化物半导体（NMOS）器件的互补金属氧化物半导体（CMOS）器件。下面的公开将继续以CMOS器件的实例说明本发明的各个实施例。然而，应该理解，除了特别声明，本发明不应限于器件的特定类型。也应该理解，可在方法之前、之中和之后提供附加的步骤，而对于方法的其他实施例，描述的一些步骤可被替代或去除。
参见图1和图2A至图2C，方法100以提供器件前体150的步骤102开始。器件前体150可以是用于制造诸如MOS区200、300和/或400（如图3至图15所示）的金属氧化物半导体（MOS）区的前体。器件前体150包括衬底210。衬底210可包括体硅。可选地，诸如晶体结构的硅或锗的元素半导体也可以包括于衬底210中。器件前体150也包括化合物半导体，诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；或它们的组合。可能的衬底210也包括绝缘体上半导体衬底，诸如绝缘体上硅（SOI）衬底、绝缘体上硅锗（SGOI）衬底以及绝缘体上锗衬底。例如，SOI衬底可通过注氧隔离（SIMOX）、晶圆接合和/或其他合适的方法来制造。
取决于设计需要，各种掺杂区也可包含于衬底210中。掺杂区可能掺杂诸如硼或BF2的p型掺杂剂。掺杂区也可掺杂诸如磷或砷的n型掺杂剂。掺杂区也可掺杂p型和n型掺杂剂的组合物。掺杂区可以P阱结构、N阱结构、双阱结构或采用凸起结构直接形成于衬底210上。
抗穿通（APT）区212可形成于衬底210的上部并位于半导体层堆叠件230的下面。可形成APT区212以防止器件穿通问题并且提供更好的泄露控制。在一些实例中，当器件前体150用于制造NMOS单元时，衬底210中的APT区212可掺杂诸如硼和/或BF2的p型掺杂剂。在一些实例中，当器件前体150用于制造PMOS单元时，衬底210中的APT区212可掺杂诸如磷和/或砷的n型掺杂剂。
参见图2A至图2C，器件前体150也可包括一个或多个隔离区220。隔离区220形成于衬底210上方以隔离有源区。例如，每个隔离区220都将半导体层堆叠件230彼此分离。可使用诸如浅沟槽隔离（STI）的传统隔离技术形成隔离区220以限定并且电隔离半导体层堆叠件。在一些实例中，隔离区220可包括氧化硅、氮化硅、氮氧化硅、气隙、其他适合的材料或它们的组合。隔离区220可通过任何适合的工艺形成。在一些实例中，STI的形成包括光刻工艺、在衬底210中蚀刻沟槽（例如，通过使用干蚀刻和/或湿蚀刻）以及用一种或多种电介质材料填充沟槽（例如，通过使用化学汽相沉积工艺）以形成隔离区220。在一些实例中，填充后的沟槽可具有诸如填充有氮化硅或氧化硅的热氧化衬层的多层结构。在一些实施例中，执行化学机械抛光（CMP）工艺以去除过多的介电质材料并且使隔离区的顶面平坦化。
如图2A所示，设置在器件前体150侧面的隔离区是器件间隔离区，而设置在半导体层堆叠件230之间的隔离区是器件内隔离区。在一些实施例中，器件间隔离区的深度（D1）大于器件内隔离区的深度（D2）。例如，如图2A所示，D1可在60nm至120nm的范围之内。D2可在40nm至60nm的范围之内。
仍参见图2A至图2C，器件前体150包括形成于衬底210上方的一个或多个半导体层堆叠件230。半导体层堆叠件230的形成工艺可包括光刻和蚀刻工艺。光刻工艺可包括形成覆盖衬底的光刻胶层（抗蚀剂）、使光刻胶曝光形成图案、执行曝光后烘烤工艺以及使光刻胶显影以形成包含光刻胶的掩模元件。蚀刻工艺可包括任何合适的干蚀刻和/或湿蚀刻方法。在开槽工艺之后，可外延生长半导体层堆叠件230。在一些实施例中，衬底210凹进部分的厚度（T）可在30nm至50nm范围之内。可选地，半导体层堆叠件230可通过图案化并且蚀刻沉积覆盖绝缘层的硅层（例如，SOI衬底的硅-绝缘体-硅堆叠件中上面的硅层）形成。
如图2A至图2C所示，半导体层堆叠件230可包括多个半导体层。每个半导体层都具有基本彼此不同的厚度。半导体层堆叠件230可包括锗（Ge）、硅（Si）、砷化镓（GaAs）、硅锗（SiGe）、磷砷化镓（GaAsP）或其他适合的材料。半导体层堆叠件230可通过外延生长工艺来沉积，诸如化学汽相沉积（CVD）、汽相外延（VPE）、超高真空（UHV）-CVD、分子束外延（MBE）和/或其他适合的工艺。然后，可使用CMP工艺平坦化包括半导体层堆叠件230的器件前体150的表面。
参见图2B，器件前体150的半导体层堆叠件230可包括交替堆叠在彼此上方的一个或多个第一层232以及一个或多个第二层234。在一些实施例中，第一层232可包括SiGe。第二层234可包括Si。在一些实施例中，半导体层堆叠件230可包括如从底部到顶部的SiGe（232）/Si（234）/SiGe（232）/Si（234）的交替结构。在一些实施例中，第一层232的厚度范围在5nm至10nm之间。第二层234的厚度范围在5nm至15nm之间。在一些实施例中，第一层232的厚度可彼此不同。第二层234的厚度可彼此不同。在一些实施例中，第一层SiGe232中Ge的百分比可在20%至50%之间。在一些实施例中，第一层SiGe232中的一些层的Ge浓度可与其他层的Ge浓度不同。
参见图2A至图2C，衬底210包括源极/漏极区250和栅极区248。源极/漏极区250被栅极区248分开。
参见图1和图3A至3C，方法100进行至步骤104，通过使部分隔离区220凹进以形成凹槽240，从而横向暴露半导体层堆叠件230。开槽工艺可包括干蚀刻工艺、湿蚀刻工艺和/或它们的组合。开槽工艺可包括选择性湿蚀刻或选择性干蚀刻。在一些实施例中，可对隔离区220进行开槽直到可露出整个半导体层堆叠件230。应该指出，下面的论述将把器件前体150当作MOS区200。
参见图1和图4A至4B，方法100进行至步骤105，在栅极区248中形成伪栅极242和硬掩模244。伪栅极242和硬掩模244可形成于栅极区248中的半导体层堆叠件230和隔离区220上方。伪栅极242可包括多晶硅。伪栅极242可通过任何适合的工艺或步骤形成。例如，伪栅极242可通过包括沉积、光刻图案化和/或蚀刻工艺的步骤形成。沉积工艺包括CVD、PVD、ALD、其他适合的方法和/或它们的组合。硬掩模244可包括氧化硅、氮化硅、氮氧化硅或其他适合的介电质材料。硬掩模244可以是单层或多层。硬掩模244可通过CVD、ALD或其他任何合适的方法来形成。
参见图1和4B，方法100进行到步骤106，在MOS区200中形成公共源极/漏极凹槽252。参见图3A和4B，可沿着线C-C方向去除源极/漏极区250中的部分半导体层堆叠件230、隔离区220和/或衬底210以利用伪栅极242和硬掩模244在MOS区200中形成公共源极/漏极凹槽252。公共源极/漏极凹槽252可通过干蚀刻工艺、湿蚀刻工艺中的任何一种和/或它们的合适组合形成。开槽工艺也可包括选择性湿蚀刻或选择性干蚀刻。开槽工艺可包括多种蚀刻工艺。
仍参见图4B，在形成伪栅极242和硬掩模244之后，可沿着栅极区248形成侧壁间隔件246。侧壁间隔件246可包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅的介电质材料或它们的组合。侧壁间隔件246也可包括多层。通常形成侧壁间隔件的方法包括在栅极区248上方沉积介电质材料。然后可各向异性回蚀介电质材料。回蚀工艺可包括多步骤蚀刻以实现蚀刻的选择性、灵活性和期望的过蚀刻控制。
参见图1和图5A至图5C，方法100进行到步骤108，在公共源极/漏极凹槽252中形成冠形源极/漏极部件254。半导体材料在公共源极/漏极沟槽252中外延生长以形成冠形源极/漏极部件254。半导体材料包括Ge、Si、GaAs、AlGaAs、SiGe、GaAsP或其他适合的材料。冠形源极/漏极部件254可通过一个或多个外延生长或外延工艺形成。冠形源极/漏极部件254可在外延工艺中原位掺杂。例如，外延生长的SiGe源极/漏极部件254可掺杂硼；而外延生长的Si源极/漏极部件254可掺杂碳以形成Si：C源极/漏极部件、掺杂磷以形成Si：P源极/漏极部件或掺杂碳和磷以形成SiCP源极/漏极部件。在一些实施例中，执行注入工艺（例如，结注入工艺）以掺杂冠形源极/漏极部件254。可执行一个或多个退火步骤以活化源极/漏极外延部件。在一些实施例中，冠形源极/漏极部件是冠形源极区，而其他冠形源极/漏极部件是冠形漏极区。冠形源极部件与冠形漏极部件被栅极区248隔离。
虽然在本发明中只示出了公共源极/漏极凹槽252和冠形源极/漏极部件254，但是源极/漏极凹槽252也可以以被隔离区220分开的单独类型形成，称为单独源极/漏极凹槽252。单独的源极/漏极部件254可通过在单独的源极/漏极凹槽252中外延生长半导体材料而形成。
参见图1和图6A至图6C，方法100进行到步骤110，在冠形源极/漏极部件254上方形成层间电介（ILD）层256。ILD层256可包括氧化硅、氮氧化物或其他适合的材料。ILD层256可包括单层或多层。ILD层256可通过适合的技术（诸如，CVD、ALD和旋涂技术）形成。在形成ILD层256之后，可执行CMP工艺以去除过多的ILD层256并且使ILD层256的顶面平坦化。在一些实施例中，如图6A至图6C所示，硬掩模244也可在CMP工艺中被去除。
参见图1和图6A至图6C，方法进行到步骤112，形成图案化的硬掩模258以覆盖MOS区200。在步骤110去除过多的ILD层256并且使MOS区200的表面平坦化之后，MOS区200的表面可覆盖有图案化的硬掩模258以防止MOS区200在其他区域内同时实施的工艺过程中受到影响。硬掩模258可包括氧化硅、氮化硅、氮氧化硅或其他任何适合的介电质材料。硬掩模258可包括单层或多层。硬掩模258可通过CVD、ALD或其他任何合适的方法来形成。
参见图7至图15，不只一个MOS区200可用于在IC器件500中同时或分别形成不同类型的MOS区。在本发明示出的一些实例中，可采用图1所示的方法100在IC器件500中形成NMOS区300和PMOS区400。可选地，MOS区300可以是PMOS区300，而MOS区400可以是NMOS区400。
参见图1和图7A至图7B，方法100进行到113，去除伪栅极242以暴露栅极区248中的半导体层堆叠件230。在PMOS区400中，栅极区248被称为栅极区448。可去除PMOS区400的伪栅极242以暴露图7B所示的栅极堆叠件449。栅极堆叠件449可包括设置在栅极区448中的半导体层堆叠件230。伪栅极242可通过诸如蚀刻工艺的任何合适的方法来去除。蚀刻工艺可包括选择性湿蚀刻或选择性干蚀刻，使得伪栅极242相对于栅叠件449和侧壁间隔件246具有充分的蚀刻选择性。可选地，伪栅极242可通过包括光刻图案化和回蚀的一系列工艺形成凹陷。
参见图1和图8A至图8B，方法100进行到步骤114，氧化PMOS区400的栅极区448中的部分栅极堆叠件449以形成外氧化层436和内纳米线438。在一些实施例中，可对栅极堆叠件449的第一层232和第二层234执行热氧化工艺。在一些实例中，热氧化工艺在有氧环境中进行。在一些实例中，热氧化工艺可在蒸汽和有氧环境的组合中进行。热氧化工艺可在蒸汽和有氧环境的组合、一个大气压以及400℃到600℃之间的温度下进行。热氧化工艺可能进行30至180分钟。
在热氧化工艺过程中，第一层232和第二层234中的元素被氧化以形成外氧化层436。在一些实施例中，外氧化层436可包括氧化硅（SiOx），其中，x是原子百分比形式的氧组成。在一些实施例中，第一层232中的另一元素可在氧化工艺过程中扩散至外氧化层436内部以形成半导体核心部分438。半导体核心部分438可沿着线B-B方向（如图3A所示）连续地形成并且连接至位于栅极区448两侧的冠形源极/漏极部件254。应该指出，下面的论述将把半导体核心部分438称作内半导体纳米线438。在一些实施例中，内半导体纳米线438可以是Ge纳米线438。形成外氧化层436以包裹内半导体纳米线438。在一些实施例中，不只一个内半导体纳米线438可形成于外氧化层436的纳米线组439中。
参见图8A至图8B，在一些实例中，内半导体纳米线438的直径可在2nm至15nm之间。外氧化层436和/或内半导体纳米线438的尺寸和形状可随着不同的工艺条件（诸如，热氧化温度和时间）而不同。
参见图1和图9A至图9B，方法100进行到步骤116，去除外氧化层436以暴露PMOS区400中的一个或多个内半导体纳米线438。去除工艺可包括干蚀刻、湿蚀刻或它们的组合。例如，对外氧化层436执行相对于内半导体纳米线438具有充分蚀刻选择性的选择性湿蚀刻或选择性干蚀刻。在去除外氧化层436之后，PMOS区400的栅极区448被配置为包括形成于纳米线组439中的一个或多个内半导体纳米线438。
参见图1和图10A至图10B，方法100进行到步骤118，在PMOS区400中形成界面层（IL）462/高k（HK）介电层464/金属栅极（MG）466。在一些实施例中，可形成一个或多个IL462以包裹一个或多个内纳米线438并且覆盖侧壁间隔件246。IL462可通过诸如ALD、化学汽相沉积CVD和臭氧氧化的任何合适的方法来沉积。IL462可包括氧化物、HfSiO和氮氧化物。在一些实施例中，隔离区220与IL462之间的界面在热处理之后不能被观察到。一个或多个HK介电层464可通过任何适合的技术（诸如，ALD、CVD、金属有机CVD（MOCVD）、物理汽相沉积（PVD）、热氧化、它们的组合或其他适合的技术）沉积在IL462上方并包裹IL462。HK介电层464可包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3（STO）、BaTiO3（BTO）、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、（Ba，Sr）TiO3（BST）、Al2O3、Si3N4、氮氧化物（SiON）或其他适合的材料。IL462可包括氧化物、HfSiO和氮氧化物。在一些实施例中，IL462与HK介电层464之间的界面在热处理之后不能被观察到。
MG层466包括单层或多层，诸如金属层、衬垫层、润湿层和粘合层。MG层466可包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、WN、Cu、W或任何适合的材料。MG层466可通过ALD、PVD、CVD或其他适合的工艺形成。执行CMP工艺以去除过多的MG层466。CMP工艺给PMOS区400中的栅极区448和ILD层256提供基本平坦的顶面。在沉积IL462/HK层464/MG466之后，如图10B所示，栅极区448可包括一个或多个半导体纳米线438以及IL462/HK层464/MG466。
参见图10A至图10B，在一些实施例中，在步骤118中，NMOS区300上方的硬掩模258可在通过CMP工艺对PMOS区400的表面进行平坦化的过程中被去除。
参见图1和图11A至图11B，方法100进行到步骤120，在PMOS区400上方形成硬掩模468以防止PMOS区400在NMOS区300的后续处理过程中受到影响。硬掩模468包括氧化硅、氮化硅、氮氧化硅或其他任何适合的介电材料。硬掩模468可包括单层或多层。硬掩模468可通过CVD、PVD、ALD或其他任何合适的方法形成。
仍参见图11A至图11B，在一些实施例中，在步骤120中，可去除伪栅极242以暴露NMOS区300的栅极区348中的栅极堆叠件349。栅极堆叠件349可包括设置在NMOS区300的栅极区348中的半导体层堆叠件230。伪栅极242可通过诸如蚀刻工艺的任何合适的方法来去除。蚀刻工艺可包括选择性湿蚀刻或选择性干蚀刻，使得伪栅极242相对于栅堆叠件349和侧壁间隔件246具有充分的蚀刻选择性。可选地，伪栅极242可通过包括光刻图案化和回蚀的一系列工艺来形成凹陷。
参见图1和图12A至图12B，方法100进行到步骤122，选择性去除NMOS区300的第一层232。在一些实施例中，第一层32可包括SiGe，而SiGe可通过任何合适的蚀刻工艺（诸如，干蚀刻工艺、湿蚀刻工艺和/或它们的组合）去除。第一层232的去除工艺也可包括选择性湿蚀刻或选择性干蚀刻，使得相对于第二层234提供充分的蚀刻选择性。在一些实例中，选择性湿蚀刻或选择性干蚀刻可选择性地去除整个第一层232。干蚀刻和湿蚀刻工艺可具有能够被调整的蚀刻参数，诸如使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、源功率、RF偏压、RF偏置功率、蚀刻剂流速和其他适合的参数。干蚀刻工艺可包括使用氯基化学剂的偏压等离子体蚀刻工艺。其他干蚀刻剂气体可包括四氟化碳（CF4）以及三氟化氯（ClF3）。干蚀刻也可使用如DRIE（深反应离子蚀刻）的机制来各向异性地执行。化学汽相蚀刻可用作选择性蚀刻的方法，而蚀刻剂气体可包括氯化氢（HCl）、四氟化碳（CF4）以及混有氢气（H2）的气体。可在适当压力和温度下通过化学汽相沉积（CVD）执行化学汽相蚀刻。
参见图1和图13A至图13B，方法100进行到步骤124，氧化NMOS区300的栅极区348中的第二层234以形成外氧化层336和内半导体纳米线338。在一些实例中，热氧化工艺可在有氧环境中进行。在一些实例中，热氧化工艺可在蒸汽和有氧气环境的组合中进行。热氧化工艺可在蒸汽和氧气环境的组合中、一个大气压以及400℃到600℃之间的温度下进行。热氧化工艺可能进行30至180分钟。
在热氧化工艺过程中，可氧化第二层234的外部以形成外氧化层336。在一些实施例中，外半导体氧化层336可包括氧化硅（SiOx），其中，x是原子百分比形式的氧组成。在一些实施例中，第二层234的内部可在氧化工艺过程中扩散至外氧化层336内部以形成半导体核心338。半导体核心部分338可沿着线B-B方向（如图2A所示）连续地形成并且连接至位于栅极区348两侧的冠形源极/漏极部件254。应该指出，下面的论述将把半导体核心部分338当作内半导体纳米线338。在一些实施例中，内半导体纳米线338可以是Si纳米线338。可形成外氧化层336以包裹内半导体纳米线338。在一些实施例中，不只一个内半导体纳米线338形成于外氧化层336的纳米线组339中。
参见图13A-13B，在一些实例中，内半导体纳米线338的直径可在2nm至13nm之间。外半导体氧化层336和/或内半导体纳米线338的尺寸和形状可随着不同的诸如热氧化温度和时间的工艺条件而不同。
参见图1和图14A-14B，方法100进行到步骤126，去除外氧化层336以暴露NMOS区300中的一个或多个内半导体纳米线338。去除工艺可包括干蚀刻、湿蚀刻或它们的组合。例如，相对于内半导体纳米线338对外氧化层336执行的选择性湿蚀刻或选择性干蚀刻具有充分的蚀刻选择性。在去除外氧化层336之后，NMOS区300的栅极区348被配置为包括纳米线组339中的一个或多个内半导体纳米线338。
参见图1和图15A至图15B，方法100进行到步骤128，在NMOS区300中形成界面层（IL）362/高k（HK）层364/金属栅极（MG）366。形成一个或多个IL362以包裹一个或多个内纳米线338并且覆盖侧壁间隔件246。一个或多个HK电介质层364可沉积在IL362上方并且包裹IL362。用于形成IL362、HK电介质层364和MG层366的形成工艺和材料与图10A至图10B中所述的用于形成IL462、HK电介质层464和MG层466的形成工艺和材料基本类似。在一些实施例中，IL362与隔离区220之间的界面在热处理之后可能不被观察到。IL362与HK电介质层364之间的界面在热处理之后可能不被观察到。在沉积IL362/HK层364/MG366之后，栅极区348可包括一个或多个内半导体纳米线338以及IL362/HK层364/MG366。
仍参见图1和图15A至15B，在步骤128中，覆盖PMOS区400的硬掩模468可被去除，在一些实施例中，硬掩模468可通过CMP工艺在对NMOS区300的表面进行平坦化的过程中被去除。
根据图7至图15中的说明，虽然PMOS区400的纳米线结构的形成先于NMOS区300的纳米线结构的形成，但NMOS区300的纳米线结构的形成也可能先于PMOS区400的纳米线结构的形成。在一些实施例中，在NMOS区300的纳米线的形成过程中，首先形成硬掩模以覆盖PMOS区400。在一些实施例中，纳米线结构可只形成于NMOS区300中。在一些实施例中，纳米线结构可只形成于PMOS区400中。在一些实施例中，在NMOS区300和/或PMOS区400中不只形成一个纳米线。本领域技术人员应该理解，NMOS区300和PMOS区400可使用任何适合的工艺以任何合适的顺序和以任何适当的形貌形成。
在一些实施例中，NMOS区300的MG层366也可包括包裹IL362/HK层364结构的第一覆盖层。还可形成第一阻挡MG和n型功函数（NWF）MG以包裹第一覆盖层。PMOS区400的MG层466也可包括包裹IL462/HK层464结构的第二覆盖层。还可形成第二阻挡MG和p型功函数（PWF）MG以包裹第二覆盖层。第一和/或第二覆盖层可包括TiN。第一和/或第二阻挡MG包括TaN。NMOS区200的NWF MG可使用与PMOS区300的PWF MG层不同的金属层形成。在一些实例中，NWF MG包括TiAlC、TaAl和/或TiAl。PWF MG可包括TiN。
IC器件500的NMOS区300和/或PMOS区400还可经历CMOS或MOS技术处理以形成本领域已知的各种部件和区域。例如，后续处理可在衬底210上形成被配置为连接IC器件500的各种部件或结构的各种接触件/通孔/线和多层互连部件（例如，金属层和层间介电质）。例如，多层互连件包括诸如常规通孔或接触件的垂直互连件和诸如金属线的水平互连件。各种互连部件可采用包括铜、钨和/或硅化物的各种导电材料。在一个实例中，镶嵌或双镶嵌工艺用于形成与铜相关的多层互连结构。
附加的步骤可被提供于方法100之前、之中和之后，并且对于方法的其他实施例，描述的一些步骤可被替代或去除。
本发明提供了制造集成电路（IC）器件的方法的很多不同的实施例。该方法包括提供前体。前体包括具有第一和第二金属氧化物半导体（MOS）区的衬底；形成于第一MOS区中的第一栅极区和源极/漏极区，第一栅极区包括半导体层堆叠件；以及形成于第二MOS区中的第二栅极区和源极/漏极区，第二栅极区包括半导体层堆叠件。半导体层堆叠件包括交替地设置在衬底上方的一个或多个第一层以及一个或多个第二层。该方法还包括横向暴露第一栅极区的半导体层堆叠件；氧化第一栅极区的半导体层堆叠件以形成第一外氧化层和第一内纳米线组，第一内纳米线组中的第一纳米线从第一源极区延伸至相应的第一漏极区；去除第一外氧化层以暴露第一栅极区中的第一内纳米线组；形成包裹第一内纳米线组的第一高k/金属栅极（HK/MG）堆叠件；横向暴露第二栅极区的半导体层堆叠件；氧化第二栅极区的半导体层堆叠件以形成第二外氧化层和第二内纳米线组，第二内纳米线组中的第二纳米线从第二源极区延伸至第二漏极区；去除第二外氧化层以暴露第二栅极区中的第二内纳米线组；以及形成包裹第二内纳米线组的第二HK/MG堆叠。
在另一个实施例中，一种IC器件包括：具有N型金属氧化物半导体（NMOS）区和P型金属氧化物半导体（PMOS）区的衬底；NMOS区中的第一栅极区和第一源极部件，第一源极部件通过第一栅极区与相应的第一漏极部件分开；以及PMOS区中的第二栅极区和第二源极部件，第二源极部件通过第二栅极区与相应的第二漏极部件分开。第一栅极区包括具有第一半导体材料的多个第一纳米线组。第一纳米线组从第一源极部件延伸至相应的第一漏极部件。第二栅极区包括具有第二半导体材料的多个第二纳米线组。第二纳米线组从第二源极部件延伸至相应的第二漏极部件。每个NMOS区和PMOS区都包括位于纳米线组之间的至少一个器件内隔离区以及位于每个NMOS区和PMOS区的一侧的至少一个器件间隔离区。器件间隔离区的深度大于器件内隔离区的深度。
在又一个实施例中，一种IC器件包括包含金属氧化物半导体（MOS）区的衬底；设置在衬底上方的栅极区；以及通过栅极区与对应的漏极部件分开的源极部件。栅极区包括从源极部件延伸至相应的漏极部件的多个纳米线组。该纳米线组包括选自由Si和SiGe组成的组的半导体材料。MOS区包括位于纳米线组之间的至少一个器件内隔离区和位于MOS区的一侧的至少一个器件间隔离区。器件间隔离区的深度大于器件内隔离区的深度。
上面概述了若干实施例的特征，从而使得本领域技术人员能更好地理解本发明的各方面。本领域的技术人员应该意识到，他们能轻易地使用本发明作为基础，设计或改变用于实施与在此介绍的实施例相同的目的和/或获得相同的优势的其他工艺和结构。本领域的技术人员也应该意识到，这些等效结构没有背离本发明的精神与范围，并且在不背离本发明的精神与范围的情况下，在此他们可作出各种改变、替代和变化。

Claims (10)

1.一种制造集成电路器件的方法，所述方法包括：
提供前体，所述前体包括：
衬底，具有第一金属氧化物半导体（MOS）区和第二MOS区；
第一栅极区和第一源极/漏极区，形成于所述第一MOS区中，所述第一栅极区包括半导体层堆叠件；以及
第二栅极区和第二源极/漏极区，形成于所述第二MOS区中，所述第二栅极区包括所述半导体层堆叠件，
其中，所述半导体层堆叠件包括交替设置在所述衬底上方的一个或多个第一层以及一个或多个第二层；
横向暴露所述第一栅极区中的所述半导体层堆叠件；
氧化所述第一栅极区中的所述半导体层堆叠件以形成第一外氧化层和第一内纳米线组，所述第一内纳米线组中的第一纳米线从所述第一源极区延伸至相应的所述第一漏极区；
去除所述第一外氧化层以暴露所述第一栅极区中的所述第一内纳米线组；
形成包裹所述第一内纳米线组的第一高k/金属栅极（HK/MG）堆叠件；
横向暴露所述第二栅极区中的所述半导体层堆叠件；
氧化所述第二栅极区的所述半导体层堆叠件以形成第二外氧化层和第二内纳米线组，所述第二内纳米线组中的第二纳米线从所述第二源极区延伸至相应的所述第二漏极区；
去除所述第二外氧化层以暴露所述第二栅极区中的所述第二内纳米线组；以及
形成包裹所述第二内纳米线组的第二HK/MG堆叠件。
2.根据权利要求1所述的方法，其中，所述第一MOS区是P型金属氧化物半导体（PMOS）区。
3.根据权利要求1所述的方法，其中，所述第二MOS区是N型金属氧化物半导体（NMOS）区。
4.根据权利要求3所述的方法，还包括：
在氧化所述第二栅极区的所述半导体层堆叠件中的所述第二层之前，去除所述第一层。
5.根据权利要求1所述的方法，其中，所述第一MOS区是NMOS区，而所述第二MOS区是PMOS区。
6.根据权利要求5所述的方法，还包括：
在氧化所述第一栅极区的所述半导体层堆叠件中的所述第二层之前，去除所述第一层。
7.根据权利要求2所述的方法，还包括：
通过以n型掺杂剂掺杂所述PMOS区中的所述半导体层堆叠件下面的部分所述衬底，形成第一抗穿通（APT）区。
8.根据权利要求3所述的方法，还包括：
通过以p型掺杂剂掺杂所述NMOS区中的所述半导体层堆叠件下面的部分所述衬底，形成第二APT区。
9.一种集成电路器件，包括：
衬底，衬底具有N型金属氧化物半导体（NMOS）区和P型金属氧化物半导体（PMOS）区；
位于所述NMOS区中的第一栅极区和第一源极部件，所述第一源极部件通过所述第一栅极区与相应的第一漏极部件分开；以及
位于所述PMOS区中的第二栅极区和第二源极部件，所述第二源极部件通过所述第二栅极区与相应的第二漏极部件分开，
其中，所述第一栅极区包括具有第一半导体材料的多个第一纳米线组，所述第一纳米线组从所述第一源极部件延伸至相应的所述第一漏极部件，
其中，所述第二栅极区包括具有第二半导体材料的多个第二纳米线组，所述第二纳米线组从所述第二源极部件延伸至相应的所述第二漏极部件，以及
其中，所述NMOS区和所述PMOS区均包括位于纳米线组之间的至少一个器件内隔离区以及位于所述NMOS区和所述PMOS区中的每一个的一侧的至少一个器件间隔离区，所述器件间隔离区的深度大于所述器件内隔离区的深度。
10.一种集成电路器件，包括：
衬底，包括金属氧化物半导体（MOS）区；
栅极区，设置在所述衬底上方；以及
源极部件，通过所述栅极区与对应的漏极部件分开，
其中，所述栅极区包括从所述源极部件延伸至相应的所述漏部件的多个纳米线组，
其中，所述纳米线组包括选自由Si和SiGe组成的组的半导体材料，以及
其中，所述MOS区包括位于所述纳米线组之间的至少一个器件内隔离区和位于所述MOS区的一侧的至少一个器件间隔离区，所述器件间隔离区的深度大于所述器件内隔离区的深度。
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