CN1531071B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1531071B
CN1531071B CN2004100283810A CN200410028381A CN1531071B CN 1531071 B CN1531071 B CN 1531071B CN 2004100283810 A CN2004100283810 A CN 2004100283810A CN 200410028381 A CN200410028381 A CN 200410028381A CN 1531071 B CN1531071 B CN 1531071B
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distribution
semiconductor device
shielding film
circuit element
manufacture method
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CN1531071A (zh
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臼井良辅
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

一种半导体装置。其包括：层间绝缘膜(405)以及绝缘膜(409)；埋设在绝缘膜(409)内的配线(407、408a、408b)；载置在绝缘膜(409)上的电路元件(410a、410b)；覆盖电路元件(410a、410b)而形成的封闭膜(415)；覆盖封闭膜(415)而形成的导电性的遮蔽膜(416)。形成配线(408a、408b)与遮蔽膜(416)电连接的结构。

Description

半导体装置及其制造方法
技术领域
本发明涉及安装了电路元件的半导体装置及其制造方法。
背景技术
现在，随着移动电话、PDA、DVC、DSC这些便携式电子设备加速实现高性能化，也要求所述这些电子设备所使用的LSI要具有更强的功能和特性，因此，LSI的动作时钟脉冲也要实现高频率。另外，为了使这些电子设备更能满足市场化的要求，其必须要实现小型化、轻量化。为了实现所述目的需要高度集成的LSI。
为了安装这样小型的高频LSI就要缩短半导体芯片之间的距离形成高密度，因此就会产生杂波干扰增大这种问题，现在，发明了用金属封闭部件覆盖住半导体装置中的组件这种技术作为解决杂波干扰的方法。(例如，特开平5-47962号公报)。
在所述的专利文件1中发表的用金属封闭部件覆盖半导体装置的组件的技术中，因为封闭部件是作成与半导体装置分开的部件安装在线路基板上，因此，封闭部件形成之后的组件尺寸就会增大，造成不能实现小型化的问题。另外，因为封闭部件与半导体装置分开单独制造，所以也有生产效率低的问题。
本发明鉴于所述问题，目的是提供以简单的方法消除半导体装置的杂波干扰的技术。
然而，现在作为将高频波用LSI形成小型组件化的技术已知的有CSP(例特开2002-94247号公报)。在该公报中发表了安装高频用LSI的有系统组件。该组件是在基础基板上形成多层配线结构，在其上形成以高频LSI为主的电路元件。多层配线结构是将芯部基板或带树脂铜片进行层叠的结构。
可是，对于便携式电子设备使用这些现有的CSP难以实现现在理想水平的小型化、薄型化、轻量化。这是因为现有的CSP具有支持芯片的基板。由于存在支持基板，组件整体厚度就增加，会限制小型化、薄型化、轻量化，而且也使散热性能的改善受到一定的限制。
发明内容
鉴于所述问题，本申请人开发了名为ISB(Integrated System in Board；注册商标)的新组件。ISB是在组装以半导体裸芯片为中心的电子电路时，具有铜的配线图模同时不使用支持电路部件的芯部(基板)的单独具有无芯部(基板)系统的组件。在特开2002-110717号公报中记述着这种有系统组件。
图1是示意表示ISB的一例的结构图。图中为了容易理解ISB整体的结构只表示了单一的配线层，而实行的结构是形成多层配线层的层叠结构。该ISB形成通过由铜图模205组成的配线连接LSI裸芯片201、Tr裸芯片202以及芯片CR203的结构。LSI裸芯片201通过金导线204与引出电极和配线连接导通。在LSI裸芯片201的正下方设置导电糊206，通过该导电糊206将ISB安装在印刷配线基板上。ISB整体形成使用由环氧树脂等制成的树脂组件207封装的结构。
根据该组件可以获得以下的优点：
(i)因为可以无核心基板安装，所以可以实现晶体管、IC、LSI的小型、薄型化。
(ii)因为在电路中可形成从晶体管到系统LSI以致芯片型电容和电阻并且可以形成组件化所以可以实现高密度SiP(system in packege)。
(iii)因为可以组合现有的半导体芯片，所以可以在短期间内开发系统LSI。
(iv)因为在半导体裸芯片的下面没有核心基板，所以可以获得良好的散热性能。
(v)因为电路配线是铜材料并且没有核心基板，所以形成低电容率的电路配线，在高速度数据传输和高频电路中发挥优良的特性。
(vi)因为是电极埋入组件内部的结构，所以能抑制电极材料产生颗粒污染。
(vii)组件尺寸自由，这与把每一个废弃材料作成64插头的SQFP组件比较只相当于约1/10的量，所以可以减小环境负担。
(viii)可以实现从安装元件的印刷电路基板到引入功能的电路基板这一新概念的系统结构。
(ix)ISB的图模设计与印刷电路基板的图模设计同样地容易，装配厂的工程师可以自行设计。
根据本发明提供的一种半导体装置，其包括：绝缘层；埋设在绝缘层内的配线；安装在绝缘层上的电路元件；覆盖电路元件而形成的封闭层；覆盖封闭层而形成的导电性的遮蔽膜。并且，配线与遮蔽膜电连接。这里，遮蔽膜具有遮蔽电磁波的功能，因此可以降低杂波的干扰。与遮蔽膜电连接的配线可以接地，因此也就可以将遮蔽膜接地，就可以遮蔽电磁波。
可以用与配线相同的材料构成遮蔽膜。例如，可以以铜为主要成分构成。另外，配线也可以形成与电路元件电连接的结构。当用ISB构成半导体装置时，将电连接在电路元件上的任一根配线接地。在本发明的半导体装置中可以形成遮蔽膜与这样地接地的配线电连接的结构。
本发明的半导体装置还可以包括保护膜，其覆盖遮蔽膜，用耐腐蚀性比构成遮蔽膜高的材料构成，保护膜例如可以用镍或金等构成。
这样，通过遮蔽膜可以遮蔽半导体装置，同时可以通过耐腐蚀性高的保护膜保护遮蔽膜表面，因此，可以长期保持遮蔽膜的机能。
根据本发明提供一种分割层叠体制造具有电路元件的半导体装置的制造方法，所述层叠体包括：绝缘层；埋设在绝缘层内的配线；安装在绝缘层表面上与配线电连接的电路元件；覆盖电路元件形成的封闭层。该半导体装置的制造方法包括：在所述层叠体的表面上形成分割槽而露出配线的侧面的工序，用导电材料覆盖层叠体表面侧形成与配线电连接的遮蔽膜的工序，从背面沿分割槽切断层叠体并将这个层叠体的电路元件从别的区域分割开的工序。
这样，由于可以配合从别的区域分割电路元件的工序而形成遮蔽膜，所以可以用简单的方法消除半导体装置的杂波干扰，因此就可以提高半导体装置的生产效率。
在本发明的半导体装置的制造方法中还可以包括使配线接地的工序。配线也可以形成与电路元件电连接的结构。
本发明的半导体装置的制造方法可以在绝缘层上安装多个电路元件，可以在露出配线侧面的工序之前设置配线与多个电路元件连接，在露出配线侧面的工序中可以以分割配线且使该被分割的各配线分别与各电路元件连接的方式形成分割槽.
在本发明的半导体装置的制造方法中可以以铜为导电材料的主要成分。
在本发明的半导体装置的制造方法中可以通过电镀法形成遮蔽膜。另外也可以通过用网版印刷法涂敷导电性糊形成遮蔽膜。
在本发明的半导体装置的制造方法中还包括用比构成遮蔽膜的材料具有更高的耐腐蚀性的材料构成的保护膜覆盖遮蔽膜的工序。
附图说明
图1是表示ISB的一例的结构示意图；
图2是表示本发明的实施例的半导体装置的制造方法的工序剖面图；
图3是表示图2所示的半导体装置的变形例的制造方法的工序剖面图；
图4是详细地表示图2所示的多层配线构造部分的半导体装置的剖面图；
图5是表示图2所示的半导体装置的制造过程中的层叠体的制造方法的图；
图6是在面朝下配置电路元件的倒装的半导体装置的剖面图；
图7是表示在多层配线结构上多个半导体装置形成矩阵状的状态图；
图8是表示半导体装置的另一例的图。
具体实施方式
图2是表示本发明的实施例中的半导体装置的制造方法的工序剖面图。
图2(a)表示半导体装置的制造过程中的层叠体。在此，层叠体包括：金属箔402；在金属箔402上形成的多层配线结构455；在多层配线结构455上形成的第一电路元件410a和第二电路元件410b；覆盖电路元件410a和电路元件410b的封闭膜415。多层配线结构455具有：层间绝缘膜405；设在层间绝缘膜405内的涂敷金属夹层403；电连接在涂敷金属夹层403上的配线407和被切断配线408；覆盖配线407和被切断配线408的绝缘膜409。在此，省略地描述多层配线结构455，但是多层配线结构455具有层叠多个涂敷金属夹层、配线以及绝缘膜的结构。
第一电路元件410a和第二电路元件410b，例如是晶体管、二极管、IC芯片等半导体元件，芯片电容、芯片电阻等无源元件。第一电路元件410a和第二电路元件410b通过金属线412适当地与配线407以及被切断配线408电连接。在这里，被切断配线408共同连接在第一电路元件410a和第二电路元件410b上。多层配线结构455的详细结构和到该阶段之前的层叠体的制造方法在以后叙述。
以下说明分割这样构成的层叠体制造半导体装置的工序。
首先，从表面侧(图中上侧)切割层叠体到层间绝缘膜405的中间形成分割槽411(图2(b))，由此，被切断配线408被切断形成连接第一电路元件410a的配线408a和连接第二电路元件410b的配线408b，配线408a和配线408b都在分割槽411的侧面露出。
接着，形成覆盖半导体装置的表面的遮蔽膜416(图2(c)).可以用与构成配线407和被切断配线408的金属相同的材料构成遮蔽膜416，例如可用铜或银等电阻较低的金属构成.另外，用与构成半导体装置的其他要素，诸如封闭膜415、配线407、层间绝缘膜405、绝缘膜409等的线性膨胀系数接近的材料构成遮蔽膜416是理想的.例如，可以用电镀法、溅射法、CVD法等形成遮蔽膜416.当用电镀法形成遮蔽膜416时，例如使用硫酸铜等化学铜进行无电解电镀，在半导体装置的表面形成铜薄膜之后再进行电解镀，例如，可以将半导体装置的表面侧浸泡在液温约25℃的硫酸铜水溶液中进行电解镀.遮蔽膜416形成与配线408a以及408b电连接.即遮蔽膜416可以在覆盖半导体装置全体之后将背面侧制成图模，去掉不需要的遮蔽膜416而形成；另外也可以只将半导体装置的表面侧浸泡在电镀液中形成遮蔽膜416.另外，也可以通过使用网版印刷法敷着导电性糊形成遮蔽膜416.
然后，去掉金属箔402，这可以通过研磨、研削、腐蚀、激光蒸发金属等工序进行。接着，在露出的焊钉403上焊上焊锡等导电材料，在多层配线结构455的背面形成焊锡球420(图2(d))。将连接配线408a和配线408b的焊锡球420接地。这样，可以将遮蔽膜416也接地，就可以保证半导体装置遮蔽杂波的功能。
接着，沿分割槽411从半导体装置的背面侧再切割开半导体装置(图2(e))。在此，要在各半导体装置中保持着遮蔽膜416分别连接配线408a以及408b的状态而进行从背面侧的切割。这样制成半导体装置。
在本实施方式，在进行图2(d)所示的除去金属箔402的工序之前，金属箔402成为支持基板。金属箔402在形成涂敷金属夹层403、配线407以及被切断配线408时或者在形成遮蔽膜416时的电解电镀工序中还作为电极使用。另外，在成型封闭膜415时也可以使向模具的输送及安装的操作性良好。
如上所述，根据本发明，在半导体装置的制造过程中可以用简单的方法在半导体装置表面形成遮蔽膜416，可以消除杂波。这样，也可以提高半导体装置的生产率。另外，根据本发明，因为在成型电路元件的封闭膜415的表面上直接形成遮蔽膜416，所以可以使半导体装置小型、轻量化。
如图3所示也能形成遮蔽膜416被保护膜418覆盖的结构。与参考图2(c)说明的一样地在形成遮蔽膜416之后，再在遮蔽膜416上例如通过电镀法、溅射法、CVD法形成保护膜418(图3(a))。由耐腐蚀性高于构成遮蔽膜416的金属材料构成保护膜418。作为这种材料可以例举镍和金。接着，除去金属箔402形成焊锡球420(图3(b))，然后，从半导体装置的背面侧切割分开半导体装置(图3(c))。
这样，通过遮蔽膜416可以遮蔽半导体装置的第一电路元件410a以及第二电路元件410b，同时可以通过耐腐蚀性高的保护膜418保护遮蔽膜416表面，因此，可以长期间维持遮蔽膜416的功能。
图4是详细表示的图2所示的多层配线结构455部分的半导体装置的剖面图。在图2中省略地描述了多层配线结构455。多层配线结构455是多层层叠由层间绝缘膜405以及配线407形成的配线层而形成的多层配线结构体。
以下，参照图5以及图2(a)说明图2(a)所示的阶段之前的层叠体的制造方法.首先，在金属箔402表面上的规定区域上有选择地形成导电薄膜422(图5(a)).具体作法是用光致抗蚀剂(未图示)涂敷在金属箔402上之后，去掉规定区域的光致抗蚀剂露出金属箔402表面的一部分；接着通过电解电镀法在金属箔402的露出面上形成导电薄膜422.导电薄膜422的膜厚，例如约为1～10μm.因为该导电薄膜422最终成为半导体装置的背面电极，所以使用金或银等与焊锡等焊料的焊接性良好的材料形成是理想的.金属箔402的主要材料最好是Cu、Al、Fe-Ni等的合金.原因是与焊接材料的焊接性和电镀性能良好.金属箔402的厚度没有特殊地规定，例如，可以是约10μm～300μm程度.
去除形成导电薄膜422所用的抗蚀剂之后，在金属箔402上形成第一层配线图模。首先，化学研磨金属箔402，进行表面的清洁和表面粗化。然后，在金属箔402上堆积热硬化性树脂全面覆盖导电薄膜422，加热硬化形成具有平坦表面的层间绝缘膜405。作为构成层间绝缘膜405的树脂材料有：BT树脂等的密胺衍生物、液晶聚合物、环氧树脂、PPE树脂、聚酰亚胺树脂、氟树脂、苯酚树脂、聚酰亚胺双马来酰亚胺等热硬化性树脂。其中，最好使用高频特性优良的液晶聚合物、环氧树脂、BT树脂等的密胺衍生物。也可以在这些树脂中适当地添加填料和添加剂。
接着，在层间绝缘层405中，例如通过二氧化碳激光、机械加工、药液化学腐蚀加工、等离子干腐蚀法等形成涂敷金属夹层孔424。然后照射受激准分子激光除去刻蚀渣，接着在整个面上形成铜镀层以填埋涂敷金属夹层孔424。为了使该铜镀层不会因为涂敷金属夹层孔424的台阶而断线，首先通过无电解镀铜在整个面形成约0.5μm的薄膜，然后再通过电解镀形成约20μm的厚度。无电解电镀用触媒通常多使用钯，为了在可镀性的绝缘基板上附着无电解镀用触媒，可以将钯以配位基的状态溶进水溶液，将可镀性绝缘基板浸泡在溶液中使其表面附着钯的配位基，在该状态下通过使用还原剂还原成金属钯，可以在可镀性的绝缘基板表面形成开始镀的核。通常，为了进行这种操作先用酒精或酸清洗被镀物，除去表面上附着的油份。
然后，以光致抗蚀剂为掩膜蚀刻铜镀层，形成铜配线407(图5(b))。此时也形成涂敷金属夹层403。例如，可以在从抗蚀剂露出处喷涂化学腐蚀液，通过蚀刻去掉不要的铜箔形成配线407。抗蚀剂可以使用通常制作印刷配线板所用的抗蚀材料，也可以用绢网印刷抗蚀墨形成，或者将抗蚀层用感光干薄膜层叠在铜箔上，在其上重合按配线导体形状透过光的光掩膜，用紫外线曝光，用显影液去除没曝光处形成。化学腐蚀液可以使用氯化铜与盐酸的溶液、氯化铁溶液、硫酸与过氧化氢溶液、过硫酸铵溶液等制造普通的印刷配线板所用的化学腐蚀液。
然后，再覆盖配线407形成层间绝缘膜405之后，通过反复进行同样的工序形成层叠涂敷金属夹层孔424、涂敷金属夹层403、配线407以及被切断配线408的层叠结构(图5(c))。
返回到图2(a)，在多层配线结构455的最上层形成绝缘膜409。构成绝缘膜409的材料可举出如：环氧树脂、丙烯基树脂、氨基甲酸酯树脂、聚酰亚胺树脂等树脂以及它们的混合物，还有在这些树脂中混合碳黑、氧化铝、氮化铝、氮化硼、氧化锡、氧化铁、氧化铜、滑石、云母、高岭石、碳酸钙、二氧化硅、氧化钛等无机填料而形成的混合物等。
然后，在绝缘膜409的表面安装第一电路元件410a以及第二电路元件410b，通过金属线412将第一电路元件410a和第二电路元件410b与配线407以及被切断配线408连接。第一电路元件410a以及第二电路元件410b，例如用焊锡等焊接材料或粘接剂等固定在绝缘膜409上。
接着，用封闭膜415成型这些第一电路元件410a以及第二电路元件410b.用模具同时进行第一电路元件410a以及第二电路元件410b的成型.在这里只表示了两个电路元件，但是可以对更多电路元件同时进行成型.封闭膜415的形成可以通过传递成型、注塑成型、浇注法或浸渍法等实现.作为树脂材料，环氧树脂等等热硬化性树脂可以用传递成型法或浇注法实现定型；聚酰亚胺树脂、聚苯硫化物等热可塑性树脂可以用注塑成型法实现定型.
另外，在以上的图2～图5中表示了以金属线连接方式连接电路元件410a(以及电路元件410b)与配线407以及配线408a(以及配线408b)，然而，也可以如图6所示地进行面朝下配置电路元件410a的倒装。
图7是表示在多层配线结构455上形成的多个半导体装置465形成矩阵状的状态的图。在本实施例，在多个组件上形成封闭膜415以及遮蔽膜416，但是在此省略描述。多个组件465沿切割线490被分割。在本实施例，因为在去掉金属箔之后进行切割，所以能抑制切断面的粗糙和切割刀的消耗。另外，通过在多层配线结构455的表面设置位置对准标记470可以迅速并且准确地决定切割线的位置。在本实施例位置对准标记470最好从多层配线构造455的表面到背面形成孔状。这样，从背面进行切割时也可以正确地决定切割线的位置。
另外，在BGA等现有的CSP中采用用模具将在基板上形成的组件打孔的方法。因此，如在本实施例说明的，与切割工序配合形成遮蔽膜416的制造工序难以适用于现在的CSP。这样通过使用在本实施例说明的ISB，可以用切割法分割半导体装置，同时也可以形成遮蔽膜416，这在制造工序有很大的优点。
图8是表示半导体装置的另一例的图。
在图2以及图3中表示了在一个半导体装置中包括一个电路元件的结构，然而，半导体装置也可以形成一个装置内包括多个电路元件的组件结构。
图8所示的半导体装置包括多个无源元件410c和多个半导体元件410d、410e、410f。在此，半导体装置包括一个半导体元件410e与另一个半导体元件410f形成层叠的结构。这样的半导体元件410e与半导体元件410f的组合，例如，可以形成SRAM和瞬间存储器、SRAM和PRAM。此时，半导体元件410e与半导体元件410f通过涂敷金属夹层500电连接。
以下，说明制造该半导体装置的工序。
图8(a)表示半导体装置的制造过程中的层叠体。层叠体包括：在金属箔402上形成的多层配线结构；在多层配线结构上形成的多个无源元件410c和多个半导体元件410d、410e、410f。在这样形成的层叠体中从图中上侧到多层配线结构中切割形成分割槽411(图8(b))。然后，参照图2进行与所述相同的工序，形成覆盖半导体装置的遮蔽膜。接着，除去金属箔402。然后，在除去了金属箔402的面上形成焊锡球420。接着，沿分割槽411从与图8(b)所示的相反侧的面再切割分开半导体装置。于是，获得图8(c)所示的结构的半导体装置。
在本例中，遮蔽膜416也通过配线408c与焊锡球420电连接。因此，通过将焊锡球420接地，遮蔽膜416也可以接地，可以遮蔽半导体装置的杂波干扰。

Claims (9)

1.一种半导体装置，其特征在于，包括：绝缘层；埋设在所述绝缘层内的配线；载置在所述绝缘层上的电路元件；覆盖所述电路元件而形成的封闭层；覆盖所述封闭层而形成的导电性的遮蔽膜；并且，所述配线与所述遮蔽膜电连接。
2.如权利要求1所述的半导体装置，其特征在于，还包括保护膜，其覆盖所述遮蔽膜，用耐腐蚀性高于构成所述遮蔽膜的材料构成。
3.一种半导体装置的制造方法，其分割层叠体制造具有所述电路元件的半导体装置，所述层叠体包括：绝缘层；埋设在所述绝缘层内的配线；载置在所述绝缘层表面上的电路元件；覆盖所述电路元件而形成的封闭层，其特征在于，包括：在所述层叠体的表面上形成分割槽并且露出所述配线的侧面的工序；用导电性材料覆盖所述层叠体表面侧并且形成所述配线电连接的遮蔽膜的工序；从背面沿所述分割槽切断所述层叠体并将该层叠体的所述电路元件从别的区域分割开的工序。
4.如权利要求3所述的半导体装置的制造方法，其特征在于，还包括使所述配线接地的工序。
5.如权利要求3所述的半导体装置的制造方法，其特征在于，在所述绝缘层上载置多个电路元件，在露出所述配线的侧面的工序之前配设所述配线与所述多个电路元件连接；在露出所述配线侧面的工序中以分割所述配线且使该被分割的各配线分别与各所述电路元件连接的方式形成所述分割槽。
6.如权利要求4所述的半导体装置的制造方法，其特征在于，在所述绝缘层上载置多个电路元件，在露出所述配线的侧面的工序之前配设所述配线与所述多个电路元件连接；在露出所述配线侧面的工序中以分割所述配线且使该被分割的各配线分别与各所述电路元件连接的方式形成所述分割槽。
7.如权利要求3所述的半导体装置的制造方法，其特征在于，还包括用比构成所述遮蔽膜的材料具有更高的耐腐蚀性的材料构成的保护膜覆盖所述遮蔽膜的工序。
8.如权利要求4所述的半导体装置的制造方法，其特征在于，还包括用比构成所述遮蔽膜的材料具有更高的耐腐蚀性的材料构成的保护膜覆盖所述遮蔽膜的工序。
9.如权利要求5所述的半导体装置的制造方法，其特征在于，还包括用比构成所述遮蔽膜的材料具有更高的耐腐蚀性的材料构成的保护膜覆盖所述遮蔽膜的工序。
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