TW200427025A - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
TW200427025A
TW200427025A TW093105854A TW93105854A TW200427025A TW 200427025 A TW200427025 A TW 200427025A TW 093105854 A TW093105854 A TW 093105854A TW 93105854 A TW93105854 A TW 93105854A TW 200427025 A TW200427025 A TW 200427025A
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Taiwan
Prior art keywords
wiring
semiconductor device
film
manufacturing
mentioned
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TW093105854A
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English (en)
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TWI293796B (zh
Inventor
Ryosuke Usui
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Sanyo Electric Co
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Publication of TW200427025A publication Critical patent/TW200427025A/zh
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Publication of TWI293796B publication Critical patent/TWI293796B/zh

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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Description

200427025 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種搭载有電路元件之半導體裝置及其 製造方法。 【先前技術】 近年來，行動電話、PDA、DVC、DSC之可攜式電子 设備的高功能化正急速地進展中。因而此等電子機器所使 用之LSI必須高功能化、高性能化。因此，LSI的動作時 脈亦為高頻。又，為使此種電子設備能夠被市場接受，必 須將其小型/輕量化，而為了實現此功能則要求高積體密 度的LSI。 如上所述，將高頻LSI安裝成小型化，故會產生半導 體晶片彼此間之距離縮短，密度變高，且雜訊（n〇ise)影響 增大的問題。以往，針對於雜訊之因應對策，已揭示有以 孟屬封裝材覆盍半導體裝置之封裝體的技術（例如，日本特 開平5-47992號公報） 【發明内容】 [發明所欲解決之課題] 由於上述專利文獻1所揭示之以金屬封裝材覆蓋半導 體裝置之封裝體的技術中，係將封裝材當作與半導體裝置 不同之個別零件，並安裝於印刷基板上，故封裝材^成後 會有封裝體尺寸變大而無法達成小型化的問題。再者，由 於封裝材係作為與半導體裝置不同之個別零件而形成，所 以也會有生產性低的問題。 315564 5 200427025 [用以解決課題之手段] 本發明係有鑑於上述問題而開發者，其目的在於提供 一種可以簡單的方法，獲致半導體裝置之雜訊因應對策的 技術。 以往，將高頻用LSI小型封裝化的技術已知有csp(例 如，日本特開20()2_94247號公報）。該公報中揭示有搭 =頻用⑶之系統封裝一、·—“… 封4體係在底基板上形成多声 4 ^夕層配線構造，並於多層配線構 ^上形成有高頻用LSI等電路元株。夕麻π a 予电峪凡件。多層配線構造係形成 積曰有芯基板或附有樹脂之銅箔等之構造。 然而，在此等習知CSP中，欲力可4崔斗、 。r 奴在可攜式機器等中達成 目所所期望之小型化、薄型化、 寻I化輕里化水準實有困難。此 乃因写知之CSP具有支捭曰κ Μ苴』 + /、男叉符曰曰片的基板。因支持基板的存在 而使封裝體整體變厚，使小型化、 J i化溽型化、輕量化有所限 制。又’散熱性的改善亦產生一定的限制。 本案發明者有鑑於此問題
/T J ^ 而開發出一種稱為ISB
(ntegrated System in Board ·双林念栖、A
立 d，且錄商標）之新穎封裝體。ISB =曰’以半導體裸晶片（barechip)為中心之電子電路封裝
…未使用芯(基材)的獨立無芯系統封裝體—S system · in · package)，而該封雕 洛、 訂放月豆係具有銅所生之配線圖 案’並且用以支持電路零件者。 有日本特開2002-1 1071 7號 公報中記載有此種系統封裝 · ^ 衣月丑(system · in · package，SiP) 〇 第1圖係表示ISB例的舾故姓Λ、㈤
〕概各構成圖。在此，為使ISB 之正體構造容易了解，僅顯一口口 ,，、、頁不早一配線層，然而，實際上 315564 6 200427025 係為積層有複數個配線層的構造。在該ISB中，lsi裸晶 片201、Tr裸晶片2〇2及晶片CR2〇3係為藉由以鋼圖案 所構成之配線而連接的構造。LSI裸晶片2〇1係藉由拉出 電極或配線與金銲線2〇4而導通。在LSI裸晶片2〇ι的正 下方設有導電性塗漿（paste)2〇6，而ISB係藉由該導電性塗 漿206安裝於印刷配線基板。ISB整體係形成藉由環氧樹 脂等所構成之樹脂封裝體207而封裝的構造。 根據該封裝體，可獲致以下的優點。 (1)由於可以無芯式進行安裝，故可實現電晶體、1C、LSI 的小型·薄型化。 (Π)由於可由電晶體，電路形成系統LSI、晶片型電容器或 電阻’且可實施封裝，故可實現高度的Sip(Systeni in Package) ° (iii) 由於可組合現有的半導體晶片，故可在短期間開發系 統 L SI 〇 (iv) 由於半導體裸晶片下沒有芯材，故可獲致良好的散熱 性。 (v) 由於電路配線係為銅材，且沒有芯材，故得以形成低介 電常數的電路配線，且可發揮高速資料傳送或高頻電路之 優良特性。 (vi) 由於係形成電極埋設於封裝體内部的構造，故可抑制 電極材料之微粒子污染的發生。 (viii)封裝體尺寸較自由，將每1個廢材與64銷（pin)之 SQFP封裝體相比較時，約需ι/10量，故可減少環境負荷。 7 315564 200427025 (vm)從載置零件的印刷電路基板，進而具備電路基板之功 月匕t 可貫現新概念的系統構成。 (ix)ISB的圖案設計係與印刷電路基板的圖案設計相同，較 為谷易，而產品生產者（set maker)的工程師可自行設計。 根據本發明，可提供一種半導體裝置，其特徵係包括： 絶緣層；埋設於絕緣層内的配線；搭載於絕緣層上的電路 兀件、胃覆盍電路元件而形成的封裝層；及覆蓋封裝層而形 成的‘電性遮蔽膜；而配線與遮蔽膜係電性連接。藉此構 =’可降低雜訊的影響。可將電性連接於遮蔽膜㈣線予 、 口此，亦可使遮蔽膜接地，而可遮蔽電磁波。 ，蔽膜係可藉由與配線相同的材料構成。遮蔽膜係可 銅為主成分而構成。x ’配線亦可電性連接於電路 :而構成…SB構成半導體裝置時，與電路元件電性 蔽膜配線皆可接地。在本發明的半導體裝置中，遮 蔽聽係可與以此方式接地之配線電性連接而構成。 —本發明之半導體裝置另包括保護膜，而該 膜而形成，I由耐腐純比構成遮蔽膜之材料= 、㈣構成。保護膜係可藉由例如錦或金等來構成。-精此構成，可利用遮蔽膜來遮 較高的保護膜來保護遮蔽膜表:置故 間維持遮蔽膜之功能。 文了長期 :據本發明’可提供一種半導體裝置的 將含有絕緣層、埋設於絕緣層内之配線 方法係 面之電路元件及覆蓋電路元件 ：;絕緣層表 风之封叙層的積層體予 315564 8 427025 、 」以製造含有上述電路元件的半導體裝置，而兮坐 導體裝置的製造方法係包括下列步驟：在上述積層體:表 面开乂成分副溝，而令上述配線之側面露出的步驟；以導電 ==盖積層體之表面側’俾形成與配線電性連接之遮 、、乂驟，及將積層體從背面沿著分割溝切 積層體之電路元件自其他區域分割的步驟。 而將该 也人=成，可藉由與自其他區域分割電路元件之步驟 。7成遮相’故可以簡單的方&，獲 之雜訊因應對策。因此，可提昇半導體裝置的生^置 在本發明半導體裝置之製造方法中，可 接地的步驟。ap娩介7 ^ 、爾7配線 配線亦可電性連接於電路元件而構成。 在本發明半導體裝置的製造方 搭載複數個電路元件，且在配線 ；:“層： 亦可連接；j曲路出之步驟W，配線 迓筏於複數個電路元件而設置，並且在令 露出的步驟中，分割 、1面 接於各電路元件……刀割後的各配線分別連 u旰弋方式，形成分割溝。 在本發明半導體裝置的製造方 以銅為主成分。 夺电f生材枓亦可 明半導體裝置的製造方法中，亦可藉由電鑛法 電性塗聚之方法來=精由利用網版印刷法附著導 覆蓋體裝置的製造方法中，另包括以保護膜 :;膜才称’而該保護膜係由耐腐钱性比構成該遮 故Μ之材料更南的材料所構成。 315564 9 200427025 【實施方式] 第2圖係本發明實施形態之半導體裝置製造方法的步 驟剖視圖。 第2圖（a)係半導體製造途中之積層體。在此，積層體 係包括：金屬箔402 ;形成於金屬箔上的多層配線構造 455 ;形成於多層配線構造上之第一電路元件41〇a及第二 電路元件41〇b ;及覆蓋電路元件410a及電路元件410b而 形成的封裝膜415。多層配線構造455具有：層間絕緣膜 405 ;設置於層間絕緣膜405的介層孔（via)403 ;與介層孔 403電性連接的配線407及被切斷配線408 ;覆蓋配線407 及被切斷配線408而形成的絕緣膜409。在此，省略多層 配線構造455之記載，而多層配線構造455係具有積層複 數個介層孔、配線及絕緣膜的構造。 第一電路元件4 1 0a及第二電路元件4 1 Ob係為例如： 電晶體、二極體、1C晶片等半導體元件、晶片電容器、晶 片電阻等被動元件。第一電路元件41〇a及第二電路元件 410b係藉由引線（wire)412,適當地連接於配線4〇7及被切 斷配線408。在此，被切斷配線408係共同連接於第一電 路元件410a及第二電路元件410b。關於多層配線構造455 的詳細構成及此階段之積層體的製造方法將於後闡述。 以下，說明將以上述方式構成的積層體加以分割，以 製造半導體裝置的步驟。 首先，將積層體從表面側（圖中上側）切割至層間絕緣 膜405之途中，而形成分割溝411(第2圖⑶））。藉此方式， 315564 10 200427025 被切斷配線408分割成連接於第一電路元件41〇a的配線 408a，以及連接於第二電路元件41〇b的配線4〇8b，而配 線408a及配線408b同時露出於分割溝411的側面。 繼之，以覆蓋半導體裝置表面之方式形成遮蔽膜 416(第2圖（c)。遮蔽膜416可藉由與構成配線4〇7及被切 斷配線408之金屬相同的材料構成。耗膜416可藉由例 如銅或銀等電阻較低的金屬來構成。理想的狀態是，遮蔽 膜416係藉由與構成半導體裝置之其他構成要素例如封裝 膜415配線407、層間絕緣膜4〇5、絕緣膜4〇9等形成之 線膨脹係數差較少的材料構成。遮蔽膜416可以例如電鍍 法、⑽法、CVD法等來形成。以電錢法形成遮蔽膜416 時Η系使用例如硫酸銅等化學鋼，進行無電解電錢，以在 半導體裝置的表面形成銅薄膜後’進行電解電鍍。電解電 艘係將例如半導II奘署I 丨、a、支 骽表置表面側次潰於液温約25 〇c之硫酸 銅水溶液來進行。i玲絲日替Λ α & 〜蚊臈416係與配線408a及配線408b 電性連接而形成。逆絲胳4 + ^ 〜威膑416亦可在覆蓋半導體裝置整體 而形成後’將背面側雜以同安乂μ 側她以圖案化，以去除不要的遮蔽膜416 而形成’ X ’亦可僅將半導體裝置之表面側浸潰於電錄液 而升/成此外，遮蔽膜416亦可由使用網版印刷法， 電性塗漿附著而形成。 接者:去除金屬落術。金屬落他之去除係可藉由 研磨、研削、姓刻、雷射全屬 耵之至屬洛發寻來進行。繼之，將 : = 附著於露出的介層⑽以在多層配線構 le 455的月面，形成銲 2 (弟~ ® (d))。與配線408a及 315564 11 200427025 配、、泉4 0 8 b連接的焊球4 2 〇係接地。藉此構成，遮蔽膜4 i 6 亦可接地’故得以確保遮斷半導體裝置雜訊之功能。 繼之’沿著分割溝41丨，從半導體裝置的背面側再進 订切剔，以分割半導體裝置（第2圖。於此，在各半導 體裝置中，從背面側進行切割時，係以確保遮蔽膜416分 別與配線408a及配線4〇8b連接的狀態來進行。藉此方式， 完成半導體裝置。 本實施形態中，金屬结4〇2係作為支持基板，直到進 仃第2圖（d)所示之金屬箔4〇2被去除。金屬箔4〇2在介層 孔403、配線4G7及被切斷配線彻形成時或遮蔽膜416 形成時之電解電鍍步驟中，係當作電極來使用。再者，模 塑封裝膜415日寺’亦可使搬送至模具、安裝於模具之 良好地進行。 ^如上所述，根據本發明，在半導體裝置之製造途中， _仔以利用簡早的方法於半導體裝置表面形成遮蔽膜Μ 6， 可C致雜Λ之因應對策。藉此構成，亦可提昇半導體裝 置的生產性。X ’根據本發明’可直接在模塑成型有電路 元件之封裝膜415表面，形成遮蔽膜416，故可將半導體 衣置小型、輕量化。 如弟3圖所不，遮蔽膜416亦可由保護膜418覆蓋而 構成。與參照第2圖（c)之今明η^ y 、兄明冋樣地，形成遮蔽膜416後， 在遮蔽膜4 1 6上利用例如雷你、也 ^ > 1如電鍍法'_法、CVD法形成保 瘦膜418(第3圖（a))。保鳟臌心δ及丄 保4胰418係由耐腐蝕性比構成遮
敝膜4 1 6之金屬更南的材料所爐 .L «竹所構成。此種材料例如有：鎳、 315564 12 200427025 金等。接著，去除金屬箔402以形成焊球420(第3圖（b))。 然後，從半導體裝置的背面側實施切割，以分割半導體裂 置（第3圖（c))。 藉此構成，得以藉由遮蔽膜416遮蔽半導體裝置之第 一電路元件410a及第二電路元件410b，同時得以藉由耐 腐餘I1生馬的保§蔓膜4 1 8保護遮蔽膜4 1 6表面，故可長期間 維持遮蔽膜4 1 6的功能。 不1同你旰御地衣不第2圖之多層配線構造455部〜 的半V體裝置之剖視圖。第2圖中，省略了多層配線構3 =5之記載，而多層配線構造455係由積層有複數個層間 系巴緣膜405及由配線4〇7所構成之配線層而構成者。 凡以下，參考第5圖及第2圖（a)，說明至第2圖（句之門 丰又的積層體製造方法。 百先，在金屬箔402表面上的預定區域，選擇性地开 费::被，422(第5圖⑷）。具體而言，以光阻劑（未圖示 :盍金屬帛402後，去除預定區域的光阻劑，以令金屬裂 外2表面的一部分露出。繼之，利用電解電錢法，在金屬 洎4 02的霞ψ ; r >、苦 你至屬 .^ 出面形成導電被膜422。導電被膜422 係為例如1 $ ! n , i ^ ^ ,# m左右。由於該導電被膜422最後合开 性良：Γ;=Τ電極’故以使用與銲料等焊接材心 Cu :1 F來，成為佳。金屬“。2的主材料係以 鍍性良好之\Nl::金為佳。此係因銲接材的附著性或電 例如1G H|4G2的厚度並無特別限制，可形成 ”如Μ心至300 "m左右。 少取 315564 13 200427025 &將形成導電被膜422時所使用的阻劑去除後，在金屬 落402上形成第一層配線圖案。首先，將金屬帛術施以 化學研磨，以進行表面清潔與表面粗化。繼之，在金屬羯 402上沉積熱硬化性樹脂，以覆蓋導電被膜a】整面，接 著，令其加熱硬化以形成具有平坦表面的層間絕緣膜 彻一°構成層間絕緣膜4〇5的樹脂材料可例舉出：π樹脂 等二聚亂胺衍生物、液晶聚合物、環氧樹脂、ppE樹脂、 聚醯亞胺樹脂、氟樹脂、苯酚樹脂、聚醯胺雙馬來酸酐縮 亞胺（poly bismaleimide)等熱硬化性樹脂。其中，高頻特性 優良的液晶聚合物、環氧樹脂、Βτ樹脂等三聚氮胺衍生物 較適合使用。亦可在此等樹脂中添加適當的填料（fiuer)或 添加劑。 繼之，在層間絕緣膜405中，藉由例如二氧化碳雷射、 機械加工、藥液所生之蝕刻加工、使用電漿之乾蝕刻法等， ，成通孔424。然後，照射準分子雷射以去除敍刻渣，接 著，以埋設通孔424之方式整面形成銅電鍍層。首先利用 無電解銅電鍍，整面形成〇.5//m左右的薄膜後，再利用 電解銅電鍵形成約20 // m左右的厚度’使該銅電鍍層在通 孔424的段差不會產生斷線。一般無電解電鍍用觸媒大多 使用I巴，❿令無電解帛電鑛用觸^付著於可挽性絕緣基材 時，將鈀以錯合物狀態含於水溶液，接著，將可撓性絕緣 基材浸潰於該水溶液中，以令把錯合物附著於該絕緣基材 的表面’在此情況下，藉由使用還原冑，還原成金屬纪， 可在可撓性絕緣基材表面形成用以開始進行電鑛的芯。一 315564 14 025 般而言，為了進行此種操 舻、n ^ ^預先將被電鑛物以酒精戋 酸洗 >尹，並將附荖於本& a 旧a 打w者於表面的油分去除。 以光阻劑作為遮罩， 早蚀刻鋼電鍍層，而形成由銅槿士 的配線407(第5圖（13)) 戚由钔構成 綠))此吩，亦形成介層孔（Wa)403。配 線407可糟由例如在從阻 4路出的邛位，賀塗化學蝕刻 液，以姓刻去除不要的銅笮 而形成。蝕刻阻劑可使用一# 印刷配線板得以使用之蝕刻 般 · 1 d柯枓，而將阻劑油墨 (resist lnk)以絲網印刷而形 乾薄膜声汽於或可將姓刻阻劑用感光性 乾/專Μ層壓於銅箔上，接著， ^ ^ # . . w ，、上以配線導體形狀重疊 透過先的先罩，使紫外線曝光， 〜十丨上A 上析/又有曝光的部位以顯 衫劑去除而形成。以化學餘 . ^ u 刻，夜而$，可使用氯化銅盥鴎 酉文的溶液、氯化鐵溶液、硫酸 m H海室 h ，、10虱化虱的洛液、過硫酸 Λ夜4、—般的印刷配線版所使用的化學餘刻液。 其後，以覆蓋配線407之方彳η卫/„ 一 之方式另形成層間絕緣膜405 後’精由反覆進行同樣的步驟，而形成通孔424、介芦孔 4〇3、配、線407及被切斷配線彻的積層構造（第$圖⑷）。 返回第2圖⑷，多層配線構造…的最上層係形成絕 緣膑409。構成絕緣膜柳的材料係有例如··環氧樹脂、 丙稀基樹月旨、聚氨醋（urethane)樹脂、聚醯亞氨樹脂等樹脂 ，此等的混合物’再者，此㈣脂中混合有炭黑、氧化紹、 虱化鋁、氮化硼、氧化錫、氧化鐵、氧化銅、滑石、雲母、 高嶺土（kaolinite)、碳酸鈣、二氧化矽（si]ica)、氧化1太 無機填料等。 、 繼之，在絕緣膜的表面搭載第一電路元件4心 315564 15 200427025 及第二電路元件41〇b，而將第一電路元件410a及第二電 2^天> 4牛 4 1 0 兴务 b藉由引線412與配線407及被切斷配線408
連接。第一帝y L 曰 包路兀件4 1 〇a及第二電路元件4 1 〇b係藉由例 如1干料等銲接材或接合劑等，固接於絕緣膜409上。 一以封裝膜415模塑此等第一電路元件41〇a及第二電路 凡件41⑽。第—電路元件4心及第二電路元件41 〇b的模 塑係使用拉具同時進行。在此，雖僅顯示兩個電路元件， 然而，可同時對多數電路元件進行模塑。封裝膜415的形 成可藉由移轉模塑法、射出成形模塑法、接合法或浸漬 Wpping)法進行。作為樹脂材料及環氧樹脂等熱硬化樹脂 可藉由私轉;^塑法製成，而聚醯亞氨樹脂、聚苯硫喊（pps， P〇lyPhenylene sulfide)等熱可塑性樹脂可藉由射出成形模 塑法製成。 、 又，上述第2圖至第5圖中，係表示利用引線銲接的 方式，連接電路元件41Ga(及電路元件·)與配線4〇7及 配線408a(及配線彻b)的形態，然而亦可如第6圖所示， :電路兀件41〇a形成面朝下(faced〇㈣配置的倒裝(出p) 安裝。 第7圖係多層配線構造455上所形成之複數個半導體 裝置465呈矩陣狀的狀態圖。在本實施形態中，係在複數 個模組上形成有封裝膜415及遮蔽膜416，然而在此省略 其記載。複數個模組465係沿著切割線49〇分割。由於在 本實施形態中，係在去除金屬箱後進行切割，力丈可抑制切 斷面之粗II及切割刀的耗損。再者，#由在多層配線構造 315564 16 200427025 455的表面設置位置對準標記470,可迅速且正確地把握切 割線的位置。本實施形態中，位置對準標記4 7 0係以從多 層配線構造455的表面至背面，形成孔狀為佳。藉此構成， 即使從背面進行切割時，亦可正確地把握切割線的位置。 此外，BGA等習知的CSP係採用以模具沖切形成於基 板上之模組的方法。因此，如本實施形態所說明，將以組 合切割步驟而形成遮蔽膜4 1 6的製造步驟適用於習知的 CSP是有困難的。因此，可藉由使用本實施形態所說明的 ISB，藉由切割來分割半導體裝置，同時亦可形成遮蔽膜 416 ’故在製造步驟上有很大的優點。 第8圖係半導體裴置的其他例圖。 第2圖及第3圖係表示一個半導體裝置中含有一 1因电 路元件的構成’然而，I導體裝置亦可作成在一個裝置内 含有複數個電路元件的模組。 第、8圖所不之半導體裝置包括：複數個被動元件 複數個半導體元件410d、410e、41〇f。在此，半導 :裝置包括:積層有一個半導體元件4l〇e與其他半導體元 的構成。此種半導體元件41Ge與半導體元件4旧 的t 〇可為例* SRAM與Flash記憶體、SRAM與pram。 半導體元件心與半導體元件41Gf係藉由介層孔 5 00而電性連接。 :T :說明製造該半導體裝置的步驟。 包括 了 ^ ( K表不半導體製造途中的積層體。積層體係 7 、於金屬須402上的多層配線構造；與形成於多 3]5564 200427025 層配線構造上的複數個被動元件4 1 〇 c、或複數個半導^元 件410d、410e、410f。在以此方式構成的積層體上，施行 從圖中上側至多層配線構造途中之切割，以形成分割溝 411(第8圖（b))。接著，與參照第2圖所述之内容同樣地， 覆蓋半導體裝置而形成遮蔽膜。其後，去除金屬荡4〇2。 然後’在去除金屬箔402的面形成焊球420。繼之，沿著 分割溝4 11，從第8圖（b)的相反側面，再次進行切割，以 分割半導體裝置。藉此方式，可獲致第8圖（c)所示之半導 體裝置的構成。 在本貫施例中，遮蔽膜4 1 6係藉由配線4 0 8 c而與焊球 4 2 0電f生連接。猎此構成，藉由使焊球4 2 〇接地，亦可使 遮蔽膜4 1 6接地，故可遮斷半導體裝置的雜訊。 【圖式簡單說明】 第1圖係ISB例的概略構成圖。 第2圖（a)至（e)係本發明實施形態之半導體裝置製造 方法的步驟剖視圖。 第3圖（a)至（c)係第2圖之半導體裝置變形例之製造方 法的步驟剖視圖。 第4圖係詳細地表示第2圖之多層配線構造部分的半 導體裝置之剖視圖。 第5圖（a)至（c)係第2圖之半導體裝置製造途中之積層 體的製造方法之圖。 第6圖係將電路元件面朝下（facedown)配置之倒裝安 裝的半導體裝置之剖視圖。 18 315564 200427025 第7圖係複數個半導體裝置呈矩陣狀形成於多層配線 構造上的狀態圖。 第8圖（a)至（c)係本發明半導體裝置的其他例圖。 [元件符號說明] 201 L SI裸晶片 202 Tr裸晶片 203 晶片CR 204 金銲線 205 鋼圖案 206 導電性塗漿 207 樹脂封裝體 208 ^ 420焊球 402 金屬箔 403 - 500介層孔 405 層間絕緣膜 407 西己線 408、 408a、408b 被切斷配線 409 絕緣膜 410a 、410b電路元件 410c 被動元件 410d 、410e、410f半導體元件 411 分割溝 412 引線 415 封裝膜 416 遮蔽膜 418 保護膜 422 導電被膜 424 通孔 455 多層配線構造 465 半導體裝置（模組） 470 位置對準標記 490 切割線 19 315564

Claims (1)

  1. 申請專利範圍： —種半導體裝置，其特徵係包括： 絕緣層； 搭載於上述絕緣層上的電路元件； 覆蓋上述電路元件而形成的封裝層· 覆蓋上述封裝層而形成的導電性遮蔽祺 而上述配線與上述遮蔽膜係電性連接、 另包栝保 且由耐腐 如申請專利範圍第i項之半導體裝置，其中 護膜，而該保護膜係覆蓋上述遮蔽膜而形 蝕性比構成上述遮蔽膜之材料更高的材且 —種半導體裝置的製造方法，係將含' ., 3、、、巴緣層、4：Φ <3* 於 上述絕緣層Μ之配線、搭載於上述 ^一 株菸萝鞏 增表面之電路兀 牛及復皿上述電路元件而形成之封裝層的積 分軎丨J，以製造含有上述電路 、g豆 係包括下列步驟： 體I置’其特徵 2上述積層體之表面形成分割溝，令上述 面露出的步驟； 以導電性材料覆蓋上述積層體之表面側， 上述配線電性連接之遮蔽膜的步驟；及 成、 將上述積層體從背m上述分m 積層體之上述電路元件從其他區域分割的步驟。而將该 如申請專利範圍第3項之半導體裝置的製造方法，並 中，另包括令上述配線接地的步驟。 315564 20 、如申請專利範圍第3項之半導體裝置的製造方法，其 中，於上述絕緣層上搭載複數個電路元件，且在上述配 線之側面露出之步驟前，上述配線係連接於上述複數個 電路元件而設置， 並且在令上述配線之側面露出的步驟中，分割上述 _、、泉而4义剎後的各配線係以分別連接於上述各電路 凡件之方式，形成上述分割溝。 )·如申請專利範圍第4項之半導體裝置的製造方法，其 於上述絕緣層上搭載複數個電路元件，且在上述配 線之側面露出之步驟前，上述配線係連接於上述複數個 電路元件而設置， 並且在令上述配線之側面露出的步驟中，分割上述 、友、以忒分割後的各配線分別連接於上述各電路元件 之方式，形成上述分割溝。 7 如申清專利範圍第3項之半導體裝置的製造方法，其 * ，另包括以保護膜覆蓋上述遮蔽膜之步驟，而該保護 \係由耐腐蝕性比構成該遮蔽膜之材料更高的材料 構成。 8 如申請專利範圍第4項之半導體裝置的製造方法，其 * /另包括以保護膜覆蓋上述遮蔽膜之步驟，而該保護 \仏由耐腐蝕性比構成該遮蔽膜之材料更高的材料所 構成。 9·如申請專利範圍第5項之半導體裝置的製造方法，其 中另包括以保護膜覆蓋上述遮蔽膜之步驟，而該保護 315564 21 200427025 膜係由对腐#性比構成該遮蔽膜之材料更高的材料所 構成。
    22 315564
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