CN102862945A - 塑封内空封装的结构 - Google Patents
塑封内空封装的结构 Download PDFInfo
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K5/00—Casings, cabinets or drawers for electric apparatus
- H05K5/0091—Housing specially adapted for small components
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0154—Moulding a cap over the MEMS device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Microelectronics & Electronic Packaging (AREA)
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
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- Packaging Frangible Articles (AREA)
Abstract
本发明公开一种塑封内空封装的结构,尤指为微机电芯片的封装,主要包括有一电路板、微机电芯片及套盖,先将微机电芯片固设于电路板上后利用连接导线接通电讯,再利用套盖覆盖于电路板之上并将微机电芯片予以阻隔后形成微机电芯片组,再于外部进行封装,藉此可有效降低微机电芯片受外界电磁辐射、光线及物理性的干扰破坏,以提高其稳定性及运作良好外,更具有简化工艺步骤以达到提高产量及降低制造成本为其主要发明要点。
Description
技术领域
本发明涉及一种塑封内空封装的结构,尤其涉及微机电芯片的封装(Package),主要是利用套盖(Can)有效的阻隔微机电芯片(MEMS DIE)免受外界电磁辐射、光线及物理性的干扰破坏,以提高其稳定性及运作良好外,更具有简化工艺步骤以达到提高产量及降低制造成本等效能。
背景技术
现有微机电芯片的封装结构,中国台湾专利号第I324890『微机电系统装置及其制造方法』,其主要是先提供盖体晶圆(圆片)及一微机电系统晶圆,将该盖体晶圆与微机电系统晶圆予以接合,再利用薄膜覆盖盖体晶圆的顶面,并将多个接合有盖体晶圆的微机电系统晶圆设置于一胶带上,然后将结合后的盖体晶圆及微机电系统晶圆予以切割,以形成微机电系统结构,然后将该微机电系统结构连接于一基板上,再利用封胶将基板及微机电系统结构予以封装,其中,该微机电系统结构在进行切割时,会令微机电系统晶圆顶面预留有一打线区;然而此种制作方法与结构在工艺上需经过两次作业程序才能进行封装,不仅耗费工时、浪费原料(因同时要备有盖体晶圆跟微机电系统晶圆)及成本高涨外,其工艺的繁复也容易使得产量的延滞;另外,为了达到节省不浪费晶圆的目的,在进行微机电系统结构的切割时,仅会预留边侧有限空间进行打线,然在进行封装时的冲压压力是相当的大,仅利用边侧些许空间进行打线,在强力的冲压下很容易就造成打线脱落,进而易造成暇疵品的提高。
因此为有效解决上述缺失,本发明提出此一利用套盖的直接套设以达到直接进行封装,除能有效降低微机电芯片受外界电磁辐射、光线及物理性的干扰破坏,以提高其稳定性及运作良好外,更具有简化工艺步骤以达到提高产量及降低制造成本以符合产业的利用。
发明内容
本发明的目的在于提供一种塑封内空封装的结构,主要通过套盖的有效的阻隔,以令微机电芯片(MEMS DIE)免受外界电磁辐射、光线及物理性的干扰破坏,提高其稳定性及运作良好外,更具有简化工艺步骤以达到提高产量及降低制造成本等效能为其主要创作目的。
为达上述目的,本发明提供一种塑封内空封装的结构,包括有:
一电路板;
一微机电芯片;
一连接导线,两端焊接微机电芯片及电路板,以达成电讯连结;
一套盖,两侧端延伸设有套盖连接杆,内呈中空状,通过上述构件而组合成微机电芯片组;
一封胶模具,通过该封胶模具对微机电芯片组进行封装。
上述的塑封内空封装的结构,其中该电路板内适当位置处嵌设有电路板中电路。
上述的塑封内空封装的结构,其中微机电芯片利用芯片黏着材而可与电路板相接合。
上述的塑封内空封装的结构,其中套盖利用套盖黏着材而能够与电路板相接合。
上述的塑封内空封装的结构,其中该封胶模具包括有上模及下模。
上述的塑封内空封装的结构,其中该套盖的形状包括方形、圆形、矩形、多角形形态。
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
附图说明
图1为本发明的塑封内空封装的结构的微机电芯片组组合剖视示意图;
图2为本发明的塑封内空封装的结构的微机电芯片组于模具内封装的组合剖视示意图;
图3为本发明的塑封内空封装的结构的微机电芯片组封装完成的组合剖视示意图;
图4为本发明的塑封内空封装的结构切割后单一封装完成微机电芯片组的组合剖视示意图;
图5为本发明的塑封内空封装的结构另一较佳实施例示意图。
其中,附图标记
电路板 100
电路板中电路 101
电路板的顶端 102
套盖黏着材 200
芯片黏着材 300
微机电芯片 400
连接导线 401
套盖 500
套盖连接杆 501
内空部 502
空隙处 503
封合树脂 600
微机电芯片组 700
顶端 701
封胶模具 800(Mold Compound)
上模 801(Upper Mold)
下模 802(Lower Mold)
具体实施方式
下面结合附图对本发明的结构原理和工作原理作具体的描述:
请参阅图1所示,主要包括有一电路板(Circuit board)100,该电路板100内嵌设有电路板中电路101,在电路板的顶端102,涂布有套盖黏着材200,以供黏着套盖500之用;
有一微机电芯片400,一端面利用芯片黏着材300而可与电路板100相接合;
有一连接导线401,两端分别焊设于微机电芯片400及电路板100内嵌设的电路板中电路101,利用该连接导线401而能使微机电芯片400与电路板100达成电讯连结;
有一套盖500,该套盖500是呈内凹容器体状,即周缘圈闭而一端封闭,另一端则开放的型态,在其开放的一端的两侧延伸有套盖连接杆501,为了达到大量制造的目的,该套盖500与套盖连接杆501是呈连续状,也即一个套盖500连结一套盖连接杆501后再连结一套盖500;其中该套盖的形状可为方形、圆形、矩形、多角形等各种形态;
当微机电芯片400要进行封装时,由于微机电芯片400是一种极易收幅射及污染而损坏的芯片,因此需在呈无尘无污染的环境中进行,此时先在电路板100中预先嵌设有一电路板中电路101,再于电路板100的顶面适当位置处分别涂布有套盖黏着材200及芯片黏着材300,其中,在涂布套盖黏着材200及芯片黏着材300时,都必须闪避掉电路板中电路101的范围,以避免影响电讯的连结;
当套盖黏着材200及芯片黏着材300被涂布完毕后,便先将微机电芯片400置于芯片黏着材300之上完成固定,然后于微机电芯片400非与芯片黏着材300接合的一面焊设连接导线401的一端,并将连接导线401的另一端焊设于电路板100的电路板中电路101上,以达成电讯的连结;
当微机电芯片400完成固定及电讯连结后,便将套盖500置于电路板100之上,并将微机电芯片400、连接导线401及电路板中电路101均被封闭于套盖500的内空部502的空间内,同时令套盖500的套盖连杆501能因套盖黏着材300的作用而被黏合于电路板100之上不致脱落,如此便构成微机电芯片组700;
请再参阅图2、图3及图4所示,当微机电芯片组700被组合完成后,便将该微机电芯片组700置于封胶模具800的下模802中,然后再由上端将封胶模具800的上模801下压于微机电芯片组700的顶端701,同时施加压力令套盖500与电路板100黏合得更紧密,之后再进行灌模封胶,将封合树脂600填充于套盖500位于套盖连接杆501上端的空隙处503以完成微机电芯片组700的封装,然后将多个同时被封装完成的微机电芯片组700进行切割成单一个体,即完成此一高稳定性、高良率及封装步骤简化的微机电芯片;
请参阅图5所示,图5为本发明塑封内空封装的结构另一较佳实施例图示,其差异在于置于套盖500内的微机电芯片,可利用芯片黏着材300使两个以上的微机电芯片400,在套盖500的内空部502可允许的空间内多个叠置,以达到提高单一微机电芯片组700的电性容量等效能;
综上所述,本发明为塑封内空封装的结构,较现有技术(如I324890),在工艺上不仅简化许多,在原料的使用上也较现有技术节略,同时在其电讯的稳定性上,也能较现有技术为高,不仅能有效降低污染的机率,更能简化工艺、减少用料、降低成本、提高良率,其具有结构的新颖性、产业的实用性与利用性无疑。
当然,本发明还可有其他多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (6)
1.一种塑封内空封装的结构,其特征在于,包括有:
一电路板;
一微机电芯片;
一连接导线,两端焊接微机电芯片及电路板,以达成电讯连结;
一套盖,两侧端延伸设有套盖连接杆,内呈中空状,通过上述构件而组合成微机电芯片组;
一封胶模具,通过该封胶模具对微机电芯片组进行封装。
2.根据权利要求1所述的塑封内空封装的结构,其特征在于,该电路板内适当位置处嵌设有电路板中电路。
3.根据权利要求1所述的塑封内空封装的结构,其特征在于,微机电芯片利用芯片黏着材而可与电路板相接合。
4.根据权利要求1所述的塑封内空封装的结构,其特征在于,套盖利用套盖黏着材而能够与电路板相接合。
5.根据权利要求1所述的塑封内空封装的结构,其特征在于,该封胶模具包括有上模及下模。
6.根据权利要求1所述的塑封内空封装的结构,其特征在于,该套盖的形状包括方形、圆形、矩形、多角形形态。
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US201161503619P | 2011-07-01 | 2011-07-01 | |
US61/503,619 | 2011-07-01 |
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US (1) | US20130070424A1 (zh) |
CN (1) | CN102862945A (zh) |
TW (1) | TW201308547A (zh) |
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CN102862946A (zh) * | 2011-07-08 | 2013-01-09 | 英属维尔京群岛商杰群科技有限公司 | 塑封预模内空封装的结构 |
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2012
- 2012-06-29 TW TW101123351A patent/TW201308547A/zh unknown
- 2012-06-29 CN CN2012102259524A patent/CN102862945A/zh active Pending
- 2012-07-01 US US13/539,453 patent/US20130070424A1/en not_active Abandoned
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US5930603A (en) * | 1996-12-02 | 1999-07-27 | Fujitsu Limited | Method for producing a semiconductor device |
CN1204144A (zh) * | 1997-06-27 | 1999-01-06 | 松下电子工业株式会社 | 树脂封装型半导体装置的制造方法 |
US20080174013A1 (en) * | 2005-01-05 | 2008-07-24 | Jun Young Yang | Semiconductor device package and manufacturing method thereof |
US20070013036A1 (en) * | 2005-07-15 | 2007-01-18 | Silicon Matrix Pte Ltd | MEMS package using flexible substrates, and method thereof |
CN2847525Y (zh) * | 2005-08-30 | 2006-12-13 | 资重兴 | 裸晶封装的保护结构 |
CN201204202Y (zh) * | 2007-12-12 | 2009-03-04 | 昆山钜亮光电科技有限公司 | 一种芯片封装结构 |
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TW201308547A (zh) | 2013-02-16 |
US20130070424A1 (en) | 2013-03-21 |
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