CN201927599U - 双面图形芯片倒装先镀后刻模组封装结构 - Google Patents

双面图形芯片倒装先镀后刻模组封装结构 Download PDF

Info

Publication number
CN201927599U
CN201927599U CN2010205178351U CN201020517835U CN201927599U CN 201927599 U CN201927599 U CN 201927599U CN 2010205178351 U CN2010205178351 U CN 2010205178351U CN 201020517835 U CN201020517835 U CN 201020517835U CN 201927599 U CN201927599 U CN 201927599U
Authority
CN
China
Prior art keywords
pin
chip
plastic packaging
packaging material
epoxy resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2010205178351U
Other languages
English (en)
Inventor
王新潮
梁志忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN2010205178351U priority Critical patent/CN201927599U/zh
Application granted granted Critical
Publication of CN201927599U publication Critical patent/CN201927599U/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本实用新型涉及一种双面图形芯片倒装先镀后刻模组封装结构,包括引脚(2)、无填料的塑封料(环氧树脂)(3)、锡金属的粘结物质(6)、芯片(7)和有填料塑封料(环氧树脂)(9),在所述引脚(2)外围的区域以及引脚(2)与引脚(2)之间的区域嵌置有无填料的塑封料(环氧树脂)(3),所述无填料的塑封料(环氧树脂)(3)将引脚下部外围以及引脚(2)下部与引脚(2)下部连接成一体,且使所述引脚背面尺寸小于引脚正面尺寸,形成上大下小的引脚结构,其特征在于所述所述引脚(2)正面延伸到后续贴装芯片的下方,在所述后续贴装芯片的下方的引脚(2)正面第一金属层(4)上通过锡金属的粘结物质(6)设置有芯片(7),在所述引脚(2)的上部以及芯片(7)外包封有填料塑封料(环氧树脂)(9)。本实用新型芯片封装结构不会再有产生掉脚的问题。

Description

双面图形芯片倒装先镀后刻模组封装结构
(一)技术领域
本实用新型涉及一种双面图形芯片倒装先镀后刻模组封装结构。属于半导体封装技术领域。
(二)背景技术
传统的芯片封装结构的制作方式是:采用金属基板的正面进行化学蚀刻及表面电镀层后,即完成引线框的制作(如图13所示)。而引线框的背面则在封装过程中再进行蚀刻。该法存在以下不足:
因为塑封前只在金属基板正面进行了半蚀刻工作,而在塑封过程中塑封料只有包裹住引脚半只脚的高度,所以塑封体与引脚的束缚能力就变小了,如果塑封体贴片到PCB板上不是很好时,再进行返工重贴,就容易产生掉脚的问题(如图14所示)。尤其塑封料的种类是采用有填料时候,因为材料在生产过程的环境与后续表面贴装的应力变化关系,会造成金属与塑封料产生垂直型的裂缝,其特性是填料比例越高则越硬越脆越容易产生裂缝。
另外,由于芯片与引脚之间的距离较远,金属线的长度较长,如图15~16所示,金属线成本较高(尤其是昂贵的纯金质的金属线);同样由于金属线的长度较长,使得芯片的信号输出速度较慢(尤其是存储类的产品 以及需要大量数据的计算,更为突出);也同样由于金属线的长度较长,所以在金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也较高;再由于芯片与引脚之间的距离较远,使得封装的体积与面积较大,材料成本较高,废弃物较多。
(三)发明内容
本实用新型的目的在于克服上述不足,提供一种不会再有产生掉脚的问题的双面图形芯片倒装先镀后刻模组封装结构。
本实用新型的目的是这样实现的:一种双面图形芯片倒装先镀后刻模组封装结构,包括引脚、无填料的塑封料(环氧树脂)、锡金属的粘结物质、芯片和有填料塑封料(环氧树脂),在所述引脚的正面设置有第一金属层,在所述引脚的背面设置有第二金属层,在所述引脚外围的区域以及引脚与引脚之间的区域嵌置有无填料的塑封料(环氧树脂),所述无填料的塑封料(环氧树脂)将引脚下部外围以及引脚下部与引脚下部连接成一体,且使所述引脚背面尺寸小于引脚正面尺寸,形成上大下小的引脚结构,其特征在于所述引脚正面延伸到后续贴装芯片的下方,在所述后续贴装芯片的下方的引脚正面第一金属层上通过锡金属的粘结物质设置有芯片,在所述引脚的上部以及芯片外包封有填料塑封料(环氧树脂)。
本实用新型的有益效果是:
1、确保不会再有产生掉脚的问题
由于引线框采用了双面蚀刻的工艺技术,所以可以轻松的规划设计与制造出上大下小的引脚结构,可以使上下层塑封料紧密的将上大下小的引 脚结构一起包裹住,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题。
2、由于应用了引线框背面与正面分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到封装体的中心,促使芯片与引脚位置能够与芯片键合的位置相同,如图12所示,如此电性的传输将可大幅度提升(尤其存储类的产品以及需要大量数据的计算,更为突出)。
3、使封装的体积与面积可以大幅度的缩小
因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚与脚之间的距离,使得封装的体积与面积可以大幅度的缩小。
4、材料成本和材料用量减少
因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。
(四)附图说明
图1(A)~图1(Q)为本实用新型双面图形芯片倒装先镀后刻模组封装结构实施例1各工序示意图。
图2为本实用新型双面图形芯片倒装模组封装结构实施例1结构示意图。
图3为图2的俯视图。
图4(A)~图4(Q)为本实用新型双面图形芯片倒装先镀后刻模组封装结构实施例2各工序示意图。
图5为本实用新型双面图形芯片倒装模组封装结构实施例2结构示意 图。
图6为图5的俯视图。
图7(A)~图7(Q)为本实用新型双面图形芯片倒装先镀后刻模组封装结构实施例3各工序示意图。
图8为本实用新型双面图形芯片倒装模组封装结构实施例3结构示意图。
图9为图8的俯视图。
图10(A)~图10(Q)为本实用新型双面图形芯片倒装先镀后刻模组封装结构实施例4各工序示意图。
图11为本实用新型双面图形芯片倒装模组封装结构实施例4结构示意图。
图12为图11的俯视图。
图13为以往采用金属基板的正面进行化学蚀刻及表面电镀层作业图。
图14为以往形成的掉脚图。
图15为以往的封装结构一示意图。
图16为图15的俯视图。
图中附图标记:
引脚2、无填料的塑封料(环氧树脂)3、第一金属层4、第二金属层5、锡金属的粘结物质6、芯片7、有填料塑封料(环氧树脂)9、金属基板10、光阻胶膜11、光阻胶膜12、光阻胶膜13、光阻胶膜14、光阻胶膜15、光阻胶膜16。
(五)具体实施方式
本实用新型双面图形芯片倒装先镀后刻模组封装结构如下:
实施例1:单芯片单圈引脚
参见图2和图3,图2为本实用新型双面图形芯片倒装模组封装结构实施例1结构示意图。图3为图2的俯视图。由图2和图3可以看出,本实用新型双面图形芯片倒装模组封装结构,包括引脚2、无填料的塑封料(环氧树脂)3、锡金属的粘结物质6、芯片7和有填料塑封料(环氧树脂)9,所述引脚2正面延伸到后续贴装芯片的下方,在所述引脚2的正面设置有第一金属层4,在所述引脚2的背面设置有第二金属层5,在所述后续贴装芯片的下方的引脚2正面第一金属层4上通过锡金属的粘结物质6设置有芯片7,在所述引脚2的上部以及芯片7外包封有填料塑封料(环氧树脂)9,在所述引脚2外围的区域以及引脚2与引脚2之间的区域嵌置有无填料的塑封料(环氧树脂)3,所述无填料的塑封料(环氧树脂)3将引脚下部外围以及引脚2下部与引脚2下部连接成一体,且使所述引脚背面尺寸小于引脚正面尺寸,形成上大下小的引脚结构。
其封装方法如下:
步骤一、取金属基板
参见图1(A),取一片厚度合适的金属基板10。金属基板的材质可以依据芯片的功能与特性进行变换,例如:铜、铝、铁、铜合金或镍铁合金等。
步骤二、金属基板正面及背面被覆光阻胶膜
参见图1(B),利用被覆设备在金属基板的正面及背面分别被覆可进行 曝光显影的光阻胶膜11和12,以保护后续的电镀金属层工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。
步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗
参见图1(C),利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域。
步骤四、金属基板正面已开窗的区域进行金属层电镀被覆
参见图1(D),对步骤三中金属基板正面已开窗的区域进行第一金属层4电镀被覆,该第一金属层4置于所述引脚2的正面。
步骤五、金属基板正面及背面进行光阻胶膜去膜
参见图1(E),将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除。
步骤六、金属基板正面及背面被覆光阻胶膜
参见图1(F),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜13和14,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。
步骤七、金属基板背面的光阻胶膜进行需要蚀刻区域的曝光/显影以及开窗
参见图1(G),利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后 续需要进行的金属基板背面蚀刻作业。
步骤八、金属基板进行背面蚀刻作业
参见图1(H),完成步骤七的曝光/显影以及开窗作业后,即在金属基板的背面进行各图形的蚀刻作业,蚀刻出引脚2的背面,同时将引脚正面尽可能的延伸到所述后续贴装芯片的下方。
步骤九、金属基板正面及背面进行光阻胶膜去膜
参见图1(I),将金属基板背面余下的光阻胶膜和金属基板正面的光阻胶膜全部揭除。
步骤十、包封无填料的塑封料(环氧树脂)
参见图1(J),将已完成步骤九所述去膜作业的金属基板背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使引脚2外围的区域以及引脚2与引脚2之间的区域均嵌置无填料的塑封料(环氧树脂)3,该无填料的塑封料(环氧树脂)3将引脚下部外围以及引脚2下部与引脚2下部连接成一体。
步骤十一、被覆光阻胶膜
参见图1(K),利用被覆设备在将已完成包封无填料塑封料作业的金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜15和16,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。
步骤十二、已完成包封无填料塑封料作业的金属基板的正面进行需要蚀刻区域的曝光/显影以及开窗
参见图1(L),利用曝光显影设备将步骤十一完成光阻胶膜被覆作业的已完成包封无填料塑封料作业的金属基板正面进行曝光显影去除部分光阻胶膜,以备后续需要进行金属基板正面蚀刻作业。
步骤十三、金属基板正面蚀刻作业
参见图1(M),完成步骤十二的曝光/显影以及开窗作业后,即在完成包封无填料塑封料作业的金属基板正面进行各图形的蚀刻作业,蚀刻出引脚2的正面,且使所述引脚2的背面尺寸小于引脚2的正面尺寸,形成上大下小的引脚2结构。
步骤十四、金属基板正面及背面进行光阻胶膜去膜
参见图1(N),将完成步骤十三蚀刻作业的金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,制成引线框。
步骤十五、装片
参见图1(O),在所述后续贴装芯片的下方的引脚2正面第一金属层4上通过锡金属的粘结物质6进行芯片7的植入。
步骤十六、包封有填料塑封料(环氧树脂)
参见图1(P),将已装片完成的半成品正面进行包封有填料塑封料(环氧树脂)9作业,并进行塑封料包封后的固化作业,使引脚的上部以及芯片外均被有填料塑封料(环氧树脂)包封。
步骤十七、引脚的背面进行金属层电镀被覆
参见图1(Q),对已完成步骤十六包封有填料塑封料(环氧树脂)作业的所述引脚的背面进行第二金属层5电镀被覆作业,而电镀的材料可以是 锡、镍金、镍钯金....等金属材质。
步骤十八、切割成品
参见图2和图3,将已完成步骤十七第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片倒装模组封装结构成品。
实施例2:单芯片多圈引脚
参见图4~6,图4(A)~图4(Q)为本实用新型双面图形芯片倒装先镀后刻模组封装结构实施例2各工序示意图。图5为本实用新型双面图形芯片倒装模组封装结构实施例2结构示意图。图6为图5的俯视图。由图4、图5和图6可以看出,实施例2与实施例1的不同之处仅在于:所述引脚2设备有多圈。
实施例3:多芯片单圈引脚
参见图7~9,图7(A)~图7(Q)为本实用新型双面图形芯片倒装先镀后刻模组封装方法实施例3各工序示意图。图8为本实用新型双面图形芯片倒装模组封装结构实施例3结构示意图。图9为图8的俯视图。由图7、图8和图9可以看出,实施例3与实施例1的不同之处仅在于:所述芯片7设置有多颗。
实施例4:多芯片多圈引脚
参见图10~12,图10(A)~图10(Q)为本实用新型双面图形芯片倒装先镀后刻模组封装结构实施例4各工序示意图。图11为本实用新型双面图形芯片倒装模组封装结构实施例4结构示意图。图12为图11的俯视图。由图 10、图11和图12可以看出,实施例4与实施例1的不同之处仅在于:所述引脚2设备有多圈,芯片7设置有多颗。

Claims (4)

1.一种双面图形芯片倒装先镀后刻模组封装结构,包括引脚(2)、无填料的塑封料(3)、锡金属的粘结物质(6)、芯片(7)和有填料塑封料(9),在所述引脚(2)的正面设置有第一金属层(4),在所述引脚(2)的背面设置有第二金属层(5),在所述引脚(2)外围的区域以及引脚(2)与引脚(2)之间的区域嵌置有无填料的塑封料(3),所述无填料的塑封料(3)将引脚下部外围以及引脚(2)下部与引脚(2)下部连接成一体,且使所述引脚背面尺寸小于引脚正面尺寸,形成上大下小的引脚结构,其特征在于所述引脚(2)正面延伸到后续贴装芯片的下方,在所述后续贴装芯片的下方的引脚(2)正面第一金属层(4)上通过锡金属的粘结物质(6)设置有芯片(7),在所述引脚(2)的上部以及芯片(7)外包封有填料塑封料(9)。
2.根据权利要求1所述的一种双面图形芯片倒装先镀后刻模组封装结构,其特征在于所述引脚(2)设置有多圈。
3.根据权利要求1所述的一种双面图形芯片倒装先镀后刻模组封装结构,其特征在于所述芯片(7)设置有多颗。
4.根据权利要求1所述的一种双面图形芯片倒装先镀后刻模组封装结构,其特征在于所述引脚(2)设置有多圈,芯片(7)设置有多颗。 
CN2010205178351U 2010-09-04 2010-09-04 双面图形芯片倒装先镀后刻模组封装结构 Expired - Lifetime CN201927599U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2010205178351U CN201927599U (zh) 2010-09-04 2010-09-04 双面图形芯片倒装先镀后刻模组封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2010205178351U CN201927599U (zh) 2010-09-04 2010-09-04 双面图形芯片倒装先镀后刻模组封装结构

Publications (1)

Publication Number Publication Date
CN201927599U true CN201927599U (zh) 2011-08-10

Family

ID=44431436

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010205178351U Expired - Lifetime CN201927599U (zh) 2010-09-04 2010-09-04 双面图形芯片倒装先镀后刻模组封装结构

Country Status (1)

Country Link
CN (1) CN201927599U (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102867805A (zh) * 2012-09-24 2013-01-09 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN113555328A (zh) * 2021-04-02 2021-10-26 江苏尊阳电子科技有限公司 一种背面先蚀的封装结构的封装工艺

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102867805A (zh) * 2012-09-24 2013-01-09 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN113555328A (zh) * 2021-04-02 2021-10-26 江苏尊阳电子科技有限公司 一种背面先蚀的封装结构的封装工艺

Similar Documents

Publication Publication Date Title
CN101958300B (zh) 双面图形芯片倒装模组封装结构及其封装方法
CN101814482B (zh) 有基岛引线框结构及其生产方法
CN101814481B (zh) 无基岛引线框结构及其生产方法
CN101840901B (zh) 无基岛静电释放圈引线框结构及其生产方法
CN101958257B (zh) 双面图形芯片直接置放先镀后刻模组封装方法
CN101950726B (zh) 双面图形芯片正装先镀后刻单颗封装方法
CN101969032B (zh) 双面图形芯片正装先镀后刻模组封装方法
CN101958299B (zh) 双面图形芯片直接置放先镀后刻单颗封装方法
CN201927599U (zh) 双面图形芯片倒装先镀后刻模组封装结构
CN201936875U (zh) 双面图形芯片正装模组封装结构
CN102005430B (zh) 双面图形芯片倒装先镀后刻模组封装方法
CN101958303B (zh) 双面图形芯片正装单颗封装结构及其封装方法
CN202003984U (zh) 双面图形芯片倒装先镀后刻单颗封装结构
CN101958301B (zh) 双面图形芯片直接置放单颗封装结构及其封装方法
CN201838577U (zh) 双面图形芯片倒装模组封装结构
CN101958305B (zh) 双面图形芯片正装模组封装结构及其封装方法
CN102005431B (zh) 双面图形芯片倒装先镀后刻单颗封装方法
CN101958302B (zh) 双面图形芯片倒装单颗封装结构及其封装方法
CN201838576U (zh) 双面图形芯片直接置放单颗封装结构
CN101958304B (zh) 双面图形芯片直接置放模组封装结构及其封装方法
CN202003985U (zh) 双面图形芯片直接置放先镀后刻单颗封装结构
CN201838579U (zh) 双面图形芯片直接置放模组封装结构
CN201838580U (zh) 双面图形芯片倒装单颗封装结构
CN201681935U (zh) 无基岛多圈脚静电释放圈无源器件封装结构
CN201681897U (zh) 无基岛多圈脚静电释放圈封装结构

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20110810