CN102027591B - 半导体模块、半导体模块的制造方法及便携式设备 - Google Patents
半导体模块、半导体模块的制造方法及便携式设备 Download PDFInfo
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- CN102027591B CN102027591B CN2009801172074A CN200980117207A CN102027591B CN 102027591 B CN102027591 B CN 102027591B CN 2009801172074 A CN2009801172074 A CN 2009801172074A CN 200980117207 A CN200980117207 A CN 200980117207A CN 102027591 B CN102027591 B CN 102027591B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 324
- 238000000034 method Methods 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 229920005989 resin Polymers 0.000 claims abstract description 244
- 239000011347 resin Substances 0.000 claims abstract description 244
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 36
- 230000008569 process Effects 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 26
- 238000002788 crimping Methods 0.000 claims description 18
- 238000005520 cutting process Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 257
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 59
- 239000010949 copper Substances 0.000 description 50
- 229910052802 copper Inorganic materials 0.000 description 48
- 238000001259 photo etching Methods 0.000 description 13
- 235000012431 wafers Nutrition 0.000 description 12
- 239000011889 copper foil Substances 0.000 description 11
- 239000011241 protective layer Substances 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 229920000647 polyepoxide Polymers 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 6
- 125000003700 epoxy group Chemical group 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- 239000004033 plastic Substances 0.000 description 5
- 238000007772 electroless plating Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 238000004873 anchoring Methods 0.000 description 2
- 239000007767 bonding agent Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 210000004877 mucosa Anatomy 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- H01L2224/03436—Lamination of a preform, e.g. foil, sheet or layer
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract
本发明提供一种半导体模块、半导体模块的制造方法及便携式设备,在CSP型半导体模块的制造方法中,提高半导体模块的生产效率。该半导体模块的制造方法包含如下工序:将形成有多个半导体元件(10)的半导体晶片(1)粘接在具有伸展性的第一绝缘树脂层(20)上的工序,其中所述半导体元件(10)具有元件电极(12);切割半导体晶片(1)的工序;拉伸第一绝缘树脂层(20)以扩大半导体元件(10)的间隔的工序;隔着第二绝缘树脂层将设置有电极的金属板和扩大了间隔的状态的多个半导体元件(10)压接,使电极与元件电极(12)电连接的压接工序;选择性地除去金属板以形成与各半导体元件(10)对应的配线层,并形成通过第一绝缘树脂层(20)和第二绝缘树脂层连结的多个半导体模块的工序;切断第一绝缘树脂层(20)及第二绝缘树脂层以实现半导体模块的单个化的工序。
Description
技术领域
本发明涉及半导体模块、半导体模块的制造方法及便携式设备。
背景技术
在便携式电话、PDA、DVC、DSC之类的便携式电子设备的高功能化的加速过程中,为了使此类产品被市场接受,必须实现小型化、轻量化,为此需要高度集成的系统LSI。对于这些电子设备而言,要求容易使用而方便,而对于设备所使用的LSI而言,要求高功能化、高性能化。为此,伴随着LSI芯片的高度集成化,其I/O数(输入输出部的数量)增多,同时对于封装自身的小型化要求也增强,为了兼顾这两方面,强烈要求开发出适合于半导体部件的密度高的基板安装的半导体封装。为了应对这种需求,正在开发各种被称为CSP(Chip Size Package:芯片尺寸封装)的封装技术。
CSP能够以与LSI芯片相同的尺寸固定于安装基板,可以使安装有CSP的一侧的安装基板小型化。因此,通过采用CSP,也可以使电子设备等的整体设置小型化。
在如上所述的CSP型半导体模块的制造方法中,作为用于减少其工序数的方法,提出有以下方法(参照专利文献1)。即,该方法首先将具有外部连接电极的半导体结构体彼此分开配置于基板上,并在半导体结构体的周侧面形成绝缘层。接着,利用绝缘膜覆盖半导体结构体和绝缘层,在绝缘膜上配置具有突起电极的金属板,使突起电极侵入绝缘膜与外部连接电极连接。之后,对金属板进行构图以形成再配线,从而完成半导体模块。
专利文献1:(日本)特开2004-349361号公报
在以往的CSP型半导体模块的制造方法中,形成有多个半导体元件的半导体晶片以粘着于切割带等的状态被切割。接着,将通过切割实现单个化的各半导体元件一个一个地从切割带剥离,并在构成支承体的基板上彼此分开配置以形成半导体模块。因此,半导体元件的配置需要花费时间,这成为导致半导体模块的生产效率降低的主要原因。
发明内容
本发明是由发明人基于上述的认识而作出的,其目的在于提供一种在CSP型半导体模块的制造方法中提高半导体模块的生产效率的技术。
为了解决上述课题,本发明的一形态是半导体模块的制造方法。该半导体模块的制造方法具有如下工序:将形成有多个半导体元件的半导体基板粘接在具有伸展性的第一绝缘树脂层上的工序,其中所述半导体元件在一侧的主表面设置有元件电极;将半导体基板切割而单个化成多个半导体元件的工序;拉伸第一绝缘树脂层以扩大多个半导体元件的间隔的工序;隔着第二绝缘树脂层将设置有突起电极的金属板和在第一绝缘树脂层上处于扩大间隔的状态的多个半导体元件压接,使突起电极贯通第二绝缘树脂层,从而将突起电极和元件电极电连接的压接工序,其中,所述突起电极与设置于各半导体元件的元件电极相对;选择性地除去金属板以形成与各半导体元件对应的配线层,并形成通过第一绝缘树脂层和第二绝缘树脂层连结的多个半导体模块的工序;将第一绝缘树脂层及第二绝缘树脂层切断而将半导体模块单个化的工序。
根据该形态,在CSP型半导体模块的制造方法中,能够提高半导体模块的生产效率。
本发明的另一个形态也是半导体模块的制造方法。该半导体模块的制造方法具有如下工序:将形成有多个半导体元件的半导体基板粘接在具有伸展性的第一绝缘树脂层上的工序,其中所述半导体元件在一侧的主表面设置有元件电极;将半导体基板切割而单个化成多个半导体元件的工序;拉伸第一绝缘树脂层以扩大多个半导体元件的间隔的工序;隔着第二绝缘树脂层将在第一绝缘树脂层上处于扩大间隔的状态的多个半导体元件与金属板压接的工序;选择性地除去金属板和第二绝缘树脂层以形成多个通孔,并在通孔内形成通孔电极以使其与元件电极电连接的工序;选择性地除去金属板以形成与各半导体元件对应的配线层,并形成通过第一绝缘树脂层和第二绝缘树脂层连结的多个半导体模块的工序;将第一绝缘树脂层及第二绝缘树脂层切断而将半导体模块单个化的工序。
本发明的又一形态也是半导体模块的制造方法。该半导体模块的制造方法具有如下工序:将形成有多个半导体元件的半导体基板粘接在具有伸展性的第一绝缘树脂层上的工序,其中所述半导体元件在一侧的主表面设置有元件电极;将半导体基板切割而单个化成多个半导体元件的工序;拉伸第一绝缘树脂层以扩大多个半导体元件的间隔的工序;在设置有与设置于各半导体元件的元件电极相对的突起电极的金属板上层叠第二绝缘树脂层,使突起电极贯通第二绝缘树脂层,将在第一绝缘树脂层上处于扩大间隔的状态的多个半导体元件与金属板贴合,使突起电极和元件电极电连接的工序;除去第一绝缘树脂层,并将将第三绝缘树脂层的另一侧的主表面与半导体元件的另一侧的主表面相配合而使在一侧的主表面具有金属层的第三绝缘树脂层与半导体元件压接的工序;选择性地除去金属板以形成与各半导体元件对应的配线层,并形成通过第二绝缘树脂层和第三绝缘树脂层连结的多个半导体模块的工序;将第二绝缘树脂层及第三绝缘树脂层切断而将半导体模块单个化的工序。
本发明的又一形态也是半导体模块的制造方法。该半导体模块的制造方法具有如下工序:将形成有多个半导体元件的半导体基板粘接在具有伸展性的第一绝缘树脂层上的工序,其中所述半导体元件在一侧的主表面设置有元件电极;将半导体基板切割而单个化成多个半导体元件的工序;拉伸第一绝缘树脂层以扩大多个半导体元件的间隔的工序;隔着第二绝缘树脂层将在第一绝缘树脂层上处于扩大间隔的状态的多个半导体元件与金属板贴合的工序;除去第一绝缘树脂层,并将第三绝缘树脂层的另一侧的主表面与半导体元件的另一侧的主表面相配合而使在一侧的主表面具有金属层的第三绝缘树脂层与半导体元件压接的工序;选择性地除去金属板和第二绝缘树脂层以形成多个通孔,并在通孔内形成通孔电极以使其与元件电极电连接的工序;选择性地除去金属板以形成与各半导体元件对应的配线层,并形成通过第二绝缘树脂层和第三绝缘树脂层连结的多个半导体模块的工序;将第二绝缘树脂层及第三绝缘树脂层切断而将半导体模块单个化的工序。
在上述形态中,在形成配线层时,可以与配线层的形成区域相对应而选择性地除去金属层。或者,在形成配线层时,可以将金属层全部除去。
本发明的另一形态是半导体模块。该半导体模块具有:在一侧的主表面设置有元件电极的半导体元件、设置于半导体元件另一侧的主表面的第一绝缘树脂层、设置有与元件电极相对的电极的配线层,以及设置于配线层和半导体元件之间的第二绝缘树脂层,电极贯通第二绝缘树脂层以使电极与元件电极电连接,第一绝缘树脂层和第二绝缘树脂层之间的界面与半导体元件的侧面相接,并且,半导体元件的侧面被第一绝缘树脂层和第二绝缘树脂层覆盖,半导体元件侧方的第一绝缘树脂层的膜厚越靠近外侧越薄。
在上述形态中,半导体元件侧方的第一绝缘树脂层的硬度,比半导体元件另一侧的主表面上的第一绝缘树脂层的硬度硬。
另外,在上述形态中,电极可以是与配线层构成一体的突起电极。或者,电极也可以是通孔电极。
本发明的另一形态是便携式设备。该便携式设备安装有上述任一形态的半导体模块。
根据本发明,在CSP型半导体模块的制造方法中可以提高半导体模块的生产效率。
附图说明
图1是表示实施方式1的半导体模块的结构的示意剖面图。
图2(A)~(C)是表示半导体元件的单个化方法的工序剖面图。
图3(A)~(C)是表示电极的形成方法的工序剖面图。
图4(A)~(E)是表示配线层的形成方法、电极和元件电极的连接方法的工序剖面图。
图5(A)~(F)是表示实施方式2的配线层的形成方法、电极和元件电极的连接方法的工序剖面图。
图6(A)~(C)是表示实施方式3的半导体元件的单个化方法的工序剖面图。
图7(A)~(E)是表示电极的形成方法的工序剖面图。
图8(A)~(E)是表示配线层的形成方法、电极和元件电极的连接方法的工序剖面图。
图9(A)、(B)是表示配线层的形成方法、电极和元件电极的连接方法的工序剖面图。
图10(A)~(E)是表示实施方式4的配线层的形成方法、电极和元件电极的连接方法的工序剖面图。
图11(A)~(D)是表示实施方式4的配线层的形成方法、电极和元件电极的连接方法的工序剖面图。
图12是表示实施方式5的便携式电话的结构的图。
图13是便携式电话的局部剖面图。
附图标记说明
1半导体晶片、2划线、4半导体模块的形成区域、10半导体元件、12元件电极、14元件保护层、20第一绝缘树脂层、30配线层、32电极、40第二绝缘树脂层、50保护层、52绝缘层、60外部连接电极、82铜箔、80第三绝缘树脂层、100半导体模块。
具体实施方式
以下,参照附图对本发明的优选实施方式进行说明。对于各附图中所示的同一或同等的结构要素、部件、处理上标注同一附图标记,适当省略重复的说明。另外,实施方式并不限定发明而仅是例示,实施方式所记述的所有特征或其组合并不限定本发明的本质。
(实施方式1)
图1是表示实施方式1的半导体模块100的结构的示意剖面图。
半导体模块100的结构主要具有半导体元件10、第一绝缘树脂层20、配线层30、第二绝缘树脂层40、保护层50、绝缘层52、外部连接电极60。
半导体元件10在一侧的主表面S11具有元件电极12。而且,在半导体元件10的主表面S11侧层叠有元件保护层14,该元件保护层14设置有开口以使元件电极12露出。作为半导体元件10的具体例,例举集成电路(IC)、大规模集成电路(LSI)等半导体芯片。作为元件保护层14的具体例,例举聚酰亚胺层。而且,元件电极12例如使用铝(Al)。
在半导体元件10一侧的主表面S11侧,在半导体元件10和后述的配线层30之间设置有第二绝缘树脂层40。第二绝缘树脂层40由绝缘性树脂构成,例如由加压时引起塑性流动的材料形成。作为加压时引起塑性流动的材料,例举环氧类热固性树脂。第二绝缘树脂层40所采用的环氧类热固性树脂可以是例如在温度160℃、压力8MPa的条件下具有黏度为1kPa·s的特性的材料。而且,这种环氧类热固性树脂例如在温度160℃的条件下,当施加5~15MPa压力时,与未加压的情况相比,树脂的黏度降低到约1/8。与此相对,热固化前的B阶段的环氧树脂在玻璃转移温度Tg以下的条件下,与未对树脂加压的情况相同程度地没有黏性,即使加压也不会产生黏性。
在第二绝缘树脂层40的与半导体元件10相反的一侧的主表面上配置有配线层30。配线层30由导电材料形成,优选由轧制金属形成,更优选由轧制铜形成。或者也可以由电解铜等形成。在配线层30的第二绝缘树脂层40侧,以与配线层30电连接的状态突出设置有与元件电极12分别相对的电极32。配线层30和电极32优选一体成型。由此,能够防止因热应力而导致在配线层30和电极32之间的界面产生龟裂(裂纹)等,而且,与配线层30和电极32分体形成时的情况相比两者的连接更可靠。并且,由于能够在将电极32与元件电极12压接的同时将元件电极12与配线层30电连接,因此,具有不会增大工序数的效果。
在配线层30的与电极32相反的一侧的端部区域,在与形成有电极32的一侧相反的一侧的表面,形成有兼作配置后述的外部连接电极60的配线的接合区域。在本实施方式中,电极32为与配线层30构成一体的突起电极,但电极32的结构并不特别限定于此,例如也可以是形成于通孔内的通孔电极,该通孔设置在配线层30及第二绝缘树脂层40的与元件电极12对应的区域。
在配线层30的与第二绝缘树脂层40相反的一侧的主表面,设置有用于防止配线层30氧化等的保护层50。作为保护层50,例举抗焊剂层等。在与配线层30的接合区域对应的保护层50的规定区域形成有开口部50a,通过开口部50a,配线层30的接合区域露出。在开口部50a内形成有焊料突起等外部连接电极60,外部连接电极60与配线层30电连接。在形成外部连接电极60的位置即开口部50a的形成区域例如是再配线围绕的前端的端部区域。
在半导体元件10另一侧的主表面S12侧设置有第一绝缘树脂层20。第一绝缘树脂层20由绝缘性树脂形成,例如由具有规定的伸展性的材料如环氧类热固性树脂形成。第一绝缘树脂层20在半导体元件10的侧方区域B(图中B的区域)的硬度,比在半导体元件10其他侧的主表面S12上方区域A(图中A区域)的硬度硬。即,第一绝缘树脂层20在俯视时与半导体元件10不重叠的区域的硬度,比与半导体元件10重叠的区域的硬度硬。例如,半导体元件10的上方区域A中的第一绝缘树脂层20的压痕硬度约为12N/mm2,与此相对,半导体元件10的侧方区域B的第一绝缘树脂层20的压痕硬度约为40N/mm2。而且,第一绝缘树脂层20的膜厚在半导体元件10的侧方形成为越靠近半导体模块100的外侧越薄。
在第一绝缘树脂层20的与半导体元件10相反的一侧的主表面上,为了防止半导体模块100等产生翘曲,设置有由与保护层50相同的材料构成的绝缘层52。
本实施方式的半导体模块100构成为,第二绝缘树脂层40设置于配线层30和半导体元件10之间,配线层30压接于第二绝缘树脂层40一侧的主表面,半导体元件10压接于另一侧的主表面。而且,电极32贯通第二绝缘树脂层40,并与设置于半导体元件10的元件电极12电连接。由于第二绝缘树脂层40由通过加压引起塑性流动的材料构成,因此,在配线层30、第二绝缘树脂层40及半导体元件10以该顺序构成一体的状态下,可以抑制在电极32和元件电极12之间存在第二绝缘树脂层40的剩余膜,谋求提高连接可靠性。而且,在配线层30、第二绝缘树脂层40及半导体元件10以该顺序构成一体的状态下,第一绝缘树脂层20和第二绝缘树脂层40在半导体元件10的侧方相接。另外,半导体元件10的侧面被第一绝缘树脂层20和第二绝缘树脂层40覆盖。即,第一绝缘树脂层20和第二绝缘树脂层40之间的界面与半导体元件10的侧面相接。
如前所述,第一绝缘树脂层20在半导体元件10的侧方区域B,越靠近半导体模块100的外侧,其膜厚越薄。因此,第一绝缘树脂层20和第二绝缘树脂层40的接触面积增大,两者的密接性提高。而且,由于第一绝缘树脂层20在半导体元件10的侧方区域B硬,因此,通过第一绝缘树脂层20的锚固效应,半导体元件10更可靠地被固定。因此,元件电极12和电极32的连接可靠性提高。
(半导体模块的制造方法)
图2(A)~(C)是表示半导体元件10的单个化方法的工序剖面图。在各图中,(i)是平面图、(ii)是沿着(i)的A-A线的局部剖面图。需要说明的是,在各图的(i)中省略了(ii)中所示的元件电极12。
首先,图2(A)所示,准备形成有多个半导体元件10且作为配置成矩阵状的半导体基板的半导体晶片1,其中该半导体元件10在一侧的主表面S11设置有元件电极12。具体而言,例如在P型硅基板等半导体晶片1的表面,通过公知的技术形成有规定的集成电路等的半导体元件10,并在其周边部或上部形成有元件电极12。另外,在除了该元件电极12之外的半导体元件10表面上的区域,形成有用于保护半导体元件10的元件保护层14。各半导体元件10由未图示的多个划线被划分。
将准备的半导体晶片1粘接在具有伸展性的第一绝缘树脂层20上。在第一绝缘树脂层20的载置半导体晶片1侧的主表面上涂敷有粘接剂,利用粘接剂的粘接力,半导体晶片1粘接在第一绝缘树脂层20上。在本实施方式中,作为第一绝缘树脂层20,采用具有伸缩性的材料如环氧类热固性树脂。第一绝缘树脂层20的膜厚例如约为100μm。
接着,如图2(B)所示,切割半导体晶片1而单个化成多个半导体元件10。在半导体晶片1的切割过程中,使用以往公知的切割装置,沿着划分多个半导体元件10的划线将半导体晶片1切断。半导体元件10例如为约5mm见方的俯视时的大致四边形形状。
接着,如图2(C)所示,将第一绝缘树脂层20朝其外周方向以各向相同的方式拉伸,以扩大各半导体元件10的间隔。拉伸第一绝缘树脂层20的量为,例如使各半导体元件10之间的间隔成为各半导体模块100的形成区域4中的半导体元件10的侧方区域B的两倍与后述半导体模块100被单个化时切断的划线2的宽度之和的量。具体而言,例如约为2~5mm左右。第一绝缘树脂层20向外周方向的拉伸例如可以使用以往公知的扩展装置朝外周方向拉伸,或者通过将第一绝缘树脂层20推到所谓的胀圈(エキスパンダリング)而进行拉伸。
图3(A)~(C)是表示电极32的形成方法的工序剖面图。在本实施方式中,以电极32为突起电极的情况为例进行说明。
首先,如图3(A)所示,准备厚度至少比电极32的高度与配线层30的厚度之和大的作为金属板的铜板33。
接着,如图3(B)所示,通过光刻法,与电极32的图案相对应而选择性地形成抗蚀剂71。具体而言,使用层压装置,在铜板33上贴附规定膜厚的抗蚀剂膜,使用具有电极32的图案的光掩模进行曝光后进行显影,从而在铜板33上选择性地形成抗蚀剂71。为了提高与抗蚀剂的密接性,优选根据需要在层压抗蚀剂膜之前对铜板33的表面实施研磨、清洗等前处理。
接着,如图3(C)所示,将抗蚀剂71作为掩模,在铜板33上形成规定图案的电极32。具体而言,以抗蚀剂71为掩模对铜板33进行蚀刻,从而形成具有规定图案的电极32。在形成电极32之后,使用剥离剂剥离抗蚀剂71。电极32的位置与拉伸第一绝缘树脂层20而各半导体元件10的间隔处于扩大了的状态的第一绝缘树脂层20上的各半导体元件10的元件电极12的位置对应。
通过以上说明的工序,在铜板33上形成电极32。本实施方式的电极32的基底部直径、顶部直径、高度例如分别为大约φ40μm、大约φ30μm、大约20μm。
图4(A)~(E)是表示配线层30的形成方法、电极32和元件电极12的连接方法的工序剖面图。
首先,如图4(A)所示,以使电极32朝向第二绝缘树脂层40侧的方式将铜板33配置于第二绝缘树脂层40一侧的主表面侧。接着,将在第一绝缘树脂层20上扩大间隔的状态的多个半导体元件10配置于第二绝缘树脂层40另一侧的主表面侧。第二绝缘树脂层40的厚度为电极32的高度以上的厚度,例如约为20μm。接着,使用加压装置隔着第二绝缘树脂层40将铜板33与半导体元件10压接。加压加工时的压力和温度分别约为5MPa和200℃。
通过加压加工,第二绝缘树脂层40引起塑性流动,电极32贯通第二绝缘树脂层40。接着,如图4(B)所示,铜板33、第二绝缘树脂层40、半导体元件10及第一绝缘树脂层20构成一体,电极32和元件电极12压接,从而电极32与元件电极12被电连接。由于电极32的形状为其侧面形状随着靠近前端而直径逐渐变细的形状,因此,电极32顺畅地贯通第二绝缘树脂层40。
接着,通过光刻法,在与第二绝缘树脂层40相反的一侧的铜板33的主表面上,与配线层30的图案相应对而选择性地形成未图示的抗蚀剂。接着,将该抗蚀剂作为掩模对铜板33的主表面进行蚀刻,如图4(C)所示,在铜板33上形成与各半导体元件10对应的规定图案的配线层30。之后,将抗蚀剂剥离。本实施方式中的配线层30的厚度例如约为20μm。
接着,如图4(D)所示,通过光刻法,在与第二绝缘树脂层40相反的一侧的配线层30的主表面上形成保护层50,该保护层50在与外部连接电极60的形成位置对应的区域具有开口部50a。接着,在开口部50a内形成外部连接电极60。而且,在与半导体元件10相反的一侧的第一绝缘树脂层20的主表面上形成绝缘层52。
接着,如图4(E)所示,沿划线2进行切割,实现多个半导体模块100的单个化。
通过以上说明的制造工序,形成半导体模块100。
对于根据以上说明的结构所带来的作用效果总结如下:在本实施方式的半导体模块100的制造方法中,切割半导体晶片1后,对支承半导体晶片1的第一绝缘树脂层20进行拉伸,在该状态下与铜板33的贴合。因此,可以省去如下工序:将通过切割被单个化的各半导体元件10一个一个地剥离,仅以规定间隔进行再配置的工序,因此,半导体模块100的制造时间缩短。因此,半导体模块的生产效率提高,进而可以降低半导体模块的制造成本。
另外,由于拉伸第一绝缘树脂层20以扩大各半导体元件10的间隔,因此,可以使各半导体元件10中的外部连接电极60的设置面积增大。因此,可以增加外部连接电极60的形成数,可以应对半导体元件10的多管脚化。
另外,本实施方式的半导体模块100构成为,第一绝缘树脂层20在半导体元件10的侧方区域B越靠近半导体模块100的外侧,其膜厚越薄。因此,第一绝缘树脂层20和第二绝缘树脂层40的接触面积增大,两者的密接性提高。由此,可以抑制第一绝缘树脂层20和第二绝缘树脂层40之间剥离,从而提高电极32和元件电极12的连接可靠性。另外,由于第一绝缘树脂层20的半导体元件10的侧方区域B硬,因此,利用第一绝缘树脂层20的锚固效应,半导体元件10更可靠地被固定。因此,元件电极12和电极32的连接可靠性提高。
(实施方式2)
在上述实施方式1中,在作为电极32形成有突起电极的铜板33和半导体元件10之间夹持第二绝缘树脂层40,并通过加压成形来形成半导体模块100,但也可以如下形成半导体模块100。以下,对本实施方式进行说明。对于与实施方式1相同的结构,标注同一附图标记,适当省略其说明。
图5(A)~(F)是表示实施方式2的配线层30的形成方法、电极32和元件电极12的连接方法的工序剖面图。
首先,如图5(A)所示,隔着第二绝缘树脂层40压接作为金属板的铜板35和在第一绝缘树脂层20上扩大间隔的状态的多个半导体元件10。
接着,如图5(B)所示,例如通过光刻法,与电极32的图案相对应而选择性地除去铜板35的一部分。接着,向铜板35的除去部位例如照射激光,选择性地除去第二绝缘树脂层40的一部分直至元件电极12露出,从而形成多个通孔37。在此,激光照射可以使用例如二氧化碳气体激光。
接着,如图5(C)所示,通过无电解镀覆法和电解镀覆法,或者无电解镀覆法等,以与元件电极12电连接的方式镀覆例如铜(Cu)等金属以形成导电层36。导电层36中形成于通孔37内的区域构成电极32。该图中未图示铜板35和被镀覆的金属之间的界面。由此,导电层36和元件电极12经由电极32导通。
接着,通过光刻法,在导电层36的主表面上,与配线层30的图案相对应而选择性地形成未图示的抗蚀剂,并以该抗蚀剂为掩模选择性地除去导电层36的主表面,如图5(D)所示,形成与各半导体元件10对应的规定图案的配线层30。
接着,如图5(E)所示,通过光刻法,在配线层30的主表面上形成具有开口部50a的保护层50,并在开口部50a内形成外部连接电极60。而且,在与半导体元件10相反的一侧的第一绝缘树脂层20的主表面上形成绝缘层52。
接着,如图5(F)所示,沿划线2进行切割,从而实现多个半导体模块100的单个化。
通过以上说明的制造工序,形成半导体模块100。
以上,如实施方式2的半导体模块100那样,也可以将电极32设为通孔电极,即便在这样的情况下,也能够得到与实施方式1相同的效果。另外,在本实施方式中,由于未将电极32和元件电极12压接,因此,可以减小对元件电极12及半导体元件10带来损伤的可能性。
(实施方式3)
以下,对本实施方式的半导体模块100的制造方法进行说明。对于与实施方式1相同的结构,标注同一附图标记,适当省略其说明。
图6(A)~(C)是表示实施方式3的半导体元件10的单个化方法的工序剖面图。在各图中,(i)是平面图、(ii)是沿(i)的A-A线的局部剖面图。在各图的(i)中省略了(ii)中所示的元件电极12。
首先,如图6(A)所示,准备形成有多个半导体元件10且作为配置成矩阵状的半导体基板的半导体晶片1,其中该半导体元件10在一侧的主表面S11设置有元件电极12,并将已准备的半导体晶片1粘接在具有伸展性的第一绝缘树脂层20上。在本实施方式中,如后所述,由于第一绝缘树脂层20未残留于最终形成的半导体模块100,因此,与实施方式1及2的情况相比,选择第一绝缘树脂层20的材质的自由度高。
接着,如图6(B)所示,切割半导体晶片1,实现多个半导体元件10的单个化。
接着,如图6(C)所示,将第一绝缘树脂层20朝其外周方向以各向相同的方式拉伸,直至各半导体元件10之间的间隔达到各半导体模块100的形成区域4中的半导体元件10的侧方区域B的两倍与划线2的宽度之和。
图7(A)~(E)是表示电极32的形成方法的工序剖面图。在本实施方式中,以电极32为突起电极的情况为例进行说明。
首先,如图7(A)所示,准备厚度至少比电极32的高度与配线层30的厚度之和大的作为金属板的铜板33。
接着,如图7(B)所示,通过光刻法,与电极32的图案相对应而选择性地形成抗蚀剂71。
接着,如图7(C)所示,以抗蚀剂71为掩模,在铜板33上形成作为规定图案的电极32的突起电极。在形成电极32后,使用剥离剂剥离抗蚀剂71。电极32的位置与拉伸第一绝缘树脂层20而各半导体元件10的间隔扩大了的状态的第一绝缘树脂层20的各半导体元件10的元件电极12的位置对应。
接着,如图7(D)所示,在铜板33的形成有电极32的一侧的主表面上,以覆盖电极32的方式层叠第二绝缘树脂层40。
接着,如图7(E)所示,对第二绝缘树脂层40的主表面实施基于例如O2等离子体等的灰化处理,除去规定量的第二绝缘树脂层40以露出电极32的顶部面,并使电极32贯通第二绝缘树脂层40。
通过以上说明的工序,形成电极32,并且在形成有电极32的一侧的主表面上形成层叠有第二绝缘树脂层40的铜板33。
图8(A)~(E)及图9(A)、(B)是表示配线层30的形成方法、电极32和元件电极12的连接方法的工序剖面图。
首先,如图8(A)所示,将层叠有第二绝缘树脂层40的铜板33以使电极32朝向半导体元件10侧的方式配置,以使该铜板33与在第一绝缘树脂层20上扩大间隔的状态的多个半导体元件10贴合。由此,电极32和元件电极12电连接。
接着,如图8(B)所示,自半导体元件10剥离第一绝缘树脂层20,以除去第一绝缘树脂层20。
接着,如图8(C)所示,将第三绝缘树脂层80另一侧的主表面与半导体元件10相配合并使用加压装置将与铜板33构成一体的半导体元件10和在一侧的主表面具有作为金属层的铜箔82的第三绝缘树脂层80压接。第三绝缘树脂层80例如是与第二绝缘树脂层40相同的绝缘性树脂,例如环氧类热固性树脂。因此,因加压加工而使第三绝缘树脂层80产生塑性流动,半导体元件10埋没于第三绝缘树脂层80内,第二绝缘树脂层40和第三绝缘树脂层80被压接。
接着,如图8(D)所示,铜板33、第二绝缘树脂层40、半导体元件10及第三绝缘树脂层80构成一体。在此,根据加压加工时的温度变化,有可能在铜板33产生翘曲。但是,在铜板33、第二绝缘树脂层40、半导体元件10及第三绝缘树脂层80构成一体的状态下,在与铜板33相反的一侧的主表面上设置有铜箔82,铜箔82也产生与铜板33的翘曲相对的翘曲。因此,可以抑制铜板33产生翘曲。
接着,通过光刻法,在铜板33的主表面上选择性地形成规定图案的抗蚀剂,并以该抗蚀剂为掩模对铜板33的主表面进行蚀刻,如图8(E)所示,在铜板33上形成与各半导体元件10对应的规定图案的配线层30。而且,在形成配线层30时,与配线层30的图案相对应而选择性地除去铜箔82。铜箔82的构图根据配线层30的图案进行,由此,可以抑制因半导体模块100的使用环境下的温度变化而导致配线层30有可能产生翘曲。另外,也可以将铜箔82全部除去。
接着,如图9(A)所示,通过光刻法,在配线层30的主表面上形成具有开口部50a的保护层50,并在开口部50a内形成外部连接电极60。而且,在与半导体元件10相反的一侧的第三绝缘树脂层80的主表面上形成绝缘层52。
接着,如图9(B)所示,沿划线2进行切割,实现多个半导体模块100的单个化。
通过以上说明的制造工序,形成半导体模块100。
以上,根据实施方式3,除实施方式1的上述效果之外,还能得到如下效果:在本实施方式中,第一绝缘树脂层20不会残留在最终形成的半导体模块100上。因此,选择第一绝缘树脂层20的材质的自由度高,可以谋求降低制造成本。另外,由于使用设置有铜箔82的第三绝缘树脂层80将半导体元件10封入绝缘树脂中,因此,可以防止因在制造过程中引起的温度变化而铜板33产生翘曲。
而且,与配线层30的图案相对应而选择性地除去铜箔82,并且,使其残留于半导体模块100中,从而可以防止因使用环境下的温度变化而导致配线层30产生翘曲。因此,电极32和元件电极12的连接可靠性提高,半导体模块100的可靠性提高。
而且,在本实施方式中,由于以使电极32自第二绝缘树脂层40露出的状态使铜板33和半导体元件10贴合,因此,可以准确地进行铜板33和半导体元件10贴合时的定位。因此,电极32和元件电极12的连接可靠性进一步提高。
(实施方式4)
在上述实施方式3中,将层叠有第二绝缘树脂层40并且作为电极32形成有突起电极的铜板33与半导体元件10贴合来形成半导体模块100,但也可以如下形成半导体模块100。以下,对本实施方式进行说明。对于与实施方式1及3相同的结构,标注同一附图标记,适当省略其说明。
图10(A)~(E)及图11(A)~(D)是表示实施方式4的配线层30的形成方法、电极32和元件电极12的连接方法的工序剖面图。
首先,如图10(A)所示,隔着第二绝缘树脂层40,将作为金属板的铜板35和在第一绝缘树脂层20上扩大间隔的状态的多个半导体元件10贴合。
接着,如图10(B)所示,自半导体元件10剥离第一绝缘树脂层20,以除去第一绝缘树脂层20。
接着,如图10(C)所示,将第三绝缘树脂层80的另一侧主表面和半导体元件10相配合并使用加压装置将与铜板35构成一体的半导体元件10和在一侧的主表面具有作为金属层的铜箔82的第三绝缘树脂层80压接。由此,如图10(D)所示,铜板35、第二绝缘树脂层40、半导体元件10及第三绝缘树脂层80构成一体。
接着,如图10(E)所示,例如通过光刻法,与电极32的图案相对应而选择性地除去铜板35的一部分。接着向铜板35的除去部位例如照射激光,选择性地除去第二绝缘树脂层40的一部分直至元件电极12露出,从而形成多个通孔37。
接着,如图11(A)所示,通过无电解镀覆法和电解镀覆法,或者无电解镀覆法等,以与元件电极12电连接的方式镀覆例如铜(Cu)等金属以形成导电层36。导电层36中形成于通孔37内的区域构成电极32。在该同图中未图示铜板35和被镀覆的金属之间的界面。由此,经由电极32使导电层36和元件电极12导通。
接着,通过光刻法,在导电层36的主表面上,与配线层30的图案相对应而选择性地形成抗蚀剂,并以该抗蚀剂为掩模选择性地除去导电层36的主表面,从而形成如图11(B)所示的配线层30。接着,通过光刻法,与配线层30的图案相对应而选择性地除去铜箔82。
接着,如图11(C)所示,通过光刻法,在配线层30的主表面上形成具有开口部50a的保护层50,并在开口部50a内形成外部连接电极60。而且,在与半导体元件10相反的一侧的第一绝缘树脂层20的主表面上形成绝缘层52。
接着,如图11(D)所示,沿划线2进行切割,实现多个半导体模块100的单个化。
通过以上说明的制造工序,形成半导体模块100。
以上,如实施方式4的半导体模块100那样,可以将电极32设为通孔电极,即便在这种情况下,由于电极32自第二绝缘树脂层40露出,因此,除具有提高与半导体元件10的定位精度的效果之外,还能够得到与实施方式3相同的效果。而且,在本实施方式中,由于电极32和元件电极12未压接,因此,可以减小对元件电极12及半导体元件10带来损伤的可能性。
(实施方式5)
接着,对具有本发明的半导体模块的便携式设备进行说明。虽然作为便携式设备示出安装于便携式电话的例子,但是例如也可以是个人用便携式信息终端(PDA)、数字视频照相机(DVC)以及数字静物照相机(DSC)之类的电子设备。
图12是表示具有本发明的实施方式的半导体模块100的便携式电话结构的图。便携式电话111构成为第一框体112和第二框体114由可动部120连结。第一框体112和第二框体114能够以可动部120为轴进行转动。在第一框体112设有显示文字、图像等信息的显示部118和听筒部124。在第二框体114设有操作用按钮等操作部122和话筒部126。而且,本发明的各实施方式的半导体模块100安装在该便携式电话111的内部。
图13是图12所示的便携式电话的局部剖面图(第一框体112的剖面图)。本发明各实施方式的半导体模块100隔着外部连接电极60安装于印刷基板128,并经由该印刷基板128与显示部118等电连接。而且,在半导体模块100的背面侧(与外部连接电极60相反的一侧的面)设置有金属基板等散热基板116,例如不使自半导体模块100产生的热量集中于第一框体112内部,可以有效地向第一框体112的外部散热。
根据本发明的实施方式的半导体模块100,半导体模块100的生产效率提高、制造成本降低,因此,对于安装有该半导体模块100的本实施方式的便携式设备而言,其制造成本降低。而且,半导体模块100向印刷线路基板安装的安装可靠性提高。因此,对于安装有该半导体模块100的本实施方式的便携式设备而言,其可靠性提高。
本发明并不限定于上述各实施方式,基于本领域技术人员的知识,可以进行各种设计变更等变形,进行这种变形后的实施方式也包含在本发明的范围内。
例如,在上述实施方式中,元件安装用基板的配线层为单层,但并不限定于此,配线层还可以是多层结构。
Claims (11)
1.一种半导体模块的制造方法,其特征在于,具有如下工序:
将形成有多个半导体元件的半导体基板粘接在具有伸展性的第一绝缘树脂层上的工序,其中所述半导体元件在一侧的主表面设置有元件电极;
将所述半导体基板切割而单个化成多个所述半导体元件的工序;
拉伸所述第一绝缘树脂层以扩大多个所述半导体元件的间隔的工序;
隔着第二绝缘树脂层将设置有突起电极的金属板和在所述第一绝缘树脂层上处于扩大间隔的状态的多个所述半导体元件压接,使所述突起电极贯通所述第二绝缘树脂层,从而将所述突起电极和所述元件电极电连接的压接工序,其中,所述突起电极与设置于各半导体元件的所述元件电极相对;
选择性地除去所述金属板以形成与各半导体元件对应的配线层,并形成通过所述第一绝缘树脂层和所述第二绝缘树脂层连结的多个半导体模块的工序;
将所述第一绝缘树脂层及所述第二绝缘树脂层切断而使所述半导体模块单个化的工序。
2.一种半导体模块的制造方法,其特征在于,具有如下工序:
将形成有多个半导体元件的半导体基板粘接在具有伸展性的第一绝缘树脂层上的工序,其中所述半导体元件在一侧的主表面设置有元件电极;
将所述半导体基板切割而单个化成多个所述半导体元件的工序;
拉伸所述第一绝缘树脂层以扩大多个所述半导体元件的间隔的工序;
隔着第二绝缘树脂层将在所述第一绝缘树脂层上处于扩大间隔的状态的多个所述半导体元件与金属板压接的工序;
选择性地除去所述金属板和所述第二绝缘树脂层以形成多个通孔,并在所述通孔内形成通孔电极以使其与所述元件电极电连接的工序;
选择性地除去所述金属板以形成与各半导体元件对应的配线层,并形成通过所述第一绝缘树脂层和所述第二绝缘树脂层连结的多个半导体模块的工序;
将所述第一绝缘树脂层及所述第二绝缘树脂层切断而使所述半导体模块单个化的工序。
3.一种半导体模块的制造方法,其特征在于,具有如下工序:
将形成有多个半导体元件的半导体基板粘接在具有伸展性的第一绝缘树脂层上的工序,其中所述半导体元件在一侧的主表面设置有元件电极;
将所述半导体基板切割而单个化成多个所述半导体元件的工序;
拉伸所述第一绝缘树脂层以扩大多个所述半导体元件的间隔的工序;
在设置有与设置于各半导体元件的所述元件电极相对的突起电极的金属板上层叠第二绝缘树脂层,使所述突起电极贯通所述第二绝缘树脂层,将在所述第一绝缘树脂层上处于扩大间隔的状态的多个所述半导体元件与所述金属板贴合,使所述突起电极和所述元件电极电连接的工序;
除去所述第一绝缘树脂层,并将第三绝缘树脂层的另一侧的主表面与所述半导体元件的另一侧的主表面相配合而使在一侧的主表面具有金属层的所述第三绝缘树脂层与所述半导体元件压接的工序;
选择性地除去所述金属板以形成与各半导体元件对应的配线层,并形成通过所述第二绝缘树脂层和所述第三绝缘树脂层连结的多个半导体模块的工序;
将所述第二绝缘树脂层及所述第三绝缘树脂层切断而使所述半导体模块单个化的工序。
4.一种半导体模块的制造方法,其特征在于,具有如下工序:
将形成有多个半导体元件的半导体基板粘接在具有伸展性的第一绝缘树脂层上的工序,其中所述半导体元件在一侧的主表面设置有元件电极;
将所述半导体基板切割而单个化成多个所述半导体元件的工序;
拉伸所述第一绝缘树脂层以扩大多个所述半导体元件的间隔的工序;
隔着第二绝缘树脂层将在所述第一绝缘树脂层上处于扩大间隔的状态的多个所述半导体元件与金属板贴合的工序;
除去所述第一绝缘树脂层,并将第三绝缘树脂层的另一侧的主表面与所述半导体元件的另一侧的主表面相配合而使在一侧的主表面具有金属层的所述第三绝缘树脂层与所述半导体元件压接的工序;
选择性地除去所述金属板和所述第二绝缘树脂层以形成多个通孔,并在所述通孔内形成通孔电极以使其与所述元件电极电连接的工序;
选择性地除去所述金属板以形成与各半导体元件对应的配线层,并形成通过所述第二绝缘树脂层和所述第三绝缘树脂层连结的多个半导体模块的工序;
将所述第二绝缘树脂层及所述第三绝缘树脂层切断而使所述半导体模块单个化的工序。
5.如权利要求3或4所述的半导体模块的制造方法,其特征在于,
在形成所述配线层时,与所述配线层的形成区域相对应而选择性地除去所述金属层。
6.如权利要求3或4所述的半导体模块的制造方法,其特征在于,
在形成所述配线层时,将所述金属层全部除去。
7.一种半导体模块,其特征在于,具有:
在一侧的主表面设置有元件电极的半导体元件、
设置于所述半导体元件的另一侧主表面的第一绝缘树脂层、
设置有与所述元件电极相对的电极的配线层、
设置于所述配线层和所述半导体元件之间的第二绝缘树脂层,
所述电极贯通所述第二绝缘树脂层,以使所述电极与所述元件电极电连接,
所述第一绝缘树脂层和所述第二绝缘树脂层之间的界面与所述半导体元件的侧面相接,并且,所述半导体元件的侧面被所述第一绝缘树脂层和所述第二绝缘树脂层覆盖,
所述半导体元件侧方的所述第一绝缘树脂层的膜厚越靠近外侧越薄。
8.如权利要求7所述的半导体模块,其特征在于,
所述半导体元件侧方的所述第一绝缘树脂层的硬度,比所述半导体元件的其他主表面上的所述第一绝缘树脂层的硬度硬。
9.如权利要求7或8所述的半导体模块,其特征在于,
所述电极是与所述配线层构成一体的突起电极。
10.如权利要求7或8所述的半导体模块,其特征在于,
所述电极是通孔电极。
11.一种便携式设备,其特征在于,
安装有权利要求7~10中任一项所述的半导体模块。
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Application Number | Priority Date | Filing Date | Title |
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JP091644/08 | 2008-03-31 | ||
JP2008091644A JP4753960B2 (ja) | 2008-03-31 | 2008-03-31 | 半導体モジュール、半導体モジュールの製造方法 |
PCT/JP2009/055307 WO2009122911A1 (ja) | 2008-03-31 | 2009-03-18 | 半導体モジュール、半導体モジュールの製造方法、ならびに携帯機器 |
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JP (1) | JP4753960B2 (zh) |
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JP2011077108A (ja) * | 2009-09-29 | 2011-04-14 | Elpida Memory Inc | 半導体装置 |
JP5496692B2 (ja) | 2010-01-22 | 2014-05-21 | 三洋電機株式会社 | 半導体モジュールの製造方法 |
KR101678052B1 (ko) * | 2010-02-25 | 2016-11-22 | 삼성전자 주식회사 | 단층 배선 패턴을 포함한 인쇄회로기판(pcb), pcb를 포함한 반도체 패키지, 반도체 패키지를 포함한 전기전자장치, pcb제조방법, 및 반도체 패키지 제조방법 |
US9748154B1 (en) * | 2010-11-04 | 2017-08-29 | Amkor Technology, Inc. | Wafer level fan out semiconductor device and manufacturing method thereof |
JP5819999B2 (ja) * | 2014-02-05 | 2015-11-24 | ラピスセミコンダクタ株式会社 | 半導体装置およびその半導体装置の製造方法 |
CN105097758B (zh) * | 2014-05-05 | 2018-10-26 | 日月光半导体制造股份有限公司 | 衬底、其半导体封装及其制造方法 |
JPWO2023042450A1 (zh) * | 2021-09-14 | 2023-03-23 |
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JPH08236586A (ja) * | 1994-12-29 | 1996-09-13 | Nitto Denko Corp | 半導体装置及びその製造方法 |
EP1335422B1 (en) * | 1995-03-24 | 2013-01-16 | Shinko Electric Industries Co., Ltd. | Process for making a chip sized semiconductor device |
JPH08306828A (ja) * | 1995-05-11 | 1996-11-22 | Nitto Denko Corp | 半導体装置 |
US6181569B1 (en) * | 1999-06-07 | 2001-01-30 | Kishore K. Chakravorty | Low cost chip size package and method of fabricating the same |
JP2001176898A (ja) * | 1999-12-20 | 2001-06-29 | Mitsui High Tec Inc | 半導体パッケージの製造方法 |
JP2002083904A (ja) * | 2000-09-06 | 2002-03-22 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP3923368B2 (ja) * | 2002-05-22 | 2007-05-30 | シャープ株式会社 | 半導体素子の製造方法 |
US6998532B2 (en) * | 2002-12-24 | 2006-02-14 | Matsushita Electric Industrial Co., Ltd. | Electronic component-built-in module |
JP2004349361A (ja) | 2003-05-21 | 2004-12-09 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP4479209B2 (ja) * | 2003-10-10 | 2010-06-09 | パナソニック株式会社 | 電子回路装置およびその製造方法並びに電子回路装置の製造装置 |
WO2006093191A1 (ja) * | 2005-03-01 | 2006-09-08 | Nec Corporation | 半導体パッケージ及びその製造方法 |
JP4428337B2 (ja) * | 2005-12-02 | 2010-03-10 | ソニー株式会社 | 半導体装置の製造方法 |
JP4877626B2 (ja) * | 2006-02-16 | 2012-02-15 | 株式会社テラミクロス | 半導体装置の製造方法 |
JP2008053693A (ja) * | 2006-07-28 | 2008-03-06 | Sanyo Electric Co Ltd | 半導体モジュール、携帯機器、および半導体モジュールの製造方法 |
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CN102027591A (zh) | 2011-04-20 |
JP4753960B2 (ja) | 2011-08-24 |
US20110193222A1 (en) | 2011-08-11 |
US8476776B2 (en) | 2013-07-02 |
JP2009246174A (ja) | 2009-10-22 |
WO2009122911A1 (ja) | 2009-10-08 |
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