CN103329266A - 具有连接有源芯片的插板的堆叠微电子组件 - Google Patents
具有连接有源芯片的插板的堆叠微电子组件 Download PDFInfo
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Abstract
微电子组件(100)可包括第一微电子元件(102)、第二微电子元件(112)和插板(120),每个微电子元件都包含邻近正面(104、114)的有源半导体器件,插板(120)的材料具有小于10ppm/℃的热膨胀系数。每个微电子元件(102、112)都可都具有在自身正面(104、114)暴露的导电垫(106、116)。插板(120)可具有在插板的开口(222)内延伸的第二导电元件(118),且在插板的第一表面(227)及第二表面(229)暴露。第一表面(227)和第二表面(229)可分别面对第一微电子元件(102)和第二微电子元件(112)的正面(104、114)。每个微电子元件(102、112)还可都包括在从各微电子元件的背面(237、239)朝自身正面(104、114)延伸的开口(206、216)内延伸的第一导电元件(236、238)。至少一个第一导电元件(236、238)可穿过第一微电子元件(102)或第二微电子元件(112)中相应一个的导电垫(204、214)而延伸。
Description
相关申请的交叉引用
本申请为申请号为12/958866、申请日为2010年12月2日的美国专利申请的继续申请,其公开的内容以引用的方式并入本文。
背景技术
本发明涉及微电子器件的封装,尤其是半导体器件的封装。
微电子器件通常包括如硅或砷化镓等半导体材料的薄板,一般称为裸片或半导体芯片。半导体芯片一般设置为单独的预封装单元。在一些单元的设计中,半导体芯片安装至基板或芯片载体上,而基板或芯片载体再安装至如印刷电路板等的电路板上。
有源电路在半导体芯片的第一面(如正面)制备。为便于与有源电路的电连接,在芯片的同一面设置有结合垫。结合垫通常以规则阵列的形式设置,或者沿裸片的边缘,或者在裸片的中心,对于许多存储器件来说设置在裸片的中心。结合垫通常由如铜或铝等的导电金属制成,大约为0.5微米(μm)厚。结合垫可包括单层或多层的金属。结合垫的大小随器件类型而变化,但典型地,在一侧的尺寸为几十微米至几百微米。
贯通硅通路(TSV)用于提供半导体芯片的正面与背面之间的电连接,芯片的正面上设有结合垫,芯片的背面与正面相对。常规的TSV孔会使可用于容纳有源电路的第一表面部分缩减。这种第一表面上可用于有源电路的可利用空间的减少,会使生产每个半导体芯片所需的硅量增加,从而潜在地增加每个芯片的成本。
在芯片的任一几何布置中,尺寸是重要的考虑因素。随着便携式电子装置的快速发展,芯片的更紧凑几何布置的需求变得更为强烈。仅以示例的方式说明,通常称为“智能手机”的装置,集成了移动电话及强大的数据处理器、存储器、如全球定位系统接收器、数码相机等的辅助器件等的功能,以及局域网连接,并伴有高分辨率的显示及相关的图像处理芯片。这种装置可提供如完整的互联网连接、包括高清视频等的娱乐、导航、电子银行及更多的性能,都设置在袖珍式的装置内。复杂的便携装置要求把大量芯片包装至狭小的空间内。此外,一些芯片具有许多输入和输出接口,一般称为“I/O口”。这些I/O口必须与其他芯片的I/O口互连。这种互连应尽量短且应具有低的阻抗,以使信号传输延迟最小化。形成这些互连的元器件不应大幅度增加组件的尺寸。类似需求也出现在其他应用中,例如,数据服务器,如在互联网搜索引擎中使用的数据服务器。例如,在复杂芯片之间设置大量短且阻抗低的互连的结构,可增加搜索引擎的频带宽度(bandwidth),并降低其能耗。
尽管在半导体通路的形成和互连方面已取得进展,但为提升制作芯片正面与背面之间连接的处理过程,及这种过程生成的结构,仍可以做出进一步的改进。
发明内容
根据本发明的方面,微电子组件可包括第一微电子元件、第二微电子元件和插板,每个微电子元件都包含邻近其正面的有源半导体器件,插板的材料具有小于百万分之十每摄氏度的热膨胀系数。每个微电子元件都可具有远离自身正面的背面及在自身正面暴露的导电垫。插板可具有朝向相反的第一表面与第二表面、及在插板的开口内延伸的第二导电元件。第二导电元件可在插板的第一表面及第二表面暴露。
插板的第一表面可面对第一微电子元件的正面,插板的第二表面可面对第二微电子元件的正面。每个微电子元件还都可包括在开口内延伸的第一导电元件,开口从各微电子元件的背面朝各微电子元件的正面延伸。至少一个第一导电元件可穿过第一微电子元件或第二微电子元件中相应一个的导电垫而延伸。第一导电元件可与第二导电元件电耦合。
在特定实施例中,由第二导电元件穿过其延伸的开口可与穿过第一微电子元件及第二微电子元件而延伸的至少一个开口相交。在一个实施例中,由第二导电元件穿过其延伸的开口可与穿过第一微电子元件及第二微电子元件而延伸的每个开口都相交。在示例性的实施例中,由第二导电元件穿过其延伸的开口可与穿过第一导电元件和第二微电子元件而延伸的任一开口都不相交。在特定实施例中,插板可基本上由介电材料组成。在一个实施例中,插板可基本上由金属或半导体材料组成。插板内的开口可衬有绝缘体。
在示例性的实施例中,每个微电子元件的第一导电元件都可穿过相应导电垫而延伸。在特定实施例中,第二导电元件可包括在第一表面和第二表面暴露的第二导电垫。第一微电子元件和第二微电子元件的垫可为第一垫。第一垫可与第二垫并置。第一导电元件可与第一垫及第二垫的并置表面接触。在一个实施例中,插板内由第二导电元件穿过其延伸的开口,可具有相对于插板的第一表面及第二表面以直角延伸的内壁。在示例性的实施例中,插板内由第二导电元件穿过其延伸的开口可沿插板的第一表面与第二表面之间的方向逐渐变细。
在一个实施例中,第一微电子元件内的开口可沿从第一微电子元件的背面朝自身正面的方向逐渐变细。在特定实施例中,第一微电子元件内开口的内表面可相对于第一微电子元件的正面以直角延伸。在示例性的实施例中,第二导电元件可与插板内开口的内表面的轮廓一致。在一个实施例中,第二导电元件可与插板内开口的内表面的轮廓不一致。
在特定实施例中,插板内开口及第一微电子元件或第二微电子元件中至少一个内的开口可为逐渐变细的,彼此沿相反的方向变小。在示例性的实施例中,插板还可包括至少一个无源元器件,与第一微电子元件或第二微电子元件中至少一个电连接。在一个实施例中,根据本发明方面的系统可包括,上述的微电子组件及一个或多个与微电子组件电连接的其他电子元器件。在特定实施例中,系统还可包括壳体,所述微电子组件和所述其他电子元器件安装至所述壳体。
根据本发明另一方面,微电子组件的制造方法可包括:组装第一微电子组件与第二微电子组件及二者之间的插板的步骤,每个微电子元件都包含邻近自身正面的有源半导体器件,然后是形成在开口内延伸的第一导电元件的步骤,开口从各微电子元件的背面朝着自身正面延伸。每个微电子元件可具有远离自身正面的背面及在正面暴露的导电垫。
插板可基本上由半导体或无机介电材料中至少一种组成。插板可具有朝向相反的第一表面与第二表面,及穿过插板而延伸且在第一表面及第二表面暴露的第二导电元件。插板的第一表面可面对第一微电子元件的正面,而插板的第二表面可面对第二微电子元件的正面。至少一个第一导电元件可穿过至少一个微电子元件的相应导电垫而延伸。第一导电元件可与第二导电元件电耦合。微电子元件内开口的内表面可相对于每个微电子元件的相应正面沿第一方向和第二方向延伸,以限定明显的角度。
在示例性的实施例中,每个微电子元件的第一导电元件可穿过相应导电垫而延伸。在一个实施例中,第二导电元件可包括在第一表面和第二表面暴露的第二导电垫。每个微电子元件的第一导电垫可与第二垫中的一个并置。第一导电元件可与第一垫及第二垫的并置表面接触。在特定实施例中,插板内第二导电元件穿过其延伸的开口可具有相对于插板的第一表面和第二表面以直角延伸的内壁。
在一个实施例中,插板内第二导电元件穿过其延伸的开口可在插板的第一表面与第二表面之间的方向逐渐变细。在示例性的实施例中,第二导电元件可与插板内开口的内表面的轮廓一致。在特定实施例中,第二导电元件可与插板内开口的内表面的轮廓不一致。在一个实施例中,插板内开口和第二导电元件可沿相反的方向逐渐变细。
附图说明
图1是说明根据本发明实施例微电子组件放置为待与电路板附接时的截面图。
图1A是进一步详细说明根据本发明实施例微电子组件的局部截面图。
图2是说明根据本发明实施例微电子组件安装至电路板时的截面图。
图3是进一步说明根据本发明实施例微电子组件的平面图。
图4、图5、图6、图7、图8、图9、图10和图11是说明根据本发明实施例的变例的微电子组件制造方法的各阶段的局部截面图。
图12、图13和图14是说明根据图4、图5、图6、图7、图8、图9、图10和图11所示本发明实施例的变例的微电子组件制造方法的各阶段的局部截面图。
图15和图16是说明根据图12、图13和图14所示本发明实施例的变例的微电子组件制造方法的各阶段的局部截面图。
图17是说明根据图16所示本发明实施例的变例的微电子组件的局部截面图。
图18是说明根据图10所示本发明实施例的另一变例的微电子组件的局部截面图。
图19根据本发明一个实施例系统的示意图。
具体实施方式
图1示出了根据本发明一个实施例的微电子组件100。微电子封装包括第一微电子元件102和第二微电子元件112,每个都具有面对位于两微电子元件之间的插板120的承载触点的正面104、114。例如,每个微电子元件可都为集成在半导体芯片上的集成电路,半导体芯片可包括硅、硅合金或其他半导体材料,如III-V族半导体材料或II-VI族半导体材料。从作为放大图的图1A可以看出,芯片102具有正面104,也称为触点承载面,为芯片的主表面,芯片的第一区域105位于正面。第二芯片112可具有与芯片102相同的结构。第一区域105包括介电区域,介电区域典型地包括具有介电层的复数个布线层,介电层在布线层之间及围绕布线层而设置。在特定实施例中,介电区域可包括一层或多层具有低介电常数的介电材料层,即“低k”介电层。低k介电材料包括多孔二氧化硅、碳掺杂二氧化硅、聚合物电介质、多孔聚合物电介质、及其他。在多孔低k介电层中,介电层可具有大量孔隙,相对于相同材料的无孔层,孔隙降低介电材料的介电常数。介电材料通常具有远大于1.0的介电常数,但占据多孔材料内空隙的空气具有的介电常数约为1.0。以这种方式,一些介电材料可通过具有大量孔洞而使介电常数降低。
但是,一些低k介电材料,如聚合物介电材料和多孔介电材料,能承受的机械应力比常规介电材料小得多。特定类型的检测微电子元件的工作环境及方法,可存在处于低k介电材料能承受的应力限度或接近该限度的应力。通过使施加至微电子元件的应力移动至远离区域105内低k介电层的位置,本文描述的微电子组件对微电子元件的低k介电层提供了更好的保护。以这种方式,制造、操作及检测过程中施加至低k介电材料的应力大幅降低,因此保护了低k介电层。
层105还包括有源半导体器件(如晶体管、二极管或其他有源器件),通过布线层最终与正面的复数个导电垫106连接。当芯片为硅在绝缘体上(silicon-on-insulator,“SOT”)类型的芯片时,第一区域105还可包括置于有源半导体器件下方的隐埋介电层。第一区域105可使芯片的第二区域107与正面104分隔开。第一区域典型地具有0.1微米至5微米的厚度,且典型地不能减薄。第二区域107通常基本上由半导体材料(通常或为单晶或为多晶)组成,且典型地具有小于20微米的厚度,该厚度典型地由最初的半导体晶圆在处理过程中减薄的程度而确定。在一个实施例中,芯片可只有第一区域105而不存在第二区域107。因此,微电子元件102、112安装于其上的插板结构120,为微电子元件提供结构支撑,使微电子元件102、112的厚度可缩减至理想的程度。同样,每个微电子元件面对插板的介电区域105。
进一步如图1所示,例如利用粘接剂101,可使微电子元件与插板120结合在一起。其他可能的结合材料可包括玻璃,在特定实施例中,玻璃可掺杂,且可具有低于500℃的玻璃化转变温度。典型地,微电子元件112与另一微电子元件102基本上由相同的半导体材料组成。从图1可以进一步看出,微电子元件110可具有穿过微电子元件内开口而延伸的复数个导电通路元件,用于设置与导电垫106、116的电连接。
微电子元件102、112可通过穿过导电垫106、116及其间的插板102而延伸的导电元件118而电连接在一起。在一个示例中,导电元件118可包括,通过沉积与导电垫106、116暴露表面接触的金属而形成的金属特征。如下文进一步详述,形成导电元件可采用各种金属沉积步骤。
从图1可以进一步看出,导电元件118可与介电元件126的表面暴露的触点124,以与倒装芯片类似的方式导电结合,例如通过结合金属块128,如焊料、锡、铟或其组合。而介电元件可具有复数个端子130,用于使封装100进一步与电路板134的相应触点136电连接,例如通过导电块132,如从介电元件126突出的焊料球。图1示出的是与电路板134接合前的封装100。图2示出的微电子组件包括封装100及与其接合的电路板134。
散热器140可与微电子元件102的背面137热耦合,如通过导热材料142,如导热油脂、导热粘接剂、或具有相对低的熔点的接合金属,如焊料、锡、铟、金或其他材料。当导热材料142同时导电,如为金属或导电金属化合物时,介电层(未示出)可使微电子元件102的背面137与这种导热且导电的材料142分隔开。如上所述,微电子组件或封装100能使微电子元件102、112的厚度缩减至理想的程度。以这种方式,每个微电子元件102或112的厚度可仅为第一区域105(图1A)的厚度或这种厚度加上第二区域107的较小厚度。缩减后厚度可利用散热器140获得显著有效且均匀的热传递。
图3是从封装的微电子元件112的背面115来看时的视图,示出了在背面暴露的导电元件118,以面阵的方式布置。在图3中还示出,导电元件118在第二开口123内延伸且与在微电子元件110正面103(图1)暴露的导电垫116连接,导电垫106也可以面阵的方式布置。替代地,当微电子元件的导电垫116具有不同布置时,如可布置为邻近外围边缘或可布置在正面的中心,导电元件118典型地具有匹配的模式。
现在参照图4,将描述制作根据本发明另一实施例微电子组件的制造方法。图4是局部截面图,示出了具有通孔222的插板220,导电通路224穿过通孔222而延伸。通路224可终止于分别在插板的第一主表面227和第二主表面229上暴露的导电垫226、228。
插板可具有线性的热膨胀系数(CTE-α),其小于约每摄氏度百万分之十,即“小于10ppm/℃”。硅、二氧化硅、一些陶瓷材料、一些金属及其他材料的CTE-α都在这个范围内。当插板由金属或半导体材料制成时,介电层230可覆盖第一主表面和第二主表面并衬在通孔222内,用于使通路224及垫226、228与插板220的主体绝缘。然后,如图5所示,第一晶圆202和第二晶圆212可附接至插板,晶圆的正面203、213分别面对第一插板表面227和第二插板表面229。可采用粘接剂或其他介电材料201,如玻璃,以使插板与晶圆附接。典型地,晶圆附接至插板上,使得每个晶圆的导电垫与插板的垫并置。例如第一晶圆202的导电垫204可与插板垫226并置,而第二晶圆212的导电垫214与插板垫228并置。
接下来,从图6可以看出,如通过研磨(grinding)、磨光(lapping)或抛光(polishing),晶圆的厚度缩减,如上所述。在这个步骤完成后,每个晶圆202、212具有的厚度231可对应于不可变薄区域105(图1A)的厚度,如上所述,或可具有较大厚度,包括置于不可变薄区域下方的区域107(图1A)的一些材料。在一个实施例中,晶圆202、212中一个或两个的区域107可具有高达20微米的厚度。
图7示出了穿过每个晶圆厚度、包括晶圆上的导电垫204、214而延伸的第一开口206和第二开口216形成后,处理过程的随后阶段。例如,这种开口可通过蚀刻、激光图案化、喷砂、机械球磨、或可应用至每个晶圆的半导体材料的其他技术而制成。在穿过晶圆厚度而延伸的开口形成后,介电层232可在开口的内壁上形成,之后,开口可穿过相应的垫204、214而延伸。形成开口206、216和介电层232的过程可如以下任意或所有专利申请中描述:公开号为20080246136A1的美国专利公开说明书,或申请日都为2010年7月23号,申请号分别为12/842717、12/842612、12/842669、12/842692、12/842587的美国专利申请,这些专利申请中公开的内容以引用的方式并入本文。在一个实施例中,介电层232可选择性地在开口206、216内暴露的半导体或导体表面上、及微电子元件的暴露表面上,通过电泳沉积或电解沉积而形成。
图8示出了可选步骤,其中各晶圆垫204、214与插板垫226、228的并置表面之间的介电材料或结合材料的一部分可去除。
然后,如图9所示,一层或多层金属可沉积在开口206、216内,以形成分别在微电子组件面向外的表面237、239暴露的导电元件236、238。导电元件236、238分别与晶圆202、212的导电垫204、214接触,并通过插板垫226、228及穿过插板而延伸的通路224而电耦合在一起。
在图9所示的实施例中,由通路224穿过其而延伸的开口222,与穿过第一晶圆202及第二晶圆212而延伸的开口206、216相交。但是,其他布置也是可以的。例如,从图10可以看出,晶圆202、212中一个或二者内的导电元件可沿一个或多个横向240(插板主表面227延伸的方向)与通路224偏离。在图10所示的情况下,导电元件236、238都可沿相同方向与通路偏离,内部形成导电元件的开口206、216中没有一个与相对应插板开口222相交,通路224穿过插板开口222而延伸,并与导电元件236、238电连接。从图9可以看出,微电子元件202、212内开口206、216的内表面可相对于每个微电子元件各自的第一表面104沿第一方向和第二方向延伸,以限定明显的角度109。
从图10可以进一步看出,插板通路224与垫204、214之间的电连接可以一种或多种方式设置。例如,微电子元件212可具有远离导电垫214朝插板220延伸的迹线244,而迹线244可与插板通路224导电结合,如通过采用如焊料、锡或铟等接合金属245、扩散结合、或替代地,在加热及加压下使金属与金属直接接合。在另一示例中,插板220可具有导电迹线242,其远离通路224以插板第一主表面227延伸的方向240而延伸。在这种情况下,导电元件236的制造过程形成了第一晶圆的垫204与插板的迹线242之间的电连接。
图11示出了另一示例,其中导电元件236、238沿方向240相互偏离。
现在参照图12,示出了另一变例,其中插板320内的开口322为锥形的,从而沿朝着一个微电子元件202的正面的方向,开口宽度逐渐变小。微电子元件202、212内的开口306、316形成后,可在开口壁及第一表面上形成介电层307、317。此后,从图13可以看出,可除去在导电垫304、314的并置表面与插板通路的相应结合表面326、328之间的如粘接剂等介电材料的一部分。图14示出了与插板通路的相应表面接触的导电元件336、338已形成后的微电子组件,其中沉积的导电材料,如沉积金属,填充导电垫304、314的表面与插板通路的相应表面326、328之间的空间,导电垫304、314的表面与相应表面326、328并置。
图15示出了另一变例,其中导电元件424穿过插板开口而延伸,具有如截头圆锥形的形状,与插板开口422的内表面的轮廓不一致。图15所示结构的制造方法也可与上文所述(图4至图14)不同。在这种情况下,当插板420与微电子元件402、412接合时,插板可具有在第一主表面与第二主表面之间延伸的开口422,其内填充有介电材料426。在微电子元件402及其上的导电垫404内形成开口406时,穿过粘接层或结合层401及穿过介电材料426的区域,材料去除过程继续,直至导电垫414的上表面414a在开口406内暴露。此后,开口406内可填充一层或多层金属或导电金属化合物,以形成穿过微电子元件402及插板420而延伸的导电元件436。
图16示出了图15所示结构的变例,其中导电元件536形成为中空结构,衬在开口406内的介电层的内表面,但并不充满开口。导电元件536与开口406内暴露的导电垫414的上表面414a接触。图17示出了另一变例,其中开口506穿过两个导电垫504、514的厚度而延伸,使得在形成时,导电元件636、638可直接相互接触。
图18示出上述实施例(图11)的变例,其中插板720包含一个或多个无源电路元件。例如插板可包含第一电容750,具有分别与沿插板720主表面751延伸的迹线756、758电连接的电极752、754。类似地,插板可包含第二电容760,具有分别与沿插板720主表面761延伸的迹线766、768电连接的电极762、764。一些迹线758、766可通过另外的导电元件736、738而与导电垫连接,在组件工作过程中承载随时间变化的信号,而其他迹线756、768可与一个或多个导电垫(未示出)连接,在组件工作过程中承载参考电位如地面或电源电压。
在图18所示实施例的其他变例中,无源电路元件可包括设置为如图18所示的一个或多个电感器、电阻器或其他无源电路元件,且具有如从图18可以看出的电互连布置。
微电子组件及包含微电子组件的更高等级的组件的结构和制造方法可包括,下面的美国专利申请中所描述的结构和制造步骤。奥加涅相(Oganesian)等人共同拥有、共同待决、同日申请的、名称为“具有分段形成的贯通硅通路及芯片上载体的堆叠微电子组件”("STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP")(美国临时专利申请号为61/419033,律师案卷号为Tessera 3.8-619)的美国临时专利申请;及名称为“具有分段形成的贯通硅通路及复数个有源芯片的堆叠微电子组件”("STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES WITH PLURAL ACTIVE CHIPS")(美国临时专利申请号为61/419037,律师案卷号为Tessera 3.8-632)的美国临时专利申请。以下都在2010年7月23日申请的美国专利申请中也有描述,申请号分别为12/842717、12/842651、12/842612、12/842669、12/842692及12/842587的美国专利申请。所有这些专利申请所公开的内容都以引用的方式并入本文。上述的结构提供了超常的三维互连能力。这些能力可用于任意类型的芯片。仅以示例的方式说明,芯片的下面的组合可在如上文所述的结构中包括:(i)处理器及与该处理器一起使用的存储器;(ii)相同类型的复数个存储器芯片;(iii)不同类型的复数个存储器芯片,如DRAM(动态随机存储器)和SRAM(静态存储器);(iv)图像传感器和用于处理来自传感器的图像的图像处理器;(v)专用集成电路(“ASIC”)和存储器。上述的结构可在不同的电子系统的构造中利用。例如,根据本发明进一步实施例的系统800包括如上文所述的结构806与其他电子元器件808和810配合使用。在描述的示例中,元器件808为半导体芯片,而元器件810为显示屏,但任意其他元器件都可应用。当然,尽管为清楚图示起见,在图19中只描述了两个附加元器件,系统可包括任意数量的这种元器件。如上文所述的结构806可为,例如,上文所述的与图1、图9、图10、图14、图15、图16及图18相关的微电子组件100。在另一变例中,二者都可提供,且任意数量的这种结构都可应用。结构806和元器件808、810都安装至以虚线示意性地描绘的共同外壳801内,且彼此电互连以形成所需的电路。在所示的示例性系统中,系统包括如柔性印刷电路板等的电路板802,且电路板包括使元器件之间彼此互连的大量导电体804,其中在图19中只示出了一个。但是,这只是示例,任意适当的用于形成电连接的结构都可应用。外壳801作为便携式外壳而描述,具有用于如移动电话或个人数字助理等的类型,显示屏810暴露在外壳的表面。其中结构806包括如成像芯片等的光敏元件,还可配置镜头811或其他光学器件,以提供光至结构的路线。同样,图19内所示的简化系统只是示例,其他系统,包括一般视为固定结构的系统,如台式计算机、路由器及类似的结构,都可应用上述的结构而制成。
因为在不偏离本发明的情况下,上述的这些实施例和其他变例及技术特征的组合都可利用,优选实施例的上述描述应当认为是本发明范围的说明而不是限制。
工业实用性
本发明享有广泛的工业实用性,包括但不限于,微电子组件及制造微电子组件的方法。
Claims (28)
1. 微电子组件,包括:
第一微电子元件和第二微电子元件,每个微电子元件都包含邻近其正面的有源半导体器件,每个微电子元件都具有远离自身正面的背面,且每个都具有在自身正面暴露的导电垫;
插板,所述插板的材料具有小于百万分之十每摄氏度的热膨胀系数(“CTE”),所述插板具有朝向相反的第一表面与第二表面,及在所述插板的开口内延伸、且在所述第一表面及所述第二表面暴露的第二导电元件,所述第一表面面对所述第一微电子元件的正面,且所述第二表面面对所述第二微电子元件的正面;
所述第一微电子元件和第二微电子元件中的每个进一步包括在开口内延伸的第一导电元件,所述开口从各微电子元件的背面朝各微电子元件的正面延伸,其中至少一个所述第一导电元件穿过所述第一微电子元件或所述第二微电子元件中相应一个的导电垫而延伸,且所述第一导电元件与所述第二导电元件电耦合。
2. 根据权利要求1所述的微电子组件,其中由所述第二导电元件穿过其延伸的所述开口与穿过所述第一微电子元件和所述第二微电子元件而延伸的至少一个开口相交。
3. 根据权利要求1所述的微电子组件,其中由所述第二导电元件穿过其延伸的所述开口与穿过所述第一微电子元件及所述第二微电子元件而延伸的每个开口都相交。
4. 根据权利要求1所述的微电子组件,其中由所述第二导电元件穿过其延伸的所述开口与穿过所述第一导电元件和所述第二微电子元件而延伸的任一开口都不相交。
5. 根据权利要求1所述的微电子组件,其中所述插板基本上由介电材料组成。
6. 根据权利要求1所述的微电子组件,其中所述插板基本上由金属或半导体材料组成,其中所述插板内的所述开口衬有绝缘体。
7. 根据权利要求1所述的微电子组件,其中每个微电子元件的所述第一导电元件都穿过相应导电垫而延伸。
8. 根据权利要求1所述的微电子组件,其中所述第二导电元件包括在所述第一表面和第二表面暴露的第二导电垫,所述第一微电子元件及所述第二微电子元件的垫为第一垫,所述第一垫与所述第二垫并置,所述第一导电元件与所述第一垫及所述第二垫的并置表面接触。
9. 根据权利要求1所述的微电子组件,其中所述插板内由第二导电元件穿过其延伸的所述开口,具有相对于所述插板的第一表面及第二表面以直角延伸的内壁。
10. 根据权利要求1所述的微电子组件,其中所述插板内由第二导电元件穿过其延伸的所述开口沿所述插板的第一表面与第二表面之间的方向逐渐变细。
11. 根据权利要求9所述的微电子组件,其中所述第一微电子元件内的开口沿从所述第一微电子元件的背面朝自身正面的方向逐渐变细。
12. 根据权利要求10所述的微电子组件,其中所述第一微电子元件内的开口沿从所述第一微电子元件的背面朝自身正面的方向逐渐变细。
13. 根据权利要求9所述的微电子组件,其中所述第一微电子元件内开口的内表面相对于所述第一微电子元件的正面以直角延伸。
14. 根据权利要求10所述的微电子组件,其中所述第一微电子元件内开口的内表面相对于所述第一微电子元件的正面以直角延伸。
15. 根据权利要求1所述的微电子组件,其中所述第二导电元件与所述插板内开口的内表面的轮廓一致。
16. 根据权利要求1所述的微电子组件,其中所述第二导电元件与所述插板内开口的内表面的轮廓不一致。
17. 根据权利要求1所述的微电子组件,其中所述插板内开口及所述第一微电子元件或所述第二微电子元件中至少一个内的开口为锥形,彼此沿相反的方向变小。
18. 根据权利要求1所述的微电子组件,其中所述插板还包括至少一个无源元器件,与所述第一微电子元件或所述第二微电子元件中至少一个电连接。
19. 系统,包括,根据权利要求1所述的微电子组件,及一个或多个与所述微电子组件电连接的其他电子元器件。
20. 根据权利要求19所述的系统,进一步包括壳体,所述微电子组件和所述其他电子元器件安装至所述壳体。
21. 微电子组件的制造方法,包括:
将第一微电子组件和第二微电子组件与二者之间的插板组装,每个微电子元件都包含邻近自身正面的有源半导体器件,且具有远离自身正面的背面及在自身正面暴露的导电垫,
所述插板基本上由半导体或无机介电材料中至少一种组成,所述插板具有朝向相反的第一表面和第二表面,及穿过所述插板而延伸、且在所述第一表面及所述第二表面暴露的第二导电元件,使得所述第一表面面对所述第一微电子元件的正面,而所述第二表面面对所述第二微电子元件的正面;
然后形成在开口内延伸的第一导电元件,所述开口从各微电子元件的背面朝着自身正面延伸,至少一个所述第一导电元件穿过至少一个微电子元件的相应导电垫而延伸,所述第一导电元件与所述第二导电元件电耦合,其中所述微电子元件内开口的内表面相对于每个微电子元件的相应正面沿第一方向和第二方向延伸,以限定明显的角度。
22. 根据权利要求21所述的方法,其中每个微电子元件的所述第一导电元件穿过相应导电垫而延伸。
23. 根据权利要求21所述的方法,其中所述第二导电元件包括在所述第一表面和所述第二表面暴露的第二导电垫,每个微电子元件的所述第一导电垫与所述第二垫中的一个并置,所述第一导电元件与所述第一垫及所述第二垫的并置表面接触。
24. 根据权利要求21所述的方法,其中所述插板内由所述第二导电元件穿过其延伸的所述开口具有相对于所述插板的第一表面和第二表面以直角延伸的内壁。
25. 根据权利要求21所述的方法,其中所述插板内由所述第二导电元件穿过其延伸的所述开口沿所述插板的第一表面与第二表面之间的方向逐渐变细。
26. 根据权利要求21所述的方法,其中所述第二导电元件与所述插板内开口的内表面的轮廓一致。
27. 根据权利要求21所述的方法,其中所述第二导电元件与所述插板内开口的内表面的轮廓不一致。
28. 根据权利要求27所述的方法,其中所述插板内开口和所述第二导电元件沿相反的方向逐渐变细。
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EP2647046A1 (en) | 2013-10-09 |
CN103329266B (zh) | 2016-10-19 |
US8637968B2 (en) | 2014-01-28 |
WO2012075371A1 (en) | 2012-06-07 |
US20120139094A1 (en) | 2012-06-07 |
TW201246500A (en) | 2012-11-16 |
JP5857065B2 (ja) | 2016-02-10 |
KR20130122959A (ko) | 2013-11-11 |
JP2013546192A (ja) | 2013-12-26 |
KR101871866B1 (ko) | 2018-06-27 |
EP2647046B1 (en) | 2020-11-18 |
TWI458070B (zh) | 2014-10-21 |
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