CN103370784B - 同时的晶圆结合及互连接合 - Google Patents

同时的晶圆结合及互连接合 Download PDF

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Publication number
CN103370784B
CN103370784B CN201180067909.3A CN201180067909A CN103370784B CN 103370784 B CN103370784 B CN 103370784B CN 201180067909 A CN201180067909 A CN 201180067909A CN 103370784 B CN103370784 B CN 103370784B
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metal
pad
dielectric layer
type surface
microelectronic element
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CN103370784A (zh
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瓦格·奥甘赛安
贝勒卡西姆·哈巴
伊利亚斯·默罕默德
皮尤什·萨瓦利亚
克雷格·米切尔
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

本发明公开了两元件(100,200)的微电子组件(300)及其形成方法。微电子元件(100)包括主表面(102)、及在主表面(102)暴露的介电层(120)和至少一个结合垫(110)。微电子元件(100)可包含复数个有源电路元件。第一金属层(130)沉积为覆盖至少一个结合垫(110)和介电层(120)。提供了具有第二金属层(230)沉积于其上的第二元件(200)，第一金属层(130)与第二金属层(230)接合。组件(300)可沿切割线(301)切割为单独的单元，每个都包括芯片。

Description

同时的晶圆结合及互连接合
相关申请的交叉引用
本申请要求临时申请号为61/424906、申请日为2010年12月20日的美国专利申请的申请日之利益，其公开的内容以引用的方式并入本文。
背景技术
本发明涉及晶圆结合，尤其是，当晶圆结合在一起时可同时伴随着这些晶圆电互连的晶圆结合。
晶圆级封装技术可在各种应用中采用，以同时地制作包括复数个如半导体芯片的微电子元件，以一个在另一个之上的方式堆叠，并在芯片之间电互连的微电子组件。在一些情况下，可采用晶圆级封装技术，以制作包括与作为封装层的介电元件或半导体元件安装在一起的微电子元件的微电子组件，微电子元件具有有源电路元件，如半导体芯片。这种技术通常要求微电子器件晶圆，即具有有源电路元件的器件晶圆，与另一元件接合，另一元件可为具有与该器件晶圆相同尺寸和形状的另一器件晶圆或封装层（如顶层晶圆或其他晶圆）。
这种晶圆级处理的一个挑战是在晶圆之间获得足够平的界面，并使各晶圆上的触点之间可靠地电互连。在这个方面，进一步的改进将是可取的。
在芯片的任一几何布置中，尺寸是重要的考虑因素。随着便携式电子装置的快速发展，芯片的更紧凑几何布置的需求变得更为强烈。仅以示例的方式说明，通常称为“智能手机”的装置，集成了移动电话及强大的数据处理器、存储器、如全球定位系统接收器、数码相机等的辅助器件等的功能，以及局域网连接，并伴有高分辨率的显示及相关的图像处理芯片。这种装置可提供如完整的互联网连接、包括高清视频等的娱乐、导航、电子银行及更多的性能，都设置在袖珍式的装置内。复杂的便携装置要求把大量芯片包装至狭小的空间内。此外，一些芯片具有许多输入和输出接口，一般称为“I/O口”。这些I/O口必须与其他芯片的I/O口互连。这种互连应尽量短且应具有低的阻抗，以使信号传输延迟最小化。形成这些互连的元器件不应大幅度增加组件的尺寸。类似需求也出现在其他应用中，例如，数据服务器，如在互联网搜索引擎中使用的数据服务器。例如，在复杂芯片之间设置大量短且阻抗低的互连的结构，可增加搜索引擎的频带宽度（bandwidth），并降低其能耗。
发明内容
本发明的第一方面为形成微电子组件的方法，包括：提供具有主表面、和在主表面暴露的介电层以及至少一个结合垫的微电子元件，微电子元件包含复数个有源电路元件；提供具有小于10ppm/℃的热膨胀系数的第二元件，第二元件具有主表面和在主表面暴露的介电层；沉积第一金属层，其覆盖微电子元件的至少一个结合垫和介电层；沉积第二金属层，其覆盖第二元件的介电层；使第一金属层与第二金属层接合。
根据这个第一方面的某些实施例，每个沉积步骤都可包括沉积的第一阶段，包括在微电子元件或第二元件中至少一个上沉积铜或铝中至少一种。微电子元件可为芯片，第二元件可具有与芯片面积基本相同的面积。沉积第一金属层的步骤可包括，在微电子元件的基本上整个主表面上沉积金属，且该方法可进一步包括去除金属的一部分，使得金属延伸至微电子元件主表面上方预定高度。该方法进一步包括，在至少一个结合垫与介电层之间的间隙处，除去直接覆盖微电子元件主表面的金属。间隙可足够大，以提供足以补偿第一金属层顶面的共面度差异的总量、与第二金属层顶面的共面度差异的总量之和的缓冲容积，第一金属层覆盖微电子元件的至少一个结合垫和介电层，第二金属层覆盖第二元件上的介电层及在其主表面暴露的至少一个结合垫。
接合步骤可包括，加热第一金属层和第二金属层中至少一个至约50℃至300℃之间的温度。第一金属层和第二金属层中至少一个可包括放热的、且通过加热而热激活的至少一部分，接合步骤可包括，加热放热金属层的至少一部分，以热激活该层。第二元件可为包含复数个有源电路元件的微电子元件，且可包括在主表面暴露的至少一个结合垫。至少一个元件可包括与至少一个结合垫电连接的贯通硅通路，其从该元件的主表面朝远离主表面的元件第二表面延伸。贯通硅通路可贯穿微电子元件及第二元件而延伸，且可与微电子元件的结合垫及第二元件的结合垫电连接。接合步骤可包括，使微电子元件的至少一个结合垫与第二元件的至少一个结合垫并置，并加热第一金属层和第二金属层至接合温度。每个元件上的至少一个结合垫可包括以复数排对齐的复数个结合垫。每个元件的至少一个结合垫可包括邻近相应主表面外周而对齐的复数个结合垫，且介电层可覆盖主表面的中心区域。
至少一个元件的介电层可为可压缩的，以吸收任何尺寸公差。至少一个结合垫高出微电子元件主表面的高度可与介电层高出微电子元件主表面的高度不同。至少一个沉积步骤可包括沉积回流金属，且接合步骤可包括加热回流金属至能导致回流金属熔化的温度。回流金属可从锡、焊料、铟、金、及其任意组合所组成的群组中选择。沉积步骤可包括沉积铜，接合步骤可包括在元件间加热及加压，使得覆盖微电子元件的铜与覆盖第二元件的铜熔合在一起。该方法可进一步包括在覆盖至少一个元件的铜上沉积金层，且接合步骤可包括加热金至金扩散入铜内的温度。沉积第一金属层和第二金属层的步骤可包括沉积基底金属和覆盖基底金属的金层，且接合步骤可包括对元件加热并加压，直至第一金属层与第二金属层熔合在一起。
本发明的第二方面为微电子组件，包括：微电子元件，具有主表面、和在主表面暴露的介电层及至少一个结合垫，微电子元件包含复数个有源电路元件；第二元件，具有小于10ppm/℃的热膨胀系数，第二元件具有主表面和在其主表面暴露的至少一个结合垫及介电层；第一金属层，覆盖微电子元件的至少一个结合垫和介电层，其中在第一金属层内，至少一个结合垫与介电层之间形成间隙；第二金属层，覆盖第二元件的至少一个结合垫和介电层；且其中第一金属层和第二金属层的覆盖介电层的第一部分接合在一起，而第一金属层和第二金属层的覆盖至少一个结合垫并与第一部分分开的第二部分，接合在一起，从而使微电子元件与第二元件机械连接及电连接。
根据该第二方面的某些实施例，微电子元件可为芯片，且第二元件可具有与芯片面积基本相同的面积。间隙可足够大，以提供足以补偿第一金属层顶面的共面度差异的总量、与第二金属层顶面的共面度差异的总量之和的缓冲容积，第一金属层覆盖微电子元件的至少一个结合垫和介电层，第二金属层覆盖第二元件的至少一个结合垫和介电层。第一金属层和第二金属层中至少一个可包括放热的、且通过加热而热激活的至少一部分。
第二元件可为包含复数个有源电路元件的微电子元件。至少一个元件可包括与至少一个结合垫电连接的贯通硅通路，其从该元件的主表面朝远离主表面的元件第二表面延伸。贯通硅通路可贯穿微电子元件及第二元件而延伸，且可与微电子元件的结合垫及第二元件的结合垫电连接。每个元件的至少一个结合垫可包括以复数排布置的一系列结合垫。每个元件的至少一个结合垫可包括邻近各元件外周而排列的复数个结合垫，且介电层可覆盖主表面的中心区域。在第二金属层内，至少一个结合垫与介电层之间可形成间隙。
至少一个元件的介电层可为可压缩的，以吸收任何尺寸公差。至少一个结合垫高出微电子元件主表面的高度可与介电层高出微电子元件主表面的高度不同。至少一个金属层可包括回流金属，回流金属从锡、焊料、铟、金、及其任意组合所组成的群组中选择。第一金属层和第二金属层中每个都可包括可被回流金属润湿的金属层，其中回流金属覆盖可润湿的金属层。第一金属层和第二金属层可包含铜。组件可进一步包括覆盖第一金属层和第二金属层中至少一个的金层。第一金属层和第二金属层可不直接覆盖元件的相应主表面。
本发明的第三方面为微电子组件，包括：微电子元件，具有主表面和在主表面暴露的介电层；第二元件，具有主表面和在主表面暴露的介电层；第一晶圆和第二晶圆的主表面相互面对，复数个导电金属元件位于介电层之间，金属元件与微电子元件电隔离，其中金属元件使第一晶圆与第二晶圆相互接合。
根据第三方面的某些实施例，第二元件具有小于10ppm/℃的热膨胀系数。微电子元件可包含复数个有源电路元件。第二元件可为微电子元件，包含复数个有源电路元件，且可包括在主表面暴露的至少一个结合垫。微电子元件可为芯片，第二元件可具有与芯片面积基本相同的面积。在每个元件上，沿主表面在每个金属元件与介电层的相邻部分之间可形成间隙，且间隙可足够大，以提供足以补偿覆盖微电子元件主表面的金属元件的顶面与介电层的顶面的共面度差异的总量、与覆盖第二元件主表面的金属元件的顶面与介电层的顶面的共面度差异的总量之和的缓冲容积。至少一个元件的介电层可为可压缩的，以吸收任何尺寸公差。
本发明的第四方面为系统，包括上述的结构及与该结构电连接的一个或多个其他电子元器件。根据此第二方面的某些实施例，系统可进一步包括外壳，结构及其他电子元器件安装至外壳。
本发明另一方面提供系统，包含根据本发明之前方面的微电子结构、根据本发明之前方面的集成芯片、或二者，与其他电子器件的组合。例如系统可位于单个外壳内，外壳可为便携式外壳。与同类常规系统相比，根据本发明此方面优选实施例的系统可更紧凑。
附图说明
图1是根据本发明第一实施例微电子元件的截面图。
图2是图1所示元件的一部分的放大视图。
图3是图1所示元件的俯视图。
图4是其上具有薄金属层的图1所示元件的截面图。
图5是图4所示元件的一部分的放大视图。
图4A是根据本发明另一实施例元件的截面图。
图5A是其上具有薄金属层的图4A所示元件的一部分的截面图。
图6是图4所示元件的俯视图。
图7是其上具有可回流金属层的图4所示元件的截面图。
图8是图7所示元件的一部分的放大视图。
图9是图7所示元件的俯视图。
图10和图11是根据本发明实施例的两元件组件的截面图。
图12和图13是根据本发明具有贯通硅通路的组件的截面图。
图14是根据本发明另一实施例的两元件组件的截面图。
图15是根据本发明另一实施例的两元件组件的截面图。
图16是根据本发明一个实施例的系统的示意图。
具体实施方式
根据本发明一个实施例，图1至图3绘出了微电子元件100，如包含有源电路元件的器件晶圆，具有主表面102和远离主表面102的第二表面104。介电层120和至少一个结合垫110在主表面102暴露。考虑到结合垫110高出主表面102，介电层120优选地由可压缩的材料组成，以吸收任何尺寸公差。在某些实施例中，至少一个结合垫110高出主表面102的高度与介电层120高出主表面102的高度不同，如图2中更清楚地示出。
微电子元件100可为晶圆或具有复数个有源电路元件的半导体芯片，或为包含复数个半导体芯片的晶圆的一部分。在另一示例中，微电子元件100可为，包括布置在阵列内并保持在一起以同时进行处理的复数个有源芯片的再构造晶圆或嵌板。在图3中非常清楚地示出的晶圆的一部分，包含在切割线112处附接在一起的四个半导体芯片111。结合垫可在阵列内布置，例如包括，布置在一排或多排内。例如，结合垫110可设置在邻近沿每个芯片外周125的切割线的各排内。在某些实施例中，介电层120可设置在周围的结合垫以内，以覆盖主表面102的中心区域。
图4至图6绘出的微电子元件100，具有覆盖结合垫110和介电层120的金属层130。金属层130可相对较薄。如图7至图9中所示，可沉积接合金属、如可回流金属层150，以覆盖金属层130。当金属层150为可回流的时，其可包括锡、焊料、铟、金或其任意组合。当金属层150为可回流金属时，下方的金属层130可被可回流金属润湿。在特定示例中，可润湿金属层130可包括铜或铜合金、铝或铝合金、或其组合的层。这个层或这些层可形成金属层130的基底结构。这种金属层130可进一步包括覆盖基底结构的镍层。在另一示例中，金属层130可包括这种镍层及覆盖镍层的金层。
金属层150可不直接覆盖主表面102，且金属层150内可存在间隙140，其位于结合垫110与介电层120之间。间隙140可在每个相邻对的结合垫110与介电层120之间都存在。每个单独的结合垫110和介电层都可在主表面102上隔离。
图10和图11绘出了与另一元件200组装在一起的微电子元件100，典型地形成晶圆级组件300，或包括一个或多个有源芯片与另一有源芯片或其他元件结合并电互连的其他组件300。元件200可与微电子元件100基本类似，具有有源电路元件，或可为具有无源电路元件的无源元件或晶圆。元件200典型地由半导体材料制成，且典型地为包含有源电路元件如晶体管、二极管等的半导体器件晶圆。但是，在特定实施例中，元件200可为无源的或基本空白的半导体晶圆或其他元件，其可包括玻璃或陶瓷材料、或热膨胀系数(CTE)小于10ppm/℃（百万分之十每摄氏度）的其他材料的基底。元件200可如图4A和图5A所示，例如具有小于10ppm/℃的热膨胀系数的元件。元件200具有主表面202、远离主表面202的第二表面204、及在主表面202暴露的介电层220。在某些实施例中，如图10和图11中所绘出的，元件200可为包含复数个有源电路元件的微电子元件，且可包括至少一个结合垫210。薄金属层230覆盖介电层220，如图5A所示，且还覆盖结合垫210，如图10所示。可回流金属层250沉积为覆盖金属层230。金属层230、250可与上述的微电子元件或晶圆100的金属层130、150一样。金属层250内可存在间隙240，位于结合垫210与介电层220之间，或在为无源元件的情况下，位于介电层220的相邻部分之间。
在形成组件300时，提供元件100、200，其中至少元件100为有源微电子元件。金属层150、250在各自元件上沉积。这个步骤可以不同方式进行。例如，金属可在各自元件100、200的基本上整个主表面102、104上沉积，覆盖位于其上的所有结合垫110、210和/或介电层120、220。然后，可去除金属的一部分，使得金属延伸至主表面102、104上方预定高度。然后可在结合垫110、210与介电层120、220之间的间隙140、240的位置，除去直接覆盖主表面102、104的金属。另外，沉积各金属层150、250的每个步骤都可包括沉积的第一阶段，例如，可包括铜或铝的金属。
在接合之前，元件100的结合垫110与元件200的结合垫210并置，如图10所示。结合垫110、210一起可包括最终位于各自的主表面102、202的介电层120、220之间的复数个电隔离的金属元件。介电材料上的金属层130、230（或隔离的金属元件）可与各元件100、200内的内部元件电隔离，或替代地，可用于与电源或地面连接。然后，如图11所示，元件100、200相互接合且金属层150与金属层250接合，以形成组件300，例如通过加热回流金属至可导致它们熔化并融合在一起的温度。在一个实施例中，至少一个金属层150、250加热至约为50℃至300℃之间的温度。例如，焊料、锡、铟、金或其组合的金属层的接合，通常可在低于300℃的温度下进行。至少一个金属层150、250可包括放热的、且通过加热而热激活的至少一部分，且接合步骤可包括加热放热金属层的该至少一部分，以热激活该层。优选地，任何尺寸公差被可压缩的至少一个介电层120、220予以处理和吸收。
间隙140、240可足够大，以提供足以补偿覆盖各结合垫110、210及介电层120、220的金属层150、250顶面的共面度差异总量的缓冲容积（relief volume）。从图11可以看出，组合后金属层150、250的某些部分可凸出至间隙140、240内，如区域152所示。替代地，在邻接间隙140、240处，这种组合后金属层的部分可呈现出具有凹入表面，如区域154所示。组合后金属层150、250的一部分具有基本为直线且竖直的边缘也是可能的，如156处所示。因此，元件100、200借助于可回流金属层150、250而接合，可回流金属层150、250是能电连接的，同时由于与元件100、200相关的任何尺寸差异而潜在地溢流至间隙140、240内。
在组件300的变例中，金属层150、250可包含铜，而不是可回流金属，且在一些情况下，金属层130、230中的一个或二者都可省略。这些层的接合包括在元件100、200之间加热及加压，使得铜层熔合在一起。金层可覆盖金属层150、250中至少一个，可加热至在金属层150、250的接合界面处使金扩散入铜内的温度。
在另一实施例中，沉积金属层150、250的步骤包括，沉积基底金属及覆盖基底金属的金层。然后对该元件加热并加压，直到金属层150、250熔合在一起。
在一个实施例中，在元件100、200结合在一起后，组件300可沿切割线切割成单独的微电子组件或单元，其中的一个这种切割线指示为线301。典型地，每个单元都包括有源芯片及元件200的相应部分，有源芯片即包含有源电路元件的芯片，而元件200的相应部分可包括另一有源芯片也可不包括。组件300可进一步构造为如图12所示，使得元件100、200中至少一个包括与一个结合垫电连接、并贯穿该元件厚度而延伸的贯通通路302。例如，贯通通路302贯穿元件100而延伸，并提供了其内与结合垫110电连接的导电元件。类似地，导电贯通通路302可贯穿元件200而延伸，并与结合垫210电连接。导电贯通通路303可同时贯穿元件100及200而延伸，且与元件100的结合垫110及元件200的结合垫210电连接，如图13所示。
各种制造导电贯通通路的方法可如，例如，临时申请号为61/419033及61/419037的美国临时专利申请，公开号为2008/0246136的美国专利申请公开说明书，或申请号为12/842717及12/842651的美国专利申请中所描述，这些专利申请中公开的内容以引用的方式并入本文。
在某些实施例中，在使元件100与200接合前只存在一个金属层150或250。这种结构如图14所示，其中元件1100包括覆盖金属层1130的金属层1150，元件1200只包括作为其顶层的金属层1230，并没有其他金属层覆盖。
在另一实施例中，如图15所示，元件2200可为插板（interposer）、顶层晶圆（coverwafer）或空白晶圆，其上没有暴露的结合垫。元件2100、2200中每个分别包括介电层2120、2220，和分别覆盖相应介电层2120、2220的金属层2130、2230。覆盖元件2100的主表面2102的结合垫2110邻近元件2200的主表面2202的暴露部分。可仅覆盖介电层2120、2220而没有覆盖结合垫2110的金属层2130、2230，可通过接合的可回流金属层2150、2250而电互连。
通过上述的过程，使各晶圆或元件上的金属层130（图11）或金属层2130（图15）相互电隔离是可能的，且在晶圆或元件结合在一起之前及之后，金属层与其上设置金属层的晶圆或元件电隔离也是可能的。替代地，晶圆或元件上的一些或所有金属层130或230，可用于与电源或地面连接。例如，晶圆上的金属层130或230可延伸至同一晶圆的接地结合垫上或与其电连接，接地结合垫为该晶圆的芯片提供接地连接。在又一实施例中，晶圆上的金属层130或230可延伸至同一晶圆的电源结合垫上或与其电连接，电源结合垫为该晶圆的芯片提供电源连接。在又一实施例中，每个微电子组件的金属层130、230的一些部分可延伸至接地结合垫或与其电连接，而每个微电子组件的金属层130、230的其他部分可延伸至电源结合垫或与其电连接。在这些情况下，两个晶圆的每个芯片的金属层，例如，每个组件内的金属层130、230及其间的可回流金属150（图11）都可用于与其内包含芯片的微电子组件的接地端子或电源端子连接。
通过根据上述的一个或多个实施例在之前描述的过程，本文提供了典型地可补偿结合界面的非平面度的技术。在一个示例中，各晶圆的金属层130、230及结合垫110、210上的接合金属层或可回流金属层150、250可具有1微米的厚度。在这种实施例中，金属层150（如图11）的标称接合厚度为2微米。本文提供的技术可补偿在晶圆整个尺寸内结合界面的平面度的总差异，达到高于0.5微米的程度。在另一示例中，在接合金属层或可回流金属150、250具有适当厚度时，本文的技术可补偿更大的非平面度，例如3微米。
上述的结构提供了超常的三维互连能力。这些能力可用于任意类型的芯片。仅以示例的方式说明，芯片的下面的组合可在如上文所述的结构中包括：（i）处理器及与该处理器一起使用的存储器；（ii）相同类型的复数个存储器芯片；（iii）不同类型的复数个存储器芯片，如DRAM（动态随机存储器）和SRAM（静态存储器）；（iv）图像传感器和用于处理来自传感器的图像的图像处理器；（v）专用集成电路（“ASIC”）和存储器。上述的结构可在不同的电子系统的构造中利用。例如，根据本发明进一步实施例的系统900包括如上文所述的结构906与其他电子元器件908和910配合使用。在描述的示例中，元器件908为半导体芯片，而元器件910为显示屏，但任意其他元器件都可应用。当然，尽管为清楚图示起见，在图16中只描述了两个附加元器件，系统可包括任意数量的这种元器件。如上文所述的结构906可为，例如，复合芯片或包含复数个芯片的结构。在另一变例中，二者都可提供，且任意数量的这种结构都可应用。结构906和元器件908、910都安装至以虚线示意性地描绘的共同外壳901内，且彼此电互连以形成所需的电路。在所示的示例性系统中，系统包括如柔性印刷电路板等的电路板902，且电路板包括使元器件之间彼此互连的大量导电体904，其中在图16中只示出了一个。但是，这只是示例，任意适当的用于形成电连接的结构都可应用。外壳901作为便携式外壳而描述，具有用于如移动电话或个人数字助理等的类型，显示屏910暴露在外壳的表面。其中结构906包括如成像芯片等的光敏元件，还可配置镜头911或其他光学器件，以提供光至结构的路线。同样，图16内所示的简化系统只是示例，其他系统，包括一般视为固定结构的系统，如台式计算机、路由器及类似的结构，都可应用上述的结构而制成。
因为上述的这些实施例和其他变例及技术特征的组合，在不偏离本发明的情况下都可利用，优选实施例的上述描述应当认为是本发明范围的说明而不是限制。
尽管本发明参照特定应用的实施例进行描述，可以理解的是，这些实施例只是说明本发明的原理和应用。因此，应理解为，在不偏离由附加的权利要求书所限定的本发明实质和范围的情况下，说明的实施例可做出许多修改及可设计出其他布置。
工业实用性
本发明享有广泛的工业实用性，包括但不限于，微电子组件及其形成方法。

Claims (49)

1.形成微电子组件的方法，包括如下步骤：
提供具有主表面和在所述主表面暴露的介电层以及至少一个结合垫的微电子元件，所述微电子元件包含复数个有源电路元件，其中所述介电层在平行于所述主表面的方向上通过间隙与所述至少一个结合垫隔离；
提供具有小于10ppm/℃的热膨胀系数的第二元件，所述第二元件具有主表面和在所述第二元件的主表面暴露的介电层；
沉积第一金属层，使得所述第一金属层的第一部分覆盖所述微电子元件的至少一个结合垫，并且所述第一金属层的第二部分覆盖所述微电子元件的介电层，所述第一部分与所述第二部分由所述间隙所隔离；
沉积第二金属层，其覆盖所述第二元件的介电层；
使所述第一金属层与所述第二金属层接合。
2.根据权利要求1所述的方法，其中每个沉积步骤都包括沉积的第一阶段，包括在所述微电子元件或所述第二元件中至少一个上沉积铜或铝中至少一种。
3.根据权利要求1所述的方法，其中所述微电子元件为芯片，所述第二元件具有与所述芯片的面积相同的面积。
4.根据权利要求1所述的方法，其中沉积第一金属层的步骤包括，在所述微电子元件的整个主表面上沉积金属，且包括去除所述金属的一部分的步骤，使得所述金属延伸至所述微电子元件的主表面上方预定高度。
5.根据权利要求4所述的方法，进一步包括，除去直接覆盖沿所述微电子元件的主表面的间隙的金属。
6.根据权利要求5所述的方法，其中所述间隙足够大，以提供足以补偿所述第一金属层的顶面的共面度的差异总量与所述第二金属层的顶面的共面度的差异总量之和的缓冲容积，所述第一金属层覆盖所述微电子元件的至少一个结合垫和介电层，所述第二金属层覆盖所述第二元件的介电层及在其主表面暴露的至少一个结合垫。
7.根据权利要求1所述的方法，其中接合步骤包括，加热所述第一金属层和所述第二金属层中至少一个至50℃至300℃之间的温度。
8.根据权利要求1所述的方法，其中所述第一金属层和所述第二金属层中至少一个包括放热的且通过加热而热激活的至少一部分，接合步骤包括，加热所述放热金属层的至少一部分，以热激活该层。
9.根据权利要求1所述的方法，其中所述第二元件为包含复数个有源电路元件的微电子元件，且包括在其主表面暴露的至少一个结合垫。
10.根据权利要求9所述的方法，其中所述微电子元件和所述第二元件中的至少一个元件包括与该元件的至少一个结合垫电连接的贯通硅通路，其从该元件的主表面朝远离该主表面的该元件的第二表面延伸。
11.根据权利要求10所述的方法，其中贯通硅通路贯穿所述微电子元件及所述第二元件而延伸，且与所述微电子元件的结合垫及所述第二元件的结合垫电连接。
12.根据权利要求9所述的方法，其中接合步骤包括，使所述微电子元件的至少一个结合垫与所述第二元件的至少一个结合垫并置，并加热所述第一金属层和所述第二金属层至接合温度。
13.根据权利要求9所述的方法，其中所述微电子元件和所述第二元件中的每个元件上的所述至少一个结合垫包括以复数排对齐的复数个结合垫。
14.根据权利要求9所述的方法，其中所述微电子元件和所述第二元件中的每个元件的所述至少一个结合垫包括邻近相应主表面外周而对齐的复数个结合垫，且所述介电层覆盖该主表面的中心区域。
15.根据权利要求1所述的方法，其中所述微电子元件和所述第二元件中的至少一个元件的所述介电层为可压缩的，以吸收任何尺寸公差。
16.根据权利要求1所述的方法，其中所述至少一个结合垫高出所述微电子元件的主表面的高度与所述介电层高出所述微电子元件的主表面的高度不同。
17.根据权利要求1所述的方法，其中至少一个沉积步骤包括沉积回流金属，且接合步骤包括加热所述回流金属至能导致所述回流金属熔化的温度。
18.根据权利要求17所述的方法，其中所述回流金属从焊料、铟、金及其任意组合所组成的群组中选择。
19.根据权利要求1所述的方法，其中沉积步骤包括沉积铜，接合步骤包括在所述微电子元件与所述第二元件间加热及加压，使得覆盖所述微电子元件的铜与覆盖所述第二元件的铜熔合在一起。
20.根据权利要求19所述的方法，进一步包括在覆盖所述微电子元件和所述第二元件中的至少一个元件的所述铜上沉积金层，且接合步骤包括加热金至金扩散入铜内的温度。
21.根据权利要求1所述的方法，其中沉积第一金属层和第二金属层的步骤包括沉积基底金属和覆盖所述基底金属的金层，其中接合步骤包括对所述微电子元件和所述第二元件加热并加压，直至所述第一金属层与所述第二金属层熔合在一起。
22.微电子组件，包括：
微电子元件，具有主表面和在所述主表面暴露的介电层及至少一个结合垫，所述微电子元件包含复数个有源电路元件；
第二元件，具有小于10ppm/℃的热膨胀系数，所述第二元件具有主表面和在其主表面暴露的至少一个结合垫及介电层；
第一金属层，覆盖所述微电子元件的至少一个结合垫和介电层，其中在所述第一金属层内，所述至少一个结合垫与所述介电层之间形成间隙；
第二金属层，覆盖所述第二元件的至少一个结合垫和介电层；及
其中所述第一金属层和所述第二金属层的覆盖所述介电层的第一部分接合在一起，且所述第一金属层和所述第二金属层的覆盖所述至少一个结合垫并与所述第一部分分开的第二部分接合在一起，从而使所述微电子元件与所述第二元件机械连接及电连接。
23.根据权利要求22所述的组件，其中所述微电子元件为芯片，且所述第二元件具有与所述芯片面积相同的面积。
24.根据权利要求22所述的组件，其中所述间隙足够大，以提供足以补偿所述第一金属层的顶面的共面度的差异总量与所述第二金属层的顶面的共面度的差异总量之和的缓冲容积，所述第一金属层覆盖所述微电子元件的至少一个结合垫和介电层，所述第二金属层覆盖所述第二元件的至少一个结合垫和介电层。
25.根据权利要求22所述的组件，其中所述第一金属层和所述第二金属层中至少一个包括放热的且通过加热而热激活的至少一部分。
26.根据权利要求22所述的组件，其中所述第二元件为包含复数个有源电路元件的微电子元件。
27.根据权利要求26所述的组件，其中所述微电子元件和所述第二元件中的至少一个元件包括与该元件的至少一个结合垫电连接的贯通硅通路，其从该元件的主表面朝远离该主表面的该元件的第二表面延伸。
28.根据权利要求27所述的组件，其中贯通硅通路贯穿所述微电子元件及所述第二元件而延伸，且与所述微电子元件的结合垫及所述第二元件的结合垫电连接。
29.根据权利要求26所述的组件，其中所述微电子元件和所述第二元件中的每个元件的至少一个结合垫包括以复数排对齐的一系列结合垫。
30.根据权利要求26所述的组件，其中所述微电子元件和所述第二元件中的每个元件的至少一个结合垫包括邻近该元件外周而排列的复数个结合垫，且所述介电层覆盖所述主表面的中心区域。
31.根据权利要求26所述的组件，其中在所述第二金属层内，至少一个结合垫与所述介电层之间形成间隙。
32.根据权利要求22所述的组件，其中所述微电子元件和所述第二元件中的至少一个元件的所述介电层为可压缩的，以吸收任何尺寸公差。
33.根据权利要求22所述的组件，其中所述至少一个结合垫高出所述微电子元件的主表面的高度与所述介电层高出所述微电子元件主表面的高度不同。
34.根据权利要求22所述的组件，其中至少一个金属层包括回流金属，所述回流金属从焊料、铟、金及其任意组合所组成的群组中选择。
35.根据权利要求34所述的组件，其中所述第一金属层和所述第二金属层中每个都包括可被所述回流金属润湿的金属层，其中所述回流金属覆盖所述可润湿的金属层。
36.根据权利要求34所述的组件，其中所述焊料为锡。
37.根据权利要求22所述的组件，其中所述第一金属层和所述第二金属层包含铜。
38.根据权利要求37所述的组件，进一步包括覆盖所述第一金属层和所述第二金属层中至少一个的金层。
39.根据权利要求22所述的组件，其中所述第一金属层和所述第二金属层不直接覆盖所述微电子元件和所述第二元件的相应主表面。
40.微电子系统，包括：根据权利要求22所述的组件，及与所述组件电连接的一个或多个其他电子元器件。
41.根据权利要求40所述的微电子系统，进一步包括外壳，所述组件及所述其他电子元器件安装至所述外壳。
42.微电子组件，包括：
微电子元件，具有主表面和在该主表面暴露的介电层；及
第二元件，具有主表面和在所述第二元件的主表面暴露的介电层；
所述微电子元件和所述第二元件的主表面相互面对，复数个金属元件位于所述介电层之间，所述金属元件与所述微电子元件电隔离，
其中所述金属元件使所述微电子元件与所述第二元件相互接合；
其中在所述微电子元件和所述第二元件当中的每个元件上，沿所述主表面在每个金属元件与所述介电层的相邻部分之间形成间隙，
其中所述间隙足够大，以提供使得可回流金属能从所述微电子元件和所述第二元件的介电层之间流入的缓冲容积，所述缓冲容积足以补偿覆盖所述微电子元件的主表面的所述金属元件的顶面与所述介电层的顶面的共面度的差异总量和覆盖所述第二元件的主表面的所述金属元件的顶面与所述介电层的顶面的共面度的差异总量之和。
43.根据权利要求42所述的组件，其中所述第二元件具有小于10ppm/℃的热膨胀系数。
44.根据权利要求42所述的组件，其中所述微电子元件包含复数个有源电路元件。
45.根据权利要求44所述的组件，其中所述第二元件为微电子元件，包含复数个有源电路元件，且包括在其主表面暴露的至少一个结合垫。
46.根据权利要求42所述的组件，其中所述微电子元件为芯片，所述第二元件具有与所述芯片的面积相同的面积。
47.根据权利要求42所述的组件，其中所述微电子元件和所述第二元件中的至少一个元件的所述介电层为可压缩的，以吸收任何尺寸公差。
48.微电子系统，包括：根据权利要求42所述的组件，及与所述组件电连接的一个或多个其他电子元器件。
49.根据权利要求48所述的微电子系统，进一步包括外壳，所述组件及所述其他电子元器件安装至所述外壳。
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