WO2016159320A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2016159320A1
WO2016159320A1 PCT/JP2016/060834 JP2016060834W WO2016159320A1 WO 2016159320 A1 WO2016159320 A1 WO 2016159320A1 JP 2016060834 W JP2016060834 W JP 2016060834W WO 2016159320 A1 WO2016159320 A1 WO 2016159320A1
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Prior art keywords
region
hole
insulating layer
wiring
opening
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PCT/JP2016/060834
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English (en)
French (fr)
Inventor
暢郎 細川
直 井上
柴山　勝己
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浜松ホトニクス株式会社
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Application filed by 浜松ホトニクス株式会社 filed Critical 浜松ホトニクス株式会社
Priority to JP2017510234A priority Critical patent/JP6742988B2/ja
Priority to KR1020177024220A priority patent/KR102605400B1/ko
Priority to EP16773200.7A priority patent/EP3279925B1/en
Priority to CN201680018889.3A priority patent/CN107360729B/zh
Priority to US15/562,004 priority patent/US10615220B2/en
Publication of WO2016159320A1 publication Critical patent/WO2016159320A1/ja

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Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • electrical connection may be performed between a front surface side and a back surface side of a semiconductor substrate through a through-hole formed in the semiconductor substrate (for example, Patent Documents). 1).
  • the electrical connection through the through hole in the semiconductor substrate may become fragile with the miniaturization and high integration.
  • an object of the present invention is to provide a semiconductor device capable of ensuring electrical connection through a through hole in a semiconductor substrate, and a method for manufacturing such a semiconductor device.
  • a semiconductor device includes a semiconductor substrate having a first surface and a second surface facing each other, and a through-hole extending from the first surface to the second surface, and the first surface, A part of the first wiring located on the first opening on the first surface side of the through hole, the inner surface and the second surface of the through hole, and continuous through the second opening on the second surface side of the through hole And an insulating layer provided on the surface of the insulating layer, and a second wiring electrically connected to the first wiring in the opening on the first surface side of the insulating layer, the surface of the insulating layer having a through hole A tapered first region that extends to the first opening on the inner side and extends from the first surface toward the second surface, and a taper that reaches the second opening on the inner side of the through hole and extends from the first surface to the second surface.
  • Second region a third region facing the second surface outside the through hole, and the first region
  • a fourth region curved to continuously connect the second region
  • a fifth region curved to continuously connect the second region and the third region, the average of the second region
  • the inclination angle is smaller than the average inclination angle of the first region and smaller than the average inclination angle of the inner surface of the through hole.
  • the first region reaching the first opening of the through hole and the second region reaching the second opening of the through hole are directed from the first surface of the semiconductor substrate to the second surface.
  • This is a tapered region that spreads out.
  • region is smaller than the average inclination angle of the inner surface of a through-hole.
  • the second region can be formed easily and reliably because the slope of the second region becomes gentler than when the insulating layer is formed with a uniform thickness along the inner surface of the through hole. it can. Furthermore, since the second wiring can be formed without depending on the shape of the inner surface of the through hole, for example, even when a sharp portion remains on the inner surface of the through hole, the second wiring caused by such a portion is left. Disconnection of the two wirings can be prevented.
  • the average inclination angle of the second region is smaller than the average inclination angle of the first region.
  • the average inclination angle of the first region reaching the first opening of the through hole is larger than the average inclination angle of the second region.
  • the average inclination angle of the inner surface of the through hole is such that the inner surface of the through hole (if the inner surface of the through hole is a curved surface such as a cylindrical surface) is orthogonal to the first surface of the semiconductor substrate, The case where the inner surface of the through hole forms an angle of 90 ° with respect to the first surface is also included.
  • the average inclination angle of the first region may be closer to the average inclination angle of the inner surface of the through hole than the average inclination angle of the second region.
  • the average thickness of the insulating layer provided on the inner surface of the through hole may be larger than the average thickness of the insulating layer provided on the second surface.
  • the first region is 2 of the sum of the thickness of the semiconductor substrate and the average thickness of the insulating layer provided on the second surface among the insulating layers provided on the inner surface of the through hole. It may be the surface of a portion having a height of / 3 or less. Accordingly, the first region and the second region can be gently connected on the surface of the insulating layer, and disconnection of the second wiring at the boundary between the first region and the second region can be reliably prevented.
  • the first region is one of the sum of the thickness of the semiconductor substrate and the average thickness of the insulating layer provided on the second surface among the insulating layers provided on the inner surface of the through hole.
  • the surface of the part which has the height below / 2 may be sufficient.
  • the first region and the second region can be more gently connected on the surface of the insulating layer, and the disconnection of the second wiring at the boundary between the first region and the second region can be more reliably prevented. it can.
  • the fourth region may be a region having a maximum curvature convex on the side opposite to the inner surface of the through hole.
  • Such a shape of the insulating layer is particularly effective in ensuring electrical connection through the through hole in the semiconductor substrate.
  • the inner surface of the through hole may be a tapered surface extending from the first surface toward the second surface, or the inner surface of the through hole (the inner surface of the through hole may be In the case of a curved surface such as a cylindrical surface, the tangent plane of the curved surface) may be a surface orthogonal to the first surface and the second surface.
  • the electrical connection through the through hole in the semiconductor substrate can be ensured.
  • the insulating layer may be made of a resin.
  • the insulating layer having the shape as described above can be easily and reliably formed.
  • a method for manufacturing a semiconductor device is the above-described method for manufacturing a semiconductor device, wherein a first wiring is provided on a first surface of a semiconductor substrate having a first surface and a second surface facing each other. Forming a through hole from the first surface to the second surface in the semiconductor substrate, exposing a part of the first wiring to the first opening on the first surface side of the through hole, and a through hole A third step of providing a continuous insulating layer on the inner surface and the second surface through the second opening on the second surface side of the through hole; and forming a contact hole in the insulating layer, and opening the first surface side of the insulating layer And a fourth step of exposing a part of the first wiring, and a second wiring is provided on the surface of the insulating layer, and the first wiring and the second wiring are electrically connected in the opening on the first surface side of the insulating layer. And a fifth step.
  • an insulating layer is formed on the inner surface and the second surface of the through hole by performing a dip coating method using a resin material having a viscosity of 10 cp or more. It may be provided. Thereby, the insulating layer having the shape as described above can be obtained easily and reliably.
  • an insulating layer is provided on the inner surface and the second surface of the through hole using a positive resin material, and in the fourth step, the insulating layer is contacted.
  • a contact hole may be formed in the insulating layer by exposing and developing a portion corresponding to the hole.
  • the present invention it is possible to provide a semiconductor device capable of ensuring electrical connection through a through hole in a semiconductor substrate, and a method for manufacturing such a semiconductor device.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
  • 2 is a cross-sectional view of the through hole and its peripheral portion of the semiconductor device of FIG. 3A and 3B are cross-sectional views for explaining a plurality of steps in the method for manufacturing the semiconductor device of FIG. 4A and 4B are cross-sectional views for explaining a plurality of steps in the method for manufacturing the semiconductor device of FIG. 5A and 5B are cross-sectional views for explaining a plurality of steps in the method for manufacturing the semiconductor device of FIG.
  • FIG. 6 is a partial cross-sectional view of a modification of the semiconductor device of FIG.
  • FIG. 7 is a partial cross-sectional view of a modification of the semiconductor device of FIG.
  • FIG. 8 is a partial cross-sectional view of a modification of the semiconductor device of FIG.
  • FIG. 9 is a cross-sectional view of a modification of the through hole and its peripheral portion of the semiconductor device of FIG.
  • the semiconductor device 1 includes a semiconductor substrate 2 having a first surface 2a and a second surface 2b facing each other.
  • the semiconductor device 1 is an optical device such as a silicon photodiode.
  • a p-type region 2c in which p-type impurities are selectively diffused is provided in a predetermined region on the first surface 2a side in a semiconductor substrate 2 made of, for example, n-type silicon.
  • a first wiring 3 made of, for example, aluminum is provided via an oxide film 4.
  • An opening 4 a is formed in a portion of the oxide film 4 corresponding to the pad portion 3 a of the first wiring 3.
  • An opening 4b is formed in a portion of oxide film 4 corresponding to the end of p-type region 2c.
  • the first wiring 3 is electrically connected to the p-type region 2c through the opening 4b.
  • an insulating film made of another insulating material such as SiN may be provided.
  • a light transmission substrate 5 made of a light transmission material such as glass is disposed on the first surface 2 a of the semiconductor substrate 2.
  • the semiconductor substrate 2 and the light transmission substrate 5 are optically and physically connected by an adhesive layer 6 made of an optical adhesive.
  • the thickness of the semiconductor substrate 2 is smaller (thin) than the thickness of the light transmission substrate 5.
  • the thickness of the semiconductor substrate 2 is about several tens of ⁇ m, and the thickness of the light transmission substrate 5 is about several hundreds of ⁇ m.
  • a through hole 7 extending from the first surface 2a to the second surface 2b is formed.
  • the first opening 7 a of the through hole 7 is located on the first surface 2 a of the semiconductor substrate 2
  • the second opening 7 b of the through hole 7 is located on the second surface 2 b of the semiconductor substrate 2.
  • the first opening 7 a is continuous with the opening 4 a of the oxide film 4 and is covered with the pad portion 3 a of the first wiring 3.
  • the inner surface 7c of the through hole 7 is a tapered surface that spreads from the first surface 2a toward the second surface 2b.
  • the through hole 7 is formed in a quadrangular pyramid shape that widens from the first surface 2a toward the second surface 2b.
  • the edge of the first opening 7a of the through hole 7 and the edge of the opening 4a of the oxide film 4 do not have to coincide with each other.
  • the edge of the opening 4 a of the oxide film 4 may be located inside the edge of the first opening 7 a of the through hole 7.
  • the aspect ratio of the through hole 7 is 0.2-10.
  • the aspect ratio refers to the depth of the through hole 7 (distance between the first opening 7a and the second opening 7b) and the width of the second opening 7b (when the second opening 7b is rectangular, between the opposite sides of the second opening 7b). Or the diameter of the second opening 7b when the second opening 7b is circular).
  • the depth of the through hole 7 is 30 ⁇ m
  • the width of the second opening 7b is 130 ⁇ m.
  • the aspect ratio is 0.23.
  • An insulating layer 10 is provided on the inner surface 7 c of the through hole 7 and the second surface 2 b of the semiconductor substrate 2.
  • the insulating layer 10 is continuous through the second opening 7 b of the through hole 7.
  • the insulating layer 10 reaches the pad portion 3a of the first wiring 3 through the opening 4a of the oxide film 4 inside the through hole 7, and has an opening 10a on the first surface 2a side of the semiconductor substrate 2. .
  • a second wiring 8 made of, for example, aluminum is provided on the surface 10b of the insulating layer 10 (the surface opposite to the inner surface 7c of the through hole 7 and the second surface 2b of the semiconductor substrate 2).
  • the second wiring 8 is electrically connected to the pad portion 3 a of the first wiring 3 in the opening 10 a of the insulating layer 10.
  • a third wiring 22 made of, for example, aluminum is provided on the surface 10b of the insulating layer 10 (the surface opposite to the second surface 2b of the semiconductor substrate 2).
  • the third wiring 22 is electrically connected to the second surface 2 b of the semiconductor substrate 2 through the opening 10 c formed in the insulating layer 10.
  • the second wiring 8 and the third wiring 22 are covered with a resin protective layer 21.
  • a shallow concave portion 21 a having a smooth inner surface is formed in a portion corresponding to the through hole 7 in the resin protective layer 21.
  • An opening 21b for exposing the pad portion 8a is formed in a portion of the resin protective layer 21 corresponding to the pad portion 8a of the second wiring 8.
  • An opening 21c that exposes the pad portion 22a is formed in a portion of the resin protective layer 21 corresponding to the pad portion 22a of the third wiring 22.
  • an extraction electrode 9 that is a bump electrode is disposed in the opening 21 b of the resin protective layer 21, an extraction electrode 9 that is a bump electrode is disposed. The extraction electrode 9 is electrically connected to the pad portion 8 a of the second wiring 8.
  • An extraction electrode 23 that is a bump electrode is disposed in the opening 21 c of the resin protective layer 21.
  • the extraction electrode 23 is electrically connected to the pad portion 22 a of the third wiring 22.
  • the semiconductor device 1 is mounted on a circuit board via an extraction electrode 9 and an extraction electrode 23, and the extraction electrode 9 and the extraction electrode 23 function as an anode electrode and a cathode electrode, respectively.
  • a protective layer for example, an oxide film or a nitride film
  • the thickness of the resin protective layer 21 may be approximately the same as the thickness of the insulating layer 10 or may be smaller than the thickness of the insulating layer 10. In particular, if the thickness of the resin protective layer 21 is approximately the same as the thickness of the insulating layer 10, the stress acting on the second wiring 8 and the third wiring 22 can be reduced.
  • the above-described insulating layer 10 will be described in more detail with reference to FIG. In FIG. 2, the light transmission substrate 5, the adhesive layer 6, the extraction electrode 9, and the resin protective layer 21 are omitted.
  • the surface 10 b of the insulating layer 10 includes a first region 11 that reaches the first opening 7 a inside the through hole 7, and a second region 12 that reaches the second opening 7 b inside the through hole 7. And a third region 13 facing the second surface 2b of the semiconductor substrate 2 outside the through hole 7.
  • the first region 11 is a tapered region extending from the first surface 2a of the semiconductor substrate 2 toward the second surface 2b.
  • the first region 11 has an average inclination angle ⁇ .
  • the average inclination angle ⁇ of the first region 11 is an intersection line between the plane and the first region 11 when attention is paid to a region on one side of the center line CL with respect to the plane including the center line CL of the through hole 7. Is an average value of angles formed with respect to the first surface 2a.
  • the intersecting line is a straight line
  • an angle formed by the straight line and the first surface 2 a is an average inclination angle ⁇ of the first region 11.
  • the average value of the angles formed by the tangent line of the curve and the first surface 2a is the average inclination angle ⁇ of the first region 11.
  • the average inclination angle ⁇ of the first region 11 is larger than 0 ° and smaller than 90 °.
  • the second region 12 is a tapered region extending from the first surface 2a of the semiconductor substrate 2 toward the second surface 2b.
  • the second region 12 has an average inclination angle ⁇ .
  • the average inclination angle ⁇ of the second region 12 is an intersection line between the plane and the second region 12 when attention is paid to a region on one side of the center line CL with respect to the plane including the center line CL of the through hole 7. Is an average value of angles formed with respect to the first surface 2a.
  • the intersecting line is a straight line
  • an angle formed by the straight line and the first surface 2 a is an average inclination angle ⁇ of the second region 12.
  • the average value of the angle formed between the tangent line of the curve and the first surface 2 a is the average inclination angle ⁇ of the second region 12.
  • the average inclination angle ⁇ of the second region 12 is greater than 0 ° and smaller than 90 °.
  • the average inclination angle ⁇ of the second region 12 is smaller than the average inclination angle ⁇ of the first region 11. That is, the second region 12 is a region having a gentler slope than the first region 11. Further, the average inclination angle ⁇ of the second region 12 is smaller than the average inclination angle ⁇ of the inner surface 7 c of the through hole 7. That is, the second region 12 is a region having a gentler slope than the inner surface 7 c of the through hole 7. In the present embodiment, the average inclination angle ⁇ of the first region 11 is closer to the average inclination angle ⁇ of the inner surface 7 c of the through hole 7 than the average inclination angle ⁇ of the second region 12.
  • the average inclination angle ⁇ of the inner surface 7c of the through hole 7 is an intersection line between the plane and the inner surface 7c when attention is paid to a region on one side of the center line CL with respect to the plane including the center line CL of the through hole 7. Is an average value of angles formed with respect to the first surface 2a.
  • the intersecting line is a straight line
  • an angle formed by the straight line and the first surface 2a is an average inclination angle ⁇ of the inner surface 7c of the through hole 7.
  • the average value of the angle formed between the tangent line of the curve and the first surface 2a is the average inclination angle ⁇ of the inner surface 7c of the through hole 7.
  • the surface 10b of the insulating layer 10 includes a fourth region 14 having a convex maximum curvature opposite to the inner surface 7c of the through hole 7, a fifth region 15 along the edge of the second opening 7b of the through hole 7, Is further included.
  • the maximum curvature convex on the side opposite to the inner surface 7c of the through hole 7 is the plane and the surface 10b when attention is paid to a region on one side of the center line CL with respect to the plane including the center line CL of the through hole 7. Is the maximum value of the curvature of the portion curved in a convex shape on the opposite side to the inner surface 7c of the through hole 7.
  • the first region 11 is located on the first opening 7 a side of the through hole 7 from the fourth region 14 (center line CL of the through hole 7) of the surface 10 b of the insulating layer 10 provided on the inner surface 7 c of the through hole 7. In the direction parallel to the first opening 7a side).
  • the second region 12 is on the second opening 7b side of the through hole 7 from the surface 10b of the insulating layer 10 provided on the inner surface 7c of the through hole 7 (parallel to the center line CL of the through hole 7). This is a region (that is, the region between the fourth region 14 and the fifth region 15) on the second opening 7b side in a certain direction.
  • the fourth region 14 is curving so that the 1st area
  • the first region 11 extends to the second surface 2b side of the semiconductor substrate 2
  • the second region 12 extends to the first surface 2a side of the semiconductor substrate 2.
  • the first region 11 and the second region 12 form intersection lines (corners, bent portions).
  • the fourth region 14 corresponds to a curved surface formed when the intersection line (corner, bent portion) is chamfered.
  • the fourth region 14 When the fourth region 14 focuses on a region on one side of the center line CL with respect to the plane including the center line CL of the through hole 7, the fourth region 14 corresponds to the first region 11 among the intersecting lines between the plane and the surface 10 b. Between the corresponding portion and the portion corresponding to the second region 12, it is a portion that curves in a convex shape on the opposite side to the inner surface 7c of the through hole 7.
  • the fifth region 15 is curved so as to continuously connect the second region 12 and the third region 13. That is, the fifth region 15 is a rounded curved surface, and smoothly connects the second region 12 and the third region 13.
  • the second region 12 extends to the second surface 2b side of the semiconductor substrate 2, and the third region 13 extends toward the center line CL of the through hole 7.
  • the second region 12 and the third region 13 form intersection lines (corners, bent portions, etc.).
  • the fifth region 15 corresponds to a curved surface formed when the intersection line (corner, bent portion, etc.) is chamfered.
  • the fifth region 15 When the fifth region 15 focuses on a region on one side of the center line CL with respect to the plane including the center line CL of the through-hole 7, the fifth region 15 corresponds to the second region 12 among the intersection lines between the plane and the surface 10b. Between the corresponding part and the part corresponding to the third region 13, it is a part that curves in a convex shape on the opposite side to the edge of the second opening 7b of the through hole 7.
  • the first region 11, the fourth region 14, and the fifth region 15 are curved surfaces that are convexly curved on the side opposite to the inner surface 7c of the through hole 7.
  • the second region 12 is a curved surface convexly curved toward the inner surface 7c side of the through hole 7 (that is, a curved surface curved concavely when viewed from the side opposite to the inner surface 7c of the through hole 7).
  • the third region 13 is a plane that is substantially parallel to the second surface 2 b of the semiconductor substrate 2.
  • the fourth region 14 is curved so as to continuously connect the first region 11 and the second region 12, and the fifth region 15 continues the second region 12 and the third region 13.
  • the surface 10b of the insulating layer 10 is curved so as to be connected to each other, there is no discontinuous portion such as a continuous surface (intersection line (corner, bent portion, etc.) between the surfaces). , 12, 13, 14, and 15 are smoothly connected surfaces).
  • the average thickness of the insulating layer 10 provided on the inner surface 7 c of the through hole 7 is larger than the average thickness of the insulating layer 10 provided on the second surface 2 b of the semiconductor substrate 2.
  • the average thickness of the insulating layer 10 provided on the inner surface 7c of the through hole 7 is the average value of the thickness of the insulating layer 10 in the direction perpendicular to the inner surface 7c.
  • the average thickness of the insulating layer 10 provided on the second surface 2b of the semiconductor substrate 2 is the average value of the thickness of the insulating layer 10 in the direction perpendicular to the second surface 2b.
  • the average thickness of the portion corresponding to the first region 11 in the insulating layer 10 corresponds to the second region 12 in the insulating layer 10. Greater than the average thickness of the part.
  • the average thickness of the portion corresponding to the first region 11 in the insulating layer 10 is the first region 11 and the through hole 7 in the direction. It is the average value of the distance to the inner surface 7c.
  • the average thickness of the portion corresponding to the second region 12 in the insulating layer 10 is the second region 12 and the through hole 7 in the direction. It is the average value of the distance to the inner surface 7c.
  • the first region 11 is a surface of a portion having a height H from the first surface 2 a of the semiconductor substrate 2 in the insulating layer 10 provided on the inner surface 7 c of the through hole 7.
  • the height H is the sum D of the thickness of the semiconductor substrate 2 (that is, the distance between the first surface 2a and the second surface 2b) and the average thickness of the insulating layer 10 provided on the second surface 2b of the semiconductor substrate 2. Of 1/2 or less.
  • the surface P passing through the edge of the opening 10 a of the insulating layer 10 and the edge of the second opening 7 b of the through hole 7 is a boundary surface, and the portion P 1 on the inner surface 7 c side of the through hole 7 with respect to the surface S, and When attention is paid to the portion P2 opposite to the inner surface 7c of the through hole 7 with respect to the surface S, the volume of the portion P1 is larger than the volume of the portion P2.
  • the area of the triangle T ⁇ b> 1 is larger than the area of the triangle T ⁇ b> 2.
  • the triangle T1 is a plane including the center line CL of the through hole 7 (that is, in the cross section of FIG. 2), the edge of the first opening 7a of the through hole 7, the edge of the second opening 7b of the through hole 7, and the insulating layer. It is a triangle having the vertex of the edge of ten openings 10a.
  • the triangle T2 is a plane including the center line CL of the through hole 7 (that is, in the cross section of FIG. 2), the edge of the opening 10a of the insulating layer 10, the edge of the second opening 7b of the through hole 7, and the fourth region 14. It is a triangle with the apex of.
  • Reference numeral 12 denotes a tapered region extending from the first surface 2a of the semiconductor substrate 2 toward the second surface 2b.
  • the average inclination angle of the second region 12 is smaller than the average inclination angle of the inner surface 7 c of the through hole 7.
  • the second wiring 8 can be easily and reliably formed. Can be formed.
  • the second wiring 8 can be formed without depending on the shape of the inner surface 7c of the through hole 7, for example, even when a sharp portion remains on the inner surface 7c of the through hole 7, such a case The disconnection of the second wiring 8 due to the portion can be prevented.
  • the average inclination angle of the second region 12 is smaller than the average inclination angle of the first region 11.
  • the average inclination angle of the first region 11 reaching the first opening 7 a of the through hole 7 is larger than the average inclination angle of the second region 12.
  • the fourth region 14 is curved so as to continuously connect the first region 11 and the second region 12, and the fifth region 15 is connected to the second region 12. Curved so as to continuously connect the third region 13. Therefore, disconnection of the second wiring 8 in the entire region of the surface 10b of the insulating layer 10 is prevented during and after manufacture. In particular, after the manufacture, stress concentration is alleviated in the entire region of the surface 10 b of the insulating layer 10, which is effective in preventing disconnection of the second wiring 8. As described above, according to the semiconductor device 1, electrical connection through the through hole 7 in the semiconductor substrate 2 can be ensured.
  • the surface 10 b of the insulating layer 10 does not have a discontinuous portion such as a continuous surface (intersection line (corner, bent portion, etc.) between the surfaces), and each region 11, 12, 13, 14, 15 is a smoothly connected surface). Thereby, stress concentration can be eased and disconnection of the second wiring 8 can be prevented.
  • the average inclination angle of the first region 11 is closer to the average inclination angle of the inner surface 7 c of the through hole 7 than the average inclination angle of the second region 12.
  • an opening 10a having a sufficient width to expose the pad portion 3a of the first wiring 3 can be obtained.
  • the opening 10a portion of the insulating layer 10 can be obtained at the time of manufacturing and after the manufacturing. Disconnection of the first wiring 3 and the second wiring 8 can be prevented more reliably.
  • the average thickness of the insulating layer 10 provided on the inner surface 7c of the through hole 7 is larger than the average thickness of the insulating layer 10 provided on the second surface 2b.
  • the insulating layer 10 provided on the inner surface 7c of the through hole 7 functions as a reinforcing layer, so that the strength of the peripheral portion of the through hole 7 can be sufficiently ensured. it can.
  • the average inclination angle of the first region 11 and the average inclination angle of the second region 12 can be set to desired angles, and the surface 10b is a continuous surface (intersection line (angle, bent portion, etc.) between the surfaces).
  • the insulating layer 10 in which the discontinuous portions are not present and the regions 11, 12, 13, 14, and 15 are smoothly connected.
  • the insulating layer 10 is formed with a uniform thickness along the inner surface 7c of the through hole 7, it is impossible to obtain the insulating layer 10 having a continuous surface 10b.
  • the average thickness of the portion of the insulating layer 10 corresponding to the first region 11 in the direction parallel to the first surface 2 a and the second surface 2 b of the semiconductor substrate 2 is the second of the insulating layer 10. It is larger than the average thickness of the portion corresponding to the region 12.
  • the overhang or the like is covered with the insulating layer 10 and is a curved surface curved in a convex shape.
  • the second wiring 8 is provided in the region 15. Thereby, disconnection of the 2nd wiring 8 in the 2nd opening 7b part of penetration hole 7 can be prevented certainly.
  • the sum D of the thickness of the semiconductor substrate 2 and the average thickness of the insulating layer 10 provided on the second surface 2 b is not more than 1 ⁇ 2.
  • the surface of the portion having the height H is the first region 11.
  • the surface S passing through the edge of the opening 10 a of the insulating layer 10 and the edge of the second opening 7 b of the through hole 7 is defined as a boundary surface, which is on the inner surface 7 c side of the through hole 7.
  • the volume of the portion P1 is larger than the volume of the portion P2.
  • the area of the triangle T1 is larger than the area of the triangle T2.
  • the first opening is larger than the fourth region 14 having the maximum curvature convex on the side opposite to the inner surface 7 c of the through hole 7 out of the surface 10 b of the insulating layer 10 provided on the inner surface 7 c of the through hole 7.
  • the region on the 7a side is the first region 11, and the region on the second opening 7b side than the fourth region 14 is the second region 12.
  • Such a shape of the insulating layer 10 is particularly effective in ensuring electrical connection through the through hole 7 in the semiconductor substrate 2.
  • the inner surface 7c of the through hole 7 is a tapered surface that spreads from the first surface 2a toward the second surface 2b. Also in this case, the electrical connection through the through hole 7 in the semiconductor substrate 2 can be ensured.
  • the insulating layer 10 is made of resin. Thereby, the insulating layer 10 having the shape as described above can be easily and reliably formed.
  • the semiconductor substrate 2 is prepared, and a device is formed on the first surface 2a of the semiconductor substrate 2 (that is, the oxide film 4, the first wiring 3 and the like are provided on the first surface 2a) (first step). Then, the light transmission substrate 5 is attached to the first surface 2 a of the semiconductor substrate 2 via the adhesive layer 6.
  • a through hole 7 is formed in the semiconductor substrate 2 by anisotropic wet etching, and further, as shown in FIG. 3B, the oxide film 4 Then, a portion corresponding to the pad portion 3 a of the first wiring 3 is removed, and an opening 4 a is formed in the oxide film 4. Thereby, the pad portion 3a of the first wiring 3 is exposed to the first opening 7a of the through hole 7 (second step).
  • the opening 4 a is formed in the oxide film 4 so that the edge of the first opening 7 a of the through hole 7 and the edge of the opening 4 a of the oxide film 4 coincide with each other.
  • the opening 4a may be formed in the oxide film 4 so that the edge of the opening 4a of the oxide film 4 is located inside the edge of the first opening 7a of the through hole 7.
  • a positive resin material having a viscosity of 10 cp or more is prepared, and the dip coating method using the resin material (the object is immersed in the resin paint, and the object is lifted from the resin paint, 4), the insulating layer 10 is provided on the inner surface 7c of the through hole 7 and the second surface 2b of the semiconductor substrate 2 (first method). 3 steps). As a result, a recess 17 having an inner surface following the second region 12, the third region 13, and the fifth region 15 is formed in the insulating layer 10.
  • a resin material a phenol resin, a polyimide resin, an epoxy resin etc. can be used, for example.
  • a mask 30 is disposed on the insulating layer 10 provided on the second surface 2 b of the semiconductor substrate 2.
  • the mask 30 has a light transmission part 31 at a position facing the pad part 3 a of the first wiring 3, and has a light shielding part 32 around the light transmission part 31.
  • the portion corresponding to the contact hole 16 in the insulating layer 10 is irradiated with light through the light transmitting portion 31 of the mask 30 to expose the portion.
  • the contact hole 16 is formed in the insulating layer 10 by developing the portion corresponding to the contact hole 16 in the insulating layer 10. Thereby, the pad portion 3a of the first wiring 3 is exposed in the opening 10a of the insulating layer 10 (fourth step).
  • an ashing process or the like may be used together.
  • a gap is formed by the concave portion 17 formed in the insulating layer 10 between the light transmitting portion 31 of the mask 30 and the portion corresponding to the contact hole 16 in the insulating layer 10.
  • the light is diffracted and applied to the insulating layer 10.
  • a tapered first region 11 extending from the first surface 2a of the semiconductor substrate 2 toward the second surface 2b and a contact hole 16 having an inner surface following the second region 12 are formed.
  • the second wiring 8 is provided on the surface 10 b of the insulating layer 10 by performing sputtering using, for example, aluminum, and the second wiring 8 is formed in the opening 10 a of the insulating layer 10.
  • the first wiring 3 and the second wiring 8 are electrically connected (fifth step).
  • the contact hole 16 has an inner surface that follows the tapered first region 11 extending from the first surface 2a of the semiconductor substrate 2 toward the second surface 2b, a metal film is also formed on the inner surface.
  • the first wiring 3 and the second wiring 8 are reliably connected in the opening 10 a of the insulating layer 10.
  • the second wiring 8 is covered with the resin protective layer 21 as shown in FIG.
  • the extraction electrode 9 is arranged on the pad portion 8a of the second wiring 8 that is not covered with the resin protective layer 21, and the semiconductor device 1 described above is obtained.
  • the semiconductor device 1 in which the electrical connection through the through hole 7 in the semiconductor substrate 2 is ensured can be efficiently manufactured.
  • the insulating layer 10 is provided on the inner surface 7 c of the through hole 7 and the second surface 2 b of the semiconductor substrate 2 by performing a dip coating method using a resin material having a viscosity of 10 cp or more. .
  • the insulating layer 10 having the shape as described above can be obtained easily and reliably.
  • a resin material having a low viscosity for example, a resin material used for water repellent coating, such as a resin material having a viscosity of 1 cp or less
  • a resin material having a viscosity of 1 cp or less is generally used.
  • the insulating layer 10 is formed with a substantially uniform thickness along the inner surface 7 c of the through hole 7. Therefore, in the method for manufacturing the semiconductor device 1, by performing the dip coating method using a resin material having a viscosity of 10 cp or more, the insulating layer 10 having the shape as described above can be obtained easily and reliably. it can.
  • the insulating layer 10 is provided on the inner surface 7 c of the through hole 7 and the second surface 2 b of the semiconductor substrate 2 using a positive resin material. Then, the contact hole 16 is formed in the insulating layer 10 by exposing and developing a portion corresponding to the contact hole 16 in the insulating layer 10. Thereby, the insulating layer 10 having the shape as described above can be obtained easily and reliably. At the time of exposure and development, the concave portion 17 formed in the insulating layer 10 reduces the thickness of the portion corresponding to the contact hole 16 in the insulating layer 10 (that is, corresponds to the contact hole 16).
  • the portion is a portion of the insulating layer 10 having a height H equal to or less than 1 ⁇ 2 of the sum D of the thickness of the semiconductor substrate 2 and the average thickness of the insulating layer 10 provided on the second surface 2b).
  • the contact hole 16 having a desired shape can be obtained easily and reliably.
  • the dip coating method is performed in a state where the light transmission substrate 5 is attached to the semiconductor substrate 2. Therefore, the thinned semiconductor substrate 2 can be used.
  • the insulating layer 10 since the depth of the through hole 7 is reduced, even if the insulating layer 10 is thickened by a dip coating method using a resin material having a high viscosity of 10 cp or more, the insulating layer 10 is not formed.
  • the contact hole 16 can be easily and reliably formed.
  • the insulating layer 10 may be formed of an insulating material other than resin.
  • the 1st opening 7a of the through-hole 7 was covered with the pad part 3a of the 1st wiring 3, if a part of 1st wiring 3 is located on the 1st opening 7a, The first wiring 3 may not cover the entire region of the first opening 7a.
  • the average inclination angle of the first region 11 is closer to the average inclination angle of the inner surface 7 c of the through hole 7 than the average inclination angle of the second region 12.
  • the average inclination angle of the inner surface 7 c of the through hole 7 may be closer to the average inclination angle of the first region 11.
  • the light transmitting substrate 5 may not be attached to the first surface 2 a of the semiconductor substrate 2 via the adhesive layer 6.
  • an oxide film 18 is provided on the first surface 2 a so as to cover the first wiring 3.
  • the portion having the height H from the first surface 2 a in the insulating layer 10 functions as a reinforcing layer. This is particularly effective from the viewpoint of ensuring sufficient strength.
  • the extraction electrode 9 may be disposed inside the through hole 7 so as to protrude from the second surface 2b of the semiconductor substrate 2.
  • the light transmission substrate 5 may be attached to the first surface 2a of the semiconductor substrate 2 via the adhesive layer 6, or as shown in FIG. The light transmitting substrate 5 may not be attached to the first surface 2 a of the semiconductor substrate 2 via the adhesive layer 6.
  • the inner surface 7c of the through hole 7 (if the inner surface 7c of the through hole 7 is a curved surface such as a cylindrical surface), the first surface 2a and the second surface It may be a surface orthogonal to 2b. Also in this case, the electrical connection through the through hole 7 in the semiconductor substrate 2 can be ensured.
  • the aspect ratio of the through hole 7 is 0.2 to 10.
  • the depth of the through hole 7 is 40 ⁇ m
  • the width of the second opening 7 b is 30 ⁇ m. In this case, the aspect ratio is 1.3.
  • the through-hole 7 having a shape such as a columnar shape or a quadrangular prism shape is formed by, for example, dry etching.
  • the average inclination angle ⁇ of the second region 12 is smaller than the average inclination angle ⁇ of the first region 11, and the average inclination angle ⁇ of the inner surface 7c of the through hole 7 (in this case) Is smaller than 90 °). That is, the second region 12 is a region having a gentler slope than the first region 11 and a gentler slope than the inner surface 7 c of the through hole 7. The average inclination angle ⁇ of the first region 11 is closer to the average inclination angle ⁇ of the inner surface 7 c of the through hole 7 than the average inclination angle ⁇ of the second region 12.
  • disconnection of the second wiring 8 can be prevented, and an opening 10a having a sufficient width for exposing the pad portion 3a of the first wiring 3 can be obtained.
  • the surface 10b of the insulating layer 10 has no discontinuous portions such as continuous surfaces (intersection lines (corners, bent portions, etc.) between the surfaces), and the regions 11, 12, 13, 14, and 15 are smooth. Connected to the surface).
  • the volume of the portion P1 is larger than the volume of the portion P2.
  • the area of the triangle T ⁇ b> 1 is larger than the area of the triangle T ⁇ b> 2.
  • the average thickness of the portion corresponding to the first region 11 in the insulating layer 10 is the second region 12 in the insulating layer 10. It is larger than the average thickness of the corresponding part.
  • the first region 11 includes the thickness of the semiconductor substrate 2 and the average thickness of the insulating layer 10 provided on the second surface 2 b of the semiconductor substrate 2 in the insulating layer 10 provided on the inner surface 7 c of the through hole 7.
  • the surface 10b of the part which has the height H of 2/3 or less of the sum D may be sufficient (refer FIG. 9).
  • the first region 11 and the second region 12 are gently connected, and the second wiring 8 is disconnected at the boundary between the first region 11 and the second region 12. Can be reliably prevented.
  • the concave portion 17 formed in the insulating layer 10 reduces the thickness of the portion corresponding to the contact hole 16 in the insulating layer 10 (that is, corresponds to the contact hole 16).
  • the portion is a portion of the insulating layer 10 having a height H that is 2/3 or less of the sum D of the thickness of the semiconductor substrate 2 and the average thickness of the insulating layer 10 provided on the second surface 2b).
  • the contact hole 16 having a desired shape can be obtained easily and reliably.
  • the insulating layer 10 is provided on the inner surface 7 c of the through hole 7 and the second surface 2 b of the semiconductor substrate 2 by performing the dip coating method. It is not limited.
  • the insulating layer 10 is provided on the inner surface 7c of the through hole 7 and the second surface 2b of the semiconductor substrate 2 by performing other methods such as a laminating method using a resin sheet and a spin coating method using a resin paint. May be.
  • the insulating layer 10 is provided on the inner surface 7 c of the through hole 7 and the second surface 2 b of the semiconductor substrate 2 using a positive resin material, and the contact hole 16 is formed in the insulating layer 10.
  • the contact hole 16 was formed in the insulating layer 10 by exposing and developing the corresponding part, this invention is not limited to this.
  • the insulating layer 10 may be provided on the inner surface 7 c of the through hole 7 and the second surface 2 b of the semiconductor substrate 2 using a negative resin material.
  • the p-type region 2c in which p-type impurities are selectively diffused is provided in a predetermined region on the first surface 2a side in the semiconductor substrate 2 made of, for example, n-type silicon.
  • the conductivity type may be reversed.
  • the extraction electrode 9 and the extraction electrode 23 function as a cathode electrode and an anode electrode, respectively.
  • the first conductivity type is not limited to the one in which the region of the second conductivity type (the other of the p type and the n type) is formed in the semiconductor substrate 2 of the first conductivity type (one of the p type and the n type).
  • a semiconductor layer of the second conductivity type (the other of p type and n type) may be formed on the semiconductor substrate 2 (one of p type and n type), or the first conductivity type may be formed on the substrate.
  • a semiconductor layer (one of p-type and n-type) is formed, and a semiconductor layer of the second conductivity type (the other of p-type and n-type) is formed on the semiconductor layer of the first conductivity type; Also good. That is, it is sufficient if the second conductivity type region is formed in the first conductivity type region of the semiconductor substrate 2.
  • the semiconductor device 1 is an optical device such as a silicon photodiode. However, the semiconductor device 1 may be another optical device or an electronic device.
  • the present invention it is possible to provide a semiconductor device capable of ensuring electrical connection through a through hole in a semiconductor substrate, and a method for manufacturing such a semiconductor device.
  • SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor substrate, 2a ... 1st surface, 2b ... 2nd surface, 3 ... 1st wiring, 7 ... Through-hole, 7a ... 1st opening, 7b ... 2nd opening, 7c ... Inner surface, 8 ... second wiring, 10 ... insulating layer, 10a ... opening, 10b ... surface, 11 ... first region, 12 ... second region, 13 ... third region, 14 ... fourth region, 15 ... fifth region, 16 ... Contact hole.

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Abstract

　半導体装置１は、貫通孔７が形成された半導体基板２と、半導体基板２の第１表面２ａに設けられた第１配線３と、貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂに設けられた絶縁層１０と、絶縁層１０の表面１０ｂに設けられ、開口１０ａにおいて第１配線３に電気的に接続された第２配線８と、を備える。絶縁層１０の表面１０ｂは、第１領域１１と、第２領域１２と、第３領域１３と、第１領域１１と第２領域１２とを連続的に接続するように湾曲した第４領域１４と、第２領域１２と第３領域１３とを連続的に接続するように湾曲した第５領域１５と、を含む。第２領域１２の平均傾斜角度は、第１領域１１の平均傾斜角度よりも小さく、且つ内面７ｃの平均傾斜角度よりも小さい。

Description

半導体装置及びその製造方法
　本発明は、半導体装置及びその製造方法に関する。
　光デバイス、電子デバイス等の半導体装置では、半導体基板に形成された貫通孔を介して半導体基板の表面側と裏面側との間で電気的な接続が実施される場合がある（例えば、特許文献１参照）。
特開２００４－５７５０７号公報
　上述したような半導体装置では、その小型化、高集積化等に伴い、半導体基板における貫通孔を介した電気的な接続が脆弱になるおそれがある。
　そこで、本発明は、半導体基板における貫通孔を介した電気的な接続を確実化することができる半導体装置、及びそのような半導体装置の製造方法を提供することを目的とする。
　本発明の一側面の半導体装置は、互いに対向する第１表面及び第２表面を有し、第１表面から第２表面に至る貫通孔が形成された半導体基板と、第１表面に設けられ、一部が貫通孔の第１表面側の第１開口上に位置する第１配線と、貫通孔の内面及び第２表面に設けられ、貫通孔の第２表面側の第２開口を介して連続する絶縁層と、絶縁層の表面に設けられ、絶縁層の第１表面側の開口において第１配線に電気的に接続された第２配線と、を備え、絶縁層の表面は、貫通孔の内側において第１開口に至り、第１表面から第２表面に向かって広がるテーパ状の第１領域と、貫通孔の内側において第２開口に至り、第１表面から第２表面に向かって広がるテーパ状の第２領域と、貫通孔の外側において第２表面に対向する第３領域と、第１領域と第２領域とを連続的に接続するように湾曲した第４領域と、第２領域と第３領域とを連続的に接続するように湾曲した第５領域と、を含み、第２領域の平均傾斜角度は、第１領域の平均傾斜角度よりも小さく、且つ貫通孔の内面の平均傾斜角度よりも小さい。
　この半導体装置では、絶縁層の表面のうち、貫通孔の第１開口に至る第１領域、及び貫通孔の第２開口に至る第２領域が、半導体基板の第１表面から第２表面に向かって広がるテーパ状の領域である。そして、第２領域の平均傾斜角度が、貫通孔の内面の平均傾斜角度よりも小さくなっている。これにより、絶縁層の表面のうち、半導体基板の第２表面に対向する第３領域と貫通孔の第２開口に至る第２領域との成す角度が、半導体基板の第２表面と貫通孔の内面との成す角度よりも大きく（すなわち、緩やかに）なる。そのため、製造時においても製造後においても、貫通孔の第２開口部分での第２配線の断線が防止される。また、例えば絶縁層が貫通孔の内面に沿って均一な厚さで形成された場合と比較して第２領域の傾斜が緩やかになるため、第２配線を容易に且つ確実に形成することができる。更に、貫通孔の内面の形状に依存することなく第２配線を形成することができるので、例えば貫通孔の内面にとがった部分が残ってしまった場合にも、そのような部分に起因する第２配線の断線を防止することができる。また、第２領域の平均傾斜角度が、第１領域の平均傾斜角度よりも小さくなっている。換言すれば、貫通孔の第１開口に至る第１領域の平均傾斜角度が、第２領域の平均傾斜角度よりも大きくなっている。これにより、例えば貫通孔が小径化された場合でも、半導体基板の第１表面側における絶縁層の開口の広さが十分に確保される。そのため、製造時においても製造後においても、絶縁層の開口部分での第１配線と第２配線との断線が防止される。更に、絶縁層の表面において、第４領域が、第１領域と第２領域とを連続的に接続するように湾曲しており、第５領域が、第２領域と第３領域とを連続的に接続するように湾曲している。そのため、製造時においても製造後においても、絶縁層の表面の全領域での第２配線の断線が防止される。特に製造後においては、絶縁層の表面の全領域で応力集中が緩和されるため、第２配線の断線の防止に有効である。以上により、この半導体装置によれば、半導体基板における貫通孔を介した電気的な接続を確実化することができる。なお、貫通孔の内面の平均傾斜角度には、貫通孔の内面（貫通孔の内面が円柱面等の曲面の場合には、その曲面の接平面）が半導体基板の第１表面に直交し、貫通孔の内面が第１表面に対して９０°の角度を成す場合も含まれる。
　本発明の一側面の半導体装置では、第１領域の平均傾斜角度は、第２領域の平均傾斜角度よりも貫通孔の内面の平均傾斜角度に近くてもよい。これにより、貫通孔の第１表面側の第１開口上に位置する第１配線の一部を露出させるために十分な広さを有する開口を得ることができ、その結果、製造時においても製造後においても、絶縁層の開口部分での第１配線と第２配線との断線をより確実に防止することができる。
　本発明の一側面の半導体装置では、貫通孔の内面に設けられた絶縁層の平均厚さは、第２表面に設けられた絶縁層の平均厚さよりも大きくてもよい。これにより、例えば半導体基板が薄型化された場合でも、貫通孔の内面に設けられた絶縁層が補強層として機能するため、貫通孔周辺部分の強度を十分に確保することができる。
　本発明の一側面の半導体装置では、第１領域は、貫通孔の内面に設けられた絶縁層のうち、半導体基板の厚さと第２表面に設けられた絶縁層の平均厚さとの和の２／３以下の高さを有する部分の表面であってもよい。これにより、絶縁層の表面において、第１領域と第２領域とを緩やかに接続して、第１領域と第２領域との境界での第２配線の断線を確実に防止することができる。
　本発明の一側面の半導体装置では、第１領域は、貫通孔の内面に設けられた絶縁層のうち、半導体基板の厚さと第２表面に設けられた絶縁層の平均厚さとの和の１／２以下の高さを有する部分の表面であってもよい。これにより、絶縁層の表面において、第１領域と第２領域とをより緩やかに接続して、第１領域と第２領域との境界での第２配線の断線をより確実に防止することができる。
　本発明の一側面の半導体装置では、第４領域は、貫通孔の内面とは反対側に凸の最大曲率を有する領域であってもよい。このような絶縁層の形状は、半導体基板における貫通孔を介した電気的な接続を確実化する上で特に有効である。
　本発明の一側面の半導体装置では、貫通孔の内面は、第１表面から第２表面に向かって広がるテーパ状の面であってもよいし、或いは、貫通孔の内面（貫通孔の内面が円柱面等の曲面の場合には、その曲面の接平面）は、第１表面及び第２表面に直交する面であってもよい。いずれの場合にも、半導体基板における貫通孔を介した電気的な接続を確実化することができる。
　本発明の一側面の半導体装置では、絶縁層は、樹脂からなってもよい。これにより、上述したような形状を有する絶縁層を容易に且つ確実に形成することができる。
　本発明の一側面の半導体装置の製造方法は、上記半導体装置の製造方法であって、互いに対向する第１表面及び第２表面を有する半導体基板の第１表面に第１配線を設ける第１工程と、半導体基板に、第１表面から第２表面に至る貫通孔を形成し、貫通孔の第１表面側の第１開口に第１配線の一部を露出させる第２工程と、貫通孔の内面及び第２表面に、貫通孔の第２表面側の第２開口を介して連続する絶縁層を設ける第３工程と、絶縁層にコンタクトホールを形成し、絶縁層の第１表面側の開口に第１配線の一部を露出させる第４工程と、絶縁層の表面に第２配線を設け、絶縁層の第１表面側の開口において第１配線と第２配線とを電気的に接続する第５工程と、を備える。
　この半導体装置の製造方法によれば、半導体基板における貫通孔を介した電気的な接続が確実化された半導体装置を効率良く製造することができる。
　本発明の一側面の半導体装置の製造方法では、第３工程では、１０ｃｐ以上の粘度を有する樹脂材料を用いてディップコート法を実施することで、貫通孔の内面及び第２表面に絶縁層を設けてもよい。これにより、上述したような形状を有する絶縁層を容易に且つ確実に得ることができる。
　本発明の一側面の半導体装置の製造方法では、第３工程では、ポジ型の樹脂材料を用いて、貫通孔の内面及び第２表面に絶縁層を設け、第４工程では、絶縁層においてコンタクトホールに対応する部分を露光及び現像することで、絶縁層にコンタクトホールを形成してもよい。これにより、上述したような形状を有する絶縁層を容易に且つ確実に得ることができる。
　本発明によれば、半導体基板における貫通孔を介した電気的な接続を確実化することができる半導体装置、及びそのような半導体装置の製造方法を提供することが可能となる。
図１は、本発明の一実施形態の半導体装置の断面図である。 図２は、図１の半導体装置の貫通孔及びその周辺部分の断面図である。 図３の（ａ）及び（ｂ）は、図１の半導体装置の製造方法における複数の工程を説明するための断面図である。 図４の（ａ）及び（ｂ）は、図１の半導体装置の製造方法における複数の工程を説明するための断面図である。 図５の（ａ）及び（ｂ）は、図１の半導体装置の製造方法における複数の工程を説明するための断面図である。 図６は、図１の半導体装置の変形例の部分断面図である。 図７は、図１の半導体装置の変形例の部分断面図である。 図８は、図１の半導体装置の変形例の部分断面図である。 図９は、図１の半導体装置の貫通孔及びその周辺部分の変形例の断面図である。
　以下、本発明の実施形態について、図面を参照して詳細に説明する。なお、各図において同一又は相当部分には同一符号を付し、重複する説明を省略する。
　図１に示されるように、半導体装置１は、互いに対向する第１表面２ａ及び第２表面２ｂを有する半導体基板２を備えている。半導体装置１は、例えばシリコンフォトダイオード等の光デバイスである。半導体装置１では、例えばｎ型のシリコンからなる半導体基板２内における第１表面２ａ側の所定領域に、ｐ型の不純物が選択拡散されたｐ型領域２ｃが設けられている。半導体基板２の第１表面２ａには、例えばアルミニウムからなる第１配線３が酸化膜４を介して設けられている。酸化膜４において第１配線３のパッド部３ａに対応する部分には、開口４ａが形成されている。酸化膜４においてｐ型領域２ｃの端部に対応する部分には、開口４ｂが形成されている。第１配線３は、開口４ｂを介してｐ型領域２ｃに電気的に接続されている。なお、酸化膜４に替えて、ＳｉＮ等、他の絶縁材料からなる絶縁膜が設けられていてもよい。
　半導体基板２の第１表面２ａには、ガラス等の光透過性材料からなる光透過基板５が配置されている。半導体基板２と光透過基板５とは、光学接着剤からなる接着層６によって光学的且つ物理的に接続されている。半導体装置１では、光透過基板５及び接着層６を介してｐ型領域２ｃに光が入射する。なお、半導体基板２の厚さは、光透過基板５の厚さよりも小さい（薄い）。一例として、半導体基板２の厚さは、数十μｍ程度であり、光透過基板５の厚さは、数百μｍ程度である。
　半導体基板２には、第１表面２ａから第２表面２ｂに至る貫通孔７が形成されている。貫通孔７の第１開口７ａは、半導体基板２の第１表面２ａに位置しており、貫通孔７の第２開口７ｂは、半導体基板２の第２表面２ｂに位置している。第１開口７ａは、酸化膜４の開口４ａと連続しており、第１配線３のパッド部３ａによって覆われている。貫通孔７の内面７ｃは、第１表面２ａから第２表面２ｂに向かって広がるテーパ状の面である。例えば、貫通孔７は、第１表面２ａから第２表面２ｂに向かって広がる四角錐台状に形成されている。なお、貫通孔７の中心線ＣＬに平行な方向から見た場合に、貫通孔７の第１開口７ａの縁と酸化膜４の開口４ａの縁とは、一致している必要はなく、例えば、酸化膜４の開口４ａの縁が貫通孔７の第１開口７ａの縁に対して内側に位置していてもよい。
　貫通孔７のアスペクト比は、０．２～１０である。アスペクト比とは、貫通孔７の深さ（第１開口７ａと第２開口７ｂとの距離）を第２開口７ｂの幅（第２開口７ｂが矩形の場合には第２開口７ｂの対辺間の距離、第２開口７ｂが円形の場合には第２開口７ｂの径）で除した値である。一例として、貫通孔７の深さは３０μｍであり、第２開口７ｂの幅は１３０μｍである。この場合、アスペクト比は０．２３となる。
　貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂには、絶縁層１０が設けられている。絶縁層１０は、貫通孔７の第２開口７ｂを介して連続している。絶縁層１０は、貫通孔７の内側において、酸化膜４の開口４ａを介して第１配線３のパッド部３ａに至っており、半導体基板２の第１表面２ａ側に開口１０ａを有している。
　絶縁層１０の表面１０ｂ（貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂとは反対側の表面）には、例えばアルミニウムからなる第２配線８が設けられている。第２配線８は、絶縁層１０の開口１０ａにおいて第１配線３のパッド部３ａに電気的に接続されている。更に、絶縁層１０の表面１０ｂ（半導体基板２の第２表面２ｂとは反対側の表面）には、例えばアルミニウムからなる第３配線２２が設けられている。第３配線２２は、絶縁層１０に形成された開口１０ｃにおいて半導体基板２の第２表面２ｂに電気的に接続されている。
　第２配線８及び第３配線２２は、樹脂保護層２１によって覆われている。樹脂保護層２１において貫通孔７に対応する部分には、滑らかな内面を有する浅い凹部２１ａが形成されている。樹脂保護層２１において第２配線８のパッド部８ａに対応する部分には、パッド部８ａを露出させる開口２１ｂが形成されている。樹脂保護層２１において第３配線２２のパッド部２２ａに対応する部分には、パッド部２２ａを露出させる開口２１ｃが形成されている。樹脂保護層２１の開口２１ｂには、バンプ電極である取出し電極９が配置されている。取出し電極９は、第２配線８のパッド部８ａに電気的に接続されている。樹脂保護層２１の開口２１ｃには、バンプ電極である取出し電極２３が配置されている。取出し電極２３は、第３配線２２のパッド部２２ａに電気的に接続されている。半導体装置１は、取出し電極９及び取出し電極２３を介して回路基板に実装され、取出し電極９及び取出し電極２３は、それぞれ、アノード電極及びカソード電極として機能する。なお、樹脂保護層２１に替えて、他の絶縁材料からなる保護層（例えば、酸化膜、窒化膜等）が設けられていてもよい。また、樹脂保護層２１の厚さは、絶縁層１０の厚さと同程度であってもよいし、或いは、絶縁層１０の厚さよりも小さくてもよい。特に、樹脂保護層２１の厚さが絶縁層１０の厚さと同程度であれば、第２配線８及び第３配線２２に作用する応力を低減することができる。
　上述した絶縁層１０について、図２を参照しつつ、より詳細に説明する。なお、図２においては、光透過基板５、接着層６、取出し電極９及び樹脂保護層２１が省略されている。
　図２に示されるように、絶縁層１０の表面１０ｂは、貫通孔７の内側において第１開口７ａに至る第１領域１１と、貫通孔７の内側において第２開口７ｂに至る第２領域１２と、貫通孔７の外側において半導体基板２の第２表面２ｂに対向する第３領域１３と、を含んでいる。
　第１領域１１は、半導体基板２の第１表面２ａから第２表面２ｂに向かって広がるテーパ状の領域である。第１領域１１は、平均傾斜角度αを有している。第１領域１１の平均傾斜角度αとは、貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの一方の側の領域に着目した場合に、当該平面と第１領域１１との交線が第１表面２ａに対して成す角度の平均値である。当該交線が直線の場合には、その直線と第１表面２ａとの成す角度が、第１領域１１の平均傾斜角度αとなる。当該交線が曲線の場合には、その曲線の接線と第１表面２ａとの成す角度の平均値が、第１領域１１の平均傾斜角度αとなる。第１領域１１の平均傾斜角度αは、０°よりも大きく９０°よりも小さい。
　第２領域１２は、半導体基板２の第１表面２ａから第２表面２ｂに向かって広がるテーパ状の領域である。第２領域１２は、平均傾斜角度βを有している。第２領域１２の平均傾斜角度βとは、貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの一方の側の領域に着目した場合に、当該平面と第２領域１２との交線が第１表面２ａに対して成す角度の平均値である。当該交線が直線の場合には、その直線と第１表面２ａとの成す角度が、第２領域１２の平均傾斜角度βとなる。当該交線が曲線の場合には、その曲線の接線と第１表面２ａとの成す角度の平均値が、第２領域１２の平均傾斜角度βとなる。第２領域１２の平均傾斜角度βは、０°よりも大きく９０°よりも小さい。
　第２領域１２の平均傾斜角度βは、第１領域１１の平均傾斜角度αよりも小さい。つまり、第２領域１２は、第１領域１１よりも緩やかな傾斜を有する領域である。また、第２領域１２の平均傾斜角度βは、貫通孔７の内面７ｃの平均傾斜角度γよりも小さい。つまり、第２領域１２は、貫通孔７の内面７ｃよりも緩やかな傾斜を有する領域である。本実施形態では、第１領域１１の平均傾斜角度αは、第２領域１２の平均傾斜角度βよりも貫通孔７の内面７ｃの平均傾斜角度γに近い。ここでは、第１領域１１の平均傾斜角度α＞貫通孔７の内面７ｃの平均傾斜角度γ＞第２領域１２の平均傾斜角度βとなっている。貫通孔７の内面７ｃの平均傾斜角度γとは、貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの一方の側の領域に着目した場合に、当該平面と内面７ｃとの交線が第１表面２ａに対して成す角度の平均値である。当該交線が直線の場合には、その直線と第１表面２ａとの成す角度が、貫通孔７の内面７ｃの平均傾斜角度γとなる。当該交線が曲線の場合には、その曲線の接線と第１表面２ａとの成す角度の平均値が、貫通孔７の内面７ｃの平均傾斜角度γとなる。
　絶縁層１０の表面１０ｂは、貫通孔７の内面７ｃとは反対側に凸の最大曲率を有する第４領域１４と、貫通孔７の第２開口７ｂの縁に沿った第５領域１５と、を更に含んでいる。貫通孔７の内面７ｃとは反対側に凸の最大曲率とは、貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの一方の側の領域に着目した場合に、当該平面と表面１０ｂとの交線のうち、貫通孔７の内面７ｃとは反対側に凸状に湾曲した部分の曲率の最大値である。なお、第１領域１１は、貫通孔７の内面７ｃに設けられた絶縁層１０の表面１０ｂのうち、第４領域１４よりも貫通孔７の第１開口７ａ側（貫通孔７の中心線ＣＬに平行な方向における第１開口７ａ側）の領域である。第２領域１２は、貫通孔７の内面７ｃに設けられた絶縁層１０の表面１０ｂのうち、第４領域１４よりも貫通孔７の第２開口７ｂ側（貫通孔７の中心線ＣＬに平行な方向における第２開口７ｂ側）の領域（すなわち、第４領域１４と第５領域１５との間の領域）である。
　第４領域１４は、第１領域１１と第２領域１２とを連続的に接続するように湾曲している。つまり、第４領域１４は、丸みを帯びた曲面であり、第１領域１１と第２領域１２とを滑らかに接続している。ここで、第４領域１４が存在しないと仮定し、第１領域１１を半導体基板２の第２表面２ｂ側に延在させ、第２領域１２を半導体基板２の第１表面２ａ側に延在させると、第１領域１１と第２領域１２とによって交線（角、屈曲箇所）が形成される。第４領域１４は、当該交線（角、屈曲箇所）をＲ面取りしたときに形成される曲面に相当する。第４領域１４は、貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの一方の側の領域に着目した場合に、当該平面と表面１０ｂとの交線のうち、第１領域１１に対応する部分と第２領域１２に対応する部分との間において、貫通孔７の内面７ｃとは反対側に凸状に湾曲する部分である。
　第５領域１５は、第２領域１２と第３領域１３とを連続的に接続するように湾曲している。つまり、第５領域１５は、丸みを帯びた曲面であり、第２領域１２と第３領域１３とを滑らかに接続している。ここで、第５領域１５が存在しないと仮定し、第２領域１２を半導体基板２の第２表面２ｂ側に延在させ、第３領域１３を貫通孔７の中心線ＣＬに向かって延在させると、第２領域１２と第３領域１３とによって交線（角、屈曲箇所等）が形成される。第５領域１５は、当該交線（角、屈曲箇所等）をＲ面取りしたときに形成される曲面に相当する。第５領域１５は、貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの一方の側の領域に着目した場合に、当該平面と表面１０ｂとの交線のうち、第２領域１２に対応する部分と第３領域１３に対応する部分との間において、貫通孔７の第２開口７ｂの縁とは反対側に凸状に湾曲する部分である。
　本実施形態では、第１領域１１、第４領域１４及び第５領域１５は、貫通孔７の内面７ｃとは反対側に凸状に湾曲した曲面である。第２領域１２は、貫通孔７の内面７ｃ側に凸状に湾曲した曲面（すなわち、貫通孔７の内面７ｃとは反対側から見ると、凹状に湾曲した曲面）である。第３領域１３は、半導体基板２の第２表面２ｂに略平行な平面である。上述したように、第４領域１４が第１領域１１と第２領域１２とを連続的に接続するように湾曲しており、第５領域１５が第２領域１２と第３領域１３とを連続的に接続するように湾曲しているので、絶縁層１０の表面１０ｂは、連続した面（面と面との交線（角、屈曲箇所等）といった不連続箇所が存在せず、各領域１１，１２，１３，１４，１５が滑らかに接続された面）となっている。
　貫通孔７の内面７ｃに設けられた絶縁層１０の平均厚さは、半導体基板２の第２表面２ｂに設けられた絶縁層１０の平均厚さよりも大きい。貫通孔７の内面７ｃに設けられた絶縁層１０の平均厚さとは、内面７ｃに垂直な方向における絶縁層１０の厚さの平均値である。半導体基板２の第２表面２ｂに設けられた絶縁層１０の平均厚さとは、第２表面２ｂに垂直な方向における絶縁層１０の厚さの平均値である。
　半導体基板２の第１表面２ａ及び第２表面２ｂに平行な方向において、絶縁層１０のうち第１領域１１に対応する部分の平均厚さは、絶縁層１０のうち第２領域１２に対応する部分の平均厚さよりも大きい。半導体基板２の第１表面２ａ及び第２表面２ｂに平行な方向において、絶縁層１０のうち第１領域１１に対応する部分の平均厚さとは、当該方向における第１領域１１と貫通孔７の内面７ｃとの距離の平均値である。半導体基板２の第１表面２ａ及び第２表面２ｂに平行な方向において、絶縁層１０のうち第２領域１２に対応する部分の平均厚さとは、当該方向における第２領域１２と貫通孔７の内面７ｃとの距離の平均値である。
　絶縁層１０では、第１領域１１は、貫通孔７の内面７ｃに設けられた絶縁層１０のうち、半導体基板２の第１表面２ａから高さＨを有する部分の表面である。高さＨは、半導体基板２の厚さ（すなわち、第１表面２ａと第２表面２ｂとの距離）と半導体基板２の第２表面２ｂに設けられた絶縁層１０の平均厚さとの和Ｄの１／２以下である。
　絶縁層１０では、絶縁層１０の開口１０ａの縁及び貫通孔７の第２開口７ｂの縁を通る面Ｓを境界面として、面Ｓに対して貫通孔７の内面７ｃ側の部分Ｐ１、及び面Ｓに対して貫通孔７の内面７ｃとは反対側の部分Ｐ２に着目すると、部分Ｐ１の体積は、部分Ｐ２の体積よりも大きい。また、絶縁層１０では、貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの一方の側の領域に着目すると、三角形Ｔ１の面積は、三角形Ｔ２の面積よりも大きい。三角形Ｔ１は、貫通孔７の中心線ＣＬを含む平面において（つまり、図２の断面において）、貫通孔７の第１開口７ａの縁、貫通孔７の第２開口７ｂの縁、及び絶縁層１０の開口１０ａの縁を頂点とする三角形である。三角形Ｔ２は、貫通孔７の中心線ＣＬを含む平面において（つまり、図２の断面において）、絶縁層１０の開口１０ａの縁、貫通孔７の第２開口７ｂの縁、及び第４領域１４の頂部を頂点とする三角形である。
　以上、説明したように、半導体装置１では、絶縁層１０の表面１０ｂのうち、貫通孔７の第１開口７ａに至る第１領域１１、及び貫通孔７の第２開口７ｂに至る第２領域１２が、半導体基板２の第１表面２ａから第２表面２ｂに向かって広がるテーパ状の領域である。そして、第２領域１２の平均傾斜角度が、貫通孔７の内面７ｃの平均傾斜角度よりも小さくなっている。これにより、絶縁層１０の表面１０ｂのうち、半導体基板２の第２表面２ｂに対向する第３領域１３と貫通孔７の第２開口７ｂに至る第２領域１２との成す角度が、半導体基板２の第２表面２ｂと貫通孔７の内面７ｃとの成す角度よりも大きく（すなわち、緩やかに）なる。そのため、製造時においても製造後においても、貫通孔７の第２開口７ｂ部分での第２配線８の断線が防止される。また、例えば絶縁層１０が貫通孔７の内面７ｃに沿って均一な厚さで形成された場合と比較して第２領域１２の傾斜が緩やかになるため、第２配線８を容易に且つ確実に形成することができる。更に、貫通孔７の内面７ｃの形状に依存することなく第２配線８を形成することができるので、例えば貫通孔７の内面７ｃにとがった部分が残ってしまった場合にも、そのような部分に起因する第２配線８の断線を防止することができる。また、第２領域１２の平均傾斜角度が、第１領域１１の平均傾斜角度よりも小さくなっている。換言すれば、貫通孔７の第１開口７ａに至る第１領域１１の平均傾斜角度が、第２領域１２の平均傾斜角度よりも大きくなっている。これにより、例えば貫通孔７が小径化された場合でも、半導体基板２の第１表面２ａ側における絶縁層１０の開口１０ａの広さが十分に確保される。そのため、製造時においても製造後においても、絶縁層１０の開口１０ａ部分での第１配線３と第２配線８との断線が防止される。更に、絶縁層１０の表面１０ｂにおいて、第４領域１４が、第１領域１１と第２領域１２とを連続的に接続するように湾曲しており、第５領域１５が、第２領域１２と第３領域１３とを連続的に接続するように湾曲している。そのため、製造時においても製造後においても、絶縁層１０の表面１０ｂの全領域での第２配線８の断線が防止される。特に製造後においては、絶縁層１０の表面１０ｂの全領域で応力集中が緩和されるため、第２配線８の断線の防止に有効である。以上により、半導体装置１によれば、半導体基板２における貫通孔７を介した電気的な接続を確実化することができる。
　半導体装置１では、絶縁層１０の表面１０ｂが、連続した面（面と面との交線（角、屈曲箇所等）といった不連続箇所が存在せず、各領域１１，１２，１３，１４，１５が滑らかに接続された面）となっている。これにより、応力集中を緩和して第２配線８の断線を防止することができる。
　半導体装置１では、第１領域１１の平均傾斜角度が、第２領域１２の平均傾斜角度よりも貫通孔７の内面７ｃの平均傾斜角度に近い。これにより、第１配線３のパッド部３ａを露出させるために十分な広さを有する開口１０ａを得ることができ、その結果、製造時においても製造後においても、絶縁層１０の開口１０ａ部分での第１配線３と第２配線８との断線をより確実に防止することができる。
　半導体装置１では、第１領域１１の平均傾斜角度α＞貫通孔７の内面７ｃの平均傾斜角度γ＞第２領域１２の平均傾斜角度βとなっている。これにより、第２配線８の断線を防止することができると共に、第１配線３のパッド部３ａを露出させるために十分な広さを有する開口１０ａを得ることができる。
　半導体装置１では、貫通孔７の内面７ｃに設けられた絶縁層１０の平均厚さが、第２表面２ｂに設けられた絶縁層１０の平均厚さよりも大きくなっている。これにより、例えば半導体基板２が薄型化された場合でも、貫通孔７の内面７ｃに設けられた絶縁層１０が補強層として機能するため、貫通孔７周辺部分の強度を十分に確保することができる。また、第１領域１１の平均傾斜角度及び第２領域１２の平均傾斜角度を所望の角度にすることができ、表面１０ｂが連続した面（面と面との交線（角、屈曲箇所等）といった不連続箇所が存在せず、各領域１１，１２，１３，１４，１５が滑らかに接続された面）となっている絶縁層１０を得ることが可能となる。例えば絶縁層１０が貫通孔７の内面７ｃに沿って均一な厚さで形成された場合には、表面１０ｂが連続した面となっている絶縁層１０を得ることは不可能である。
　半導体装置１では、半導体基板２の第１表面２ａ及び第２表面２ｂに平行な方向において、絶縁層１０のうち第１領域１１に対応する部分の平均厚さが、絶縁層１０のうち第２領域１２に対応する部分の平均厚さよりも大きい。これにより、第２配線８の断線が発生し難く且つ第１配線３と第２配線８との断線が発生し難い形状を有する絶縁層１０を得ることが可能となる。
　半導体装置１では、例えば貫通孔７の第２開口７ｂの縁にオーバーハング等が残存していたとしても、当該オーバーハング等が絶縁層１０に覆われ、凸状に湾曲した曲面である第５領域１５に第２配線８が設けられることになる。これにより、貫通孔７の第２開口７ｂ部分での第２配線８の断線を確実に防止することができる。
　半導体装置１では、貫通孔７の内面７ｃに設けられた絶縁層１０のうち、半導体基板２の厚さと第２表面２ｂに設けられた絶縁層１０の平均厚さとの和Ｄの１／２以下の高さＨを有する部分の表面が、第１領域１１となっている。これにより、絶縁層１０の表面１０ｂにおいて、第１領域１１と第２領域１２とを緩やかに接続して、第１領域１１と第２領域１２との境界での第２配線８の断線を確実に防止することができる。
　半導体装置１の絶縁層１０では、絶縁層１０の開口１０ａの縁及び貫通孔７の第２開口７ｂの縁を通る面Ｓを境界面として、面Ｓに対して貫通孔７の内面７ｃ側の部分Ｐ１、及び面Ｓに対して貫通孔７の内面７ｃとは反対側の部分Ｐ２に着目すると、部分Ｐ１の体積が部分Ｐ２の体積よりも大きくなっている。また、貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの一方の側の領域に着目すると、三角形Ｔ１の面積が三角形Ｔ２の面積よりも大きくなっている。これらによっても、絶縁層１０の表面１０ｂにおいて、第１領域１１と第２領域１２とを緩やかに接続して、第１領域１１と第２領域１２との境界での第２配線８の断線を確実に防止することができる。
　半導体装置１では、貫通孔７の内面７ｃに設けられた絶縁層１０の表面１０ｂのうち、貫通孔７の内面７ｃとは反対側に凸の最大曲率を有する第４領域１４よりも第１開口７ａ側の領域が第１領域１１となっており、第４領域１４よりも第２開口７ｂ側の領域が第２領域１２となっている。このような絶縁層１０の形状は、半導体基板２における貫通孔７を介した電気的な接続を確実化する上で特に有効である。
　半導体装置１では、貫通孔７の内面７ｃが、第１表面２ａから第２表面２ｂに向かって広がるテーパ状の面である。この場合にも、半導体基板２における貫通孔７を介した電気的な接続を確実化することができる。
　半導体装置１では、絶縁層１０が樹脂からなる。これにより、上述したような形状を有する絶縁層１０を容易に且つ確実に形成することができる。
　次に、上述した半導体装置１の製造方法について、図３～図５を参照しつつ、説明する。まず、半導体基板２を用意し、半導体基板２の第１表面２ａにデバイスを構成する（すなわち、第１表面２ａに、酸化膜４、第１配線３等を設ける）（第１工程）。そして、半導体基板２の第１表面２ａに接着層６を介して光透過基板５を取り付ける。
　続いて、図３の（ａ）に示されるように、異方性のウェットエッチングによって半導体基板２に貫通孔７を形成し、更に、図３の（ｂ）に示されるように、酸化膜４において第１配線３のパッド部３ａに対応する部分を除去して、酸化膜４に開口４ａを形成する。これにより、貫通孔７の第１開口７ａに第１配線３のパッド部３ａを露出させる（第２工程）。なお、貫通孔７の中心線ＣＬに平行な方向から見た場合に、貫通孔７の第１開口７ａの縁と酸化膜４の開口４ａの縁とが一致するように酸化膜４に開口４ａを形成する必要はなく、例えば、酸化膜４の開口４ａの縁が貫通孔７の第１開口７ａの縁に対して内側に位置するように酸化膜４に開口４ａを形成してもよい。
　続いて、１０ｃｐ以上の粘度を有し且つポジ型の樹脂材料を用意し、当該樹脂材料を用いてディップコート法（対象物を樹脂塗料に浸漬させ、対象物を樹脂塗料から引き上げることで、対象物に樹脂層を形成する方法）を実施することで、図４の（ａ）に示されるように、貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂに絶縁層１０を設ける（第３工程）。これにより、絶縁層１０には、第２領域１２、第３領域１３及び第５領域１５に追従した内面を有する凹部１７が形成される。なお、樹脂材料としては、例えば、フェノール樹脂、ポリイミド樹脂、エポキシ樹脂等を用いることができる。
　続いて、図４の（ｂ）に示されるように、半導体基板２の第２表面２ｂに設けられた絶縁層１０上に、マスク３０を配置する。マスク３０は、第１配線３のパッド部３ａに対向する位置に光透過部３１を有し、光透過部３１の周囲に遮光部３２を有している。続いて、絶縁層１０においてコンタクトホール１６に対応する部分に、マスク３０の光透過部３１を介して光を照射し、当該部分を露光する。更に、絶縁層１０においてコンタクトホール１６に対応する部分を現像することで、絶縁層１０にコンタクトホール１６を形成する。これにより、絶縁層１０の開口１０ａに第１配線３のパッド部３ａを露出させる（第４工程）。なお、コンタクトホール１６を形成する際に、アッシング処理等を併用してもよい。
　露光の際には、マスク３０の光透過部３１と絶縁層１０においてコンタクトホール１６に対応する部分との間に、絶縁層１０に形成された凹部１７によって隙間が形成される。これにより、光が回折して絶縁層１０に照射されることになる。そのため、現像の際には、半導体基板２の第１表面２ａから第２表面２ｂに向かって広がるテーパ状の第１領域１１、及び第２領域１２に追従した内面を有するコンタクトホール１６が形成される。
　続いて、図５の（ａ）に示されるように、例えばアルミニウムを用いてスパッタ法を実施することで、絶縁層１０の表面１０ｂに第２配線８を設け、絶縁層１０の開口１０ａにおいて第１配線３と第２配線８とを電気的に接続する（第５工程）。このとき、コンタクトホール１６が、半導体基板２の第１表面２ａから第２表面２ｂに向かって広がるテーパ状の第１領域１１に追従した内面を有しているため、当該内面にも金属膜が確実に形成され、延いては、絶縁層１０の開口１０ａにおいて第１配線３と第２配線８とが確実に接続される。
　続いて、例えば絶縁層１０と同一の樹脂材料を用いてディップコート法を実施することで、図５の（ｂ）に示されるように、第２配線８を樹脂保護層２１で覆う。最後に、樹脂保護層２１で覆われていない第２配線８のパッド部８ａに取出し電極９を配置し、上述した半導体装置１を得る。
　上記半導体装置１の製造方法によれば、半導体基板２における貫通孔７を介した電気的な接続が確実化された半導体装置１を効率良く製造することができる。
　上記半導体装置１の製造方法では、１０ｃｐ以上の粘度を有する樹脂材料を用いてディップコート法を実施することで、貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂに絶縁層１０を設ける。これにより、上述したような形状を有する絶縁層１０を容易に且つ確実に得ることができる。
　なお、ディップコート法には、粘性の低い樹脂材料（例えば撥水コーティングに用いられる樹脂材料等、例えば１ｃｐ以下の粘度を有する樹脂材料)が用いられることが一般的である。しかし、そのような樹脂材料を用いてディップコート法を実施しても、絶縁層１０が貫通孔７の内面７ｃに沿って略均一な厚さで形成されてしまう。そこで、上記半導体装置１の製造方法では、１０ｃｐ以上の粘度を有する樹脂材料を用いてディップコート法を実施することで、上述したような形状を有する絶縁層１０を容易に且つ確実に得ることができる。
　上記半導体装置１の製造方法では、ポジ型の樹脂材料を用いて、貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂに絶縁層１０を設ける。そして、絶縁層１０においてコンタクトホール１６に対応する部分を露光及び現像することで、絶縁層１０にコンタクトホール１６を形成する。これにより、上述したような形状を有する絶縁層１０を容易に且つ確実に得ることができる。なお、露光及び現像の際には、絶縁層１０に形成された凹部１７によって、絶縁層１０においてコンタクトホール１６に対応する部分の厚さが薄くなっているため（すなわち、コンタクトホール１６に対応する部分が、絶縁層１０のうち、半導体基板２の厚さと第２表面２ｂに設けられた絶縁層１０の平均厚さとの和Ｄの１／２以下の高さＨを有する部分であるため）、所望の形状を有するコンタクトホール１６を容易に且つ確実に得ることができる。
　上記半導体装置１の製造方法では、半導体基板２に光透過基板５が取り付けられた状態で、ディップコート法を実施する。そのため、薄型化された半導体基板２を用いることができる。薄型化された半導体基板２では、貫通孔７の深さが小さくなることから、１０ｃｐ以上という高い粘度を有する樹脂材料を用いたディップコート法によって絶縁層１０が厚くなっても、絶縁層１０にコンタクトホール１６を容易に且つ確実に形成することができる。
　以上、本発明の一実施形態について説明したが、本発明は、上記実施形態に限定されるものではない。例えば、絶縁層１０は、樹脂以外の絶縁材料によって形成されていてもよい。また、上記実施形態では、貫通孔７の第１開口７ａが第１配線３のパッド部３ａによって覆われていたが、第１配線３の一部が第１開口７ａ上に位置していればよく、第１配線３が第１開口７ａの全領域を覆っていなくてもよい。
　また、上記実施形態では、第１領域１１の平均傾斜角度が、第２領域１２の平均傾斜角度よりも貫通孔７の内面７ｃの平均傾斜角度に近かったが、第２領域１２の平均傾斜角度が、第１領域１１の平均傾斜角度よりも貫通孔７の内面７ｃの平均傾斜角度に近くてもよい。
　また、図６に示されるように、半導体基板２の第１表面２ａには、光透過基板５が接着層６を介して取り付けられていなくてもよい。この場合、第１表面２ａには、第１配線３を覆うように酸化膜１８が設けられている。このように、半導体基板２に光透過基板５が取り付けられていない場合には、絶縁層１０において第１表面２ａから高さＨを有する部分は、補強層として機能するため、貫通孔７周辺部分の強度を十分に確保する観点から特に有効である。
　また、図７及び図８に示されるように、取出し電極９は、半導体基板２の第２表面２ｂから突出するように、貫通孔７の内側に配置されていてもよい。この場合にも、図７に示されるように、半導体基板２の第１表面２ａに光透過基板５が接着層６を介して取り付けられていてもよいし、或いは、図８に示されるように、半導体基板２の第１表面２ａに光透過基板５が接着層６を介して取り付けられていなくてもよい。
　また、図９に示されるように、貫通孔７の内面７ｃ（貫通孔７の内面７ｃが円柱面等の曲面の場合には、その曲面の接平面）は、第１表面２ａ及び第２表面２ｂに直交する面であってもよい。この場合にも、半導体基板２における貫通孔７を介した電気的な接続を確実化することができる。ここで、貫通孔７のアスペクト比は、０．２～１０である。一例として、貫通孔７の深さは４０μｍであり、第２開口７ｂの幅は３０μｍである。この場合、アスペクト比は１．３となる。なお、円柱状、四角柱状等の形状を有する貫通孔７は、例えばドライエッチングによって形成される。
　図９に示される貫通孔７についても、第２領域１２の平均傾斜角度βは、第１領域１１の平均傾斜角度αよりも小さく、且つ貫通孔７の内面７ｃの平均傾斜角度γ（この場合には、９０°）よりも小さい。つまり、第２領域１２は、第１領域１１よりも緩やかな傾斜を有し、且つ貫通孔７の内面７ｃよりも緩やかな傾斜を有する領域である。また、第１領域１１の平均傾斜角度αは、第２領域１２の平均傾斜角度βよりも貫通孔７の内面７ｃの平均傾斜角度γに近い。ここでは、貫通孔７の内面７ｃの平均傾斜角度γ＞第１領域１１の平均傾斜角度α＞第２領域１２の平均傾斜角度βとなっている。これにより、第２配線８の断線を防止することができると共に、第１配線３のパッド部３ａを露出させるために十分な広さを有する開口１０ａを得ることができる。また、絶縁層１０の表面１０ｂは、連続した面（面と面との交線（角、屈曲箇所等）といった不連続箇所が存在せず、各領域１１，１２，１３，１４，１５が滑らかに接続された面）となっている。また、絶縁層１０では、絶縁層１０の開口１０ａの縁及び貫通孔７の第２開口７ｂの縁を通る面Ｓを境界面として、面Ｓに対して貫通孔７の内面７ｃ側の部分Ｐ１、及び面Ｓに対して貫通孔７の内面７ｃとは反対側の部分Ｐ２に着目すると、部分Ｐ１の体積は、部分Ｐ２の体積よりも大きい。また、絶縁層１０では、貫通孔７の中心線ＣＬを含む平面について、中心線ＣＬの一方の側の領域に着目すると、三角形Ｔ１の面積は、三角形Ｔ２の面積よりも大きい。また、半導体基板２の第１表面２ａ及び第２表面２ｂに平行な方向において、絶縁層１０のうち第１領域１１に対応する部分の平均厚さは、絶縁層１０のうち第２領域１２に対応する部分の平均厚さよりも大きい。
　また、第１領域１１は、貫通孔７の内面７ｃに設けられた絶縁層１０のうち、半導体基板２の厚さと半導体基板２の第２表面２ｂに設けられた絶縁層１０の平均厚さとの和Ｄの２／３以下の高さＨを有する部分の表面１０ｂであってもよい（図９参照）。この場合にも、絶縁層１０の表面１０ｂにおいて、第１領域１１と第２領域１２とを緩やかに接続して、第１領域１１と第２領域１２との境界での第２配線８の断線を確実に防止することができる。なお、露光及び現像の際には、絶縁層１０に形成された凹部１７によって、絶縁層１０においてコンタクトホール１６に対応する部分の厚さが薄くなっているため（すなわち、コンタクトホール１６に対応する部分が、絶縁層１０のうち、半導体基板２の厚さと第２表面２ｂに設けられた絶縁層１０の平均厚さとの和Ｄの２／３以下の高さＨを有する部分であるため）、所望の形状を有するコンタクトホール１６を容易に且つ確実に得ることができる。
　また、上記半導体装置１の製造方法では、ディップコート法を実施することで、貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂに絶縁層１０を設けたが、本発明は、これに限定されない。例えば、樹脂シートを用いたラミネート法、樹脂塗料を用いたスピンコート法等、他の方法を実施することで、貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂに絶縁層１０を設けてもよい。
　また、上記半導体装置１の製造方法では、ポジ型の樹脂材料を用いて、貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂに絶縁層１０を設け、絶縁層１０においてコンタクトホール１６に対応する部分を露光及び現像することで、絶縁層１０にコンタクトホール１６を形成したが、本発明は、これに限定されない。例えば、ネガ型の樹脂材料を用いて、貫通孔７の内面７ｃ及び半導体基板２の第２表面２ｂに絶縁層１０を設けてもよい。この場合、絶縁層１０においてコンタクトホール１６に対応する部分以外の部分を露光し、絶縁層１０においてコンタクトホール１６に対応する部分を現像することで、絶縁層１０にコンタクトホール１６を形成してもよい。光の減衰、光の回折等に起因して、現像だけでは、半導体基板２の第２表面２ｂから第１表面２ａに向かって広がるテーパ状のコンタクトホール１６が形成され得るが、更に熱処理等を施すことで、半導体基板２の第１表面２ａから第２表面２ｂに向かって広がるテーパ状のコンタクトホール１６を得ることができる。
　また、上記実施形態では、例えばｎ型のシリコンからなる半導体基板２内における第１表面２ａ側の所定領域に、ｐ型の不純物が選択拡散されたｐ型領域２ｃが設けられていたが、各導電型は、逆であってもよい。その場合、取出し電極９及び取出し電極２３は、それぞれ、カソード電極及びアノード電極として機能する。更に、第１導電型（ｐ型及びｎ型の一方）の半導体基板２内に第２導電型（ｐ型及びｎ型の他方）の領域が形成されたものに限定されず、第１導電型（ｐ型及びｎ型の一方）の半導体基板２上に第２導電型（ｐ型及びｎ型の他方）の半導体層が形成されたものであってもよいし、基板上に第１導電型（ｐ型及びｎ型の一方）の半導体層が形成され、当該第１導電型の半導体層上に第２導電型（ｐ型及びｎ型の他方）の半導体層が形成されたものであってもよい。つまり、半導体基板２の第１導電型の領域に第２導電型の領域が形成されたものであればよい。また、上記実施形態では、半導体装置１が、例えばシリコンフォトダイオード等の光デバイスであったが、半導体装置１は、その他の光デバイスであってもよいし、電子デバイス等であってもよい。
　本発明によれば、半導体基板における貫通孔を介した電気的な接続を確実化することができる半導体装置、及びそのような半導体装置の製造方法を提供することが可能となる。
　１…半導体装置、２…半導体基板、２ａ…第１表面、２ｂ…第２表面、３…第１配線、７…貫通孔、７ａ…第１開口、７ｂ…第２開口、７ｃ…内面、８…第２配線、１０…絶縁層、１０ａ…開口、１０ｂ…表面、１１…第１領域、１２…第２領域、１３…第３領域、１４…第４領域、１５…第５領域、１６…コンタクトホール。

Claims (12)

  1. 　互いに対向する第１表面及び第２表面を有し、前記第１表面から前記第２表面に至る貫通孔が形成された半導体基板と、
    　前記第１表面に設けられ、一部が前記貫通孔の前記第１表面側の第１開口上に位置する第１配線と、
    　前記貫通孔の内面及び前記第２表面に設けられ、前記貫通孔の前記第２表面側の第２開口を介して連続する絶縁層と、
    　前記絶縁層の表面に設けられ、前記絶縁層の前記第１表面側の開口において前記第１配線に電気的に接続された第２配線と、を備え、
    　前記絶縁層の前記表面は、
    　前記貫通孔の内側において前記第１開口に至り、前記第１表面から前記第２表面に向かって広がるテーパ状の第１領域と、
    　前記貫通孔の内側において前記第２開口に至り、前記第１表面から前記第２表面に向かって広がるテーパ状の第２領域と、
    　前記貫通孔の外側において前記第２表面に対向する第３領域と、
    　前記第１領域と前記第２領域とを連続的に接続するように湾曲した第４領域と、
    　前記第２領域と前記第３領域とを連続的に接続するように湾曲した第５領域と、を含み、
    　前記第２領域の平均傾斜角度は、前記第１領域の平均傾斜角度よりも小さく、且つ前記貫通孔の前記内面の平均傾斜角度よりも小さい、半導体装置。
  2. 　前記第１領域の前記平均傾斜角度は、前記第２領域の前記平均傾斜角度よりも前記貫通孔の前記内面の平均傾斜角度に近い、請求項１記載の半導体装置。
  3. 　前記貫通孔の前記内面に設けられた前記絶縁層の平均厚さは、前記第２表面に設けられた前記絶縁層の平均厚さよりも大きい、請求項１又は２記載の半導体装置。
  4. 　前記第１領域は、前記貫通孔の前記内面に設けられた前記絶縁層のうち、前記半導体基板の厚さと前記第２表面に設けられた前記絶縁層の平均厚さとの和の２／３以下の高さを有する部分の表面である、請求項１～３のいずれか一項記載の半導体装置。
  5. 　前記第１領域は、前記貫通孔の前記内面に設けられた前記絶縁層のうち、前記半導体基板の厚さと前記第２表面に設けられた前記絶縁層の平均厚さとの和の１／２以下の高さを有する部分の表面である、請求項４記載の半導体装置。
  6. 　前記第４領域は、前記貫通孔の前記内面とは反対側に凸の最大曲率を有する領域である、請求項１～５のいずれか一項記載の半導体装置。
  7. 　前記貫通孔の前記内面は、前記第１表面から前記第２表面に向かって広がるテーパ状の面である、請求項１～６のいずれか一項記載の半導体装置。
  8. 　前記貫通孔の前記内面は、前記第１表面及び前記第２表面に直交する面である、請求項１～６のいずれか一項記載の半導体装置。
  9. 　前記絶縁層は、樹脂からなる、請求項１～８のいずれか一項記載の半導体装置。
  10. 　請求項１～９のいずれか一項記載の半導体装置の製造方法であって、
    　互いに対向する第１表面及び第２表面を有する半導体基板の前記第１表面に第１配線を設ける第１工程と、
    　前記半導体基板に、前記第１表面から前記第２表面に至る貫通孔を形成し、前記貫通孔の前記第１表面側の第１開口に前記第１配線の一部を露出させる第２工程と、
    　前記貫通孔の内面及び前記第２表面に、前記貫通孔の前記第２表面側の第２開口を介して連続する絶縁層を設ける第３工程と、
    　前記絶縁層にコンタクトホールを形成し、前記絶縁層の前記第１表面側の開口に前記第１配線の一部を露出させる第４工程と、
    　前記絶縁層の表面に第２配線を設け、前記絶縁層の前記第１表面側の前記開口において前記第１配線と前記第２配線とを電気的に接続する第５工程と、を備える、半導体装置の製造方法。
  11. 　前記第３工程では、１０ｃｐ以上の粘度を有する樹脂材料を用いてディップコート法を実施することで、前記貫通孔の前記内面及び前記第２表面に前記絶縁層を設ける、請求項１０記載の半導体装置の製造方法。
  12. 　前記第３工程では、ポジ型の樹脂材料を用いて、前記貫通孔の前記内面及び前記第２表面に前記絶縁層を設け、
    　前記第４工程では、前記絶縁層において前記コンタクトホールに対応する部分を露光及び現像することで、前記絶縁層に前記コンタクトホールを形成する、請求項１０又は１１記載の半導体装置の製造方法。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020202353A (ja) * 2019-06-13 2020-12-17 キヤノン株式会社 半導体装置およびその製造方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6469213B2 (ja) * 2015-03-31 2019-02-13 浜松ホトニクス株式会社 半導体装置
JP6725231B2 (ja) * 2015-10-06 2020-07-15 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、および電子装置
JP6552547B2 (ja) * 2017-05-24 2019-07-31 三菱電機株式会社 赤外線センサおよび赤外線固体撮像装置
US11659746B2 (en) * 2018-03-09 2023-05-23 Sharp Kabushiki Kaisha Display device
US11635186B2 (en) * 2018-03-13 2023-04-25 Motherson Innovations Company Limited Polymeric substrate and a method of providing same
JP6878338B2 (ja) * 2018-03-14 2021-05-26 株式会社東芝 受光装置および受光装置の製造方法
CN112368602B (zh) * 2018-07-12 2023-03-14 深圳帧观德芯科技有限公司 具有高时间分辨率的光学雷达
JP7251946B2 (ja) * 2018-10-31 2023-04-04 浜松ホトニクス株式会社 固体撮像装置
JP7067448B2 (ja) 2018-12-10 2022-05-16 三菱電機株式会社 半導体装置の製造方法、半導体装置
WO2020161937A1 (ja) * 2019-02-05 2020-08-13 パナソニックＩｐマネジメント株式会社 センサ装置
CN114223066A (zh) * 2019-08-28 2022-03-22 京瓷株式会社 发光元件搭载用封装件以及发光装置
JP7257978B2 (ja) * 2020-01-20 2023-04-14 三菱電機株式会社 半導体装置
US11322639B2 (en) * 2020-04-09 2022-05-03 Globalfoundries U.S. Inc. Avalanche photodiode

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59126643A (ja) * 1983-01-07 1984-07-21 Matsushita Electric Ind Co Ltd 電子回路の被覆方法
JPH08330295A (ja) * 1995-03-24 1996-12-13 Fuji Electric Co Ltd 半導体装置の製造方法
JP2006215062A (ja) * 2005-02-01 2006-08-17 Sharp Corp 液晶表示パネル、液晶表示装置、および液晶表示パネルの製造方法
JP2007305955A (ja) * 2006-04-10 2007-11-22 Toshiba Corp 半導体装置及びその製造方法
JP2008277371A (ja) * 2007-04-26 2008-11-13 Sony Corp 半導体装置、電子機器、および半導体装置の製造方法

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4830706A (en) * 1986-10-06 1989-05-16 International Business Machines Corporation Method of making sloped vias
JPH02268416A (ja) 1989-04-11 1990-11-02 Matsushita Electron Corp 半導体装置の製造方法及びそれに使用するフオトマスク
JPH0414830A (ja) 1990-05-08 1992-01-20 Fujitsu Ltd 半導体装置の製造方法
KR0127271B1 (ko) 1993-11-23 1998-04-02 김주용 반도체 소자의 금속배선 형성방법
JP3577913B2 (ja) * 1997-02-27 2004-10-20 セイコーエプソン株式会社 半導体装置、およびこれを具備する電子機器
JPH10307305A (ja) * 1997-03-07 1998-11-17 Toshiba Corp アレイ基板、液晶表示装置及びそれらの製造方法
JP2003007921A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置およびその製造方法
JP2003101222A (ja) * 2001-09-21 2003-04-04 Sony Corp 薄膜回路基板装置及びその製造方法
JP2004057507A (ja) 2002-07-29 2004-02-26 Toshiba Corp Ｘ線検出装置、貫通電極の製造方法及びｘ線断層撮影装置
JP2004273561A (ja) * 2003-03-05 2004-09-30 Sanyo Electric Co Ltd 半導体装置及びその製造方法
EP1519410A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
JP3970210B2 (ja) * 2003-06-24 2007-09-05 三洋電機株式会社 半導体装置の製造方法
JP4250038B2 (ja) 2003-08-20 2009-04-08 シャープ株式会社 半導体集積回路
JP2005101268A (ja) 2003-09-25 2005-04-14 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2005158907A (ja) * 2003-11-25 2005-06-16 Mitsui Chemicals Inc 配線板の製造方法
JP2007105859A (ja) 2005-10-17 2007-04-26 Canon Inc 配向性メソ構造体膜、配向性メソポーラス物質膜、及びその製造方法、及びそれを用いた半導体素子
CN101379615B (zh) * 2006-02-01 2013-06-12 皇家飞利浦电子股份有限公司 盖革式雪崩光电二极管
CN100563000C (zh) * 2006-04-10 2009-11-25 株式会社东芝 半导体器件及其制造方法
JP2007305960A (ja) * 2006-04-14 2007-11-22 Sharp Corp 半導体装置およびその製造方法
WO2007135768A1 (ja) 2006-05-19 2007-11-29 Sumitomo Bakelite Co., Ltd. 半導体装置
JP5155536B2 (ja) * 2006-07-28 2013-03-06 一般財団法人電力中央研究所 ＳｉＣ結晶の質を向上させる方法およびＳｉＣ半導体素子の製造方法
US20080036097A1 (en) 2006-08-10 2008-02-14 Teppei Ito Semiconductor package, method of production thereof and encapsulation resin
TW200915970A (en) 2007-09-27 2009-04-01 Sanyo Electric Co Circuit device, circuit module and outdoor equipment
EP2325882A4 (en) 2008-09-18 2017-01-04 The University of Tokyo Method for manufacturing semiconductor device
JP5369608B2 (ja) * 2008-10-23 2013-12-18 富士電機株式会社 無停電電源装置および無停電電源装置の選択遮断方法
WO2010147187A1 (ja) 2009-06-18 2010-12-23 ローム株式会社 半導体装置
JP5423572B2 (ja) * 2010-05-07 2014-02-19 セイコーエプソン株式会社 配線基板、圧電発振器、ジャイロセンサー、配線基板の製造方法
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) * 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
JP5447316B2 (ja) * 2010-09-21 2014-03-19 株式会社大真空 電子部品パッケージ用封止部材、及び電子部品パッケージ
KR101215648B1 (ko) * 2011-02-11 2012-12-26 에스케이하이닉스 주식회사 반도체 칩 및 그 제조방법
WO2012120653A1 (ja) 2011-03-08 2012-09-13 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
JP5926921B2 (ja) 2011-10-21 2016-05-25 浜松ホトニクス株式会社 光検出装置
JP5832852B2 (ja) 2011-10-21 2015-12-16 浜松ホトニクス株式会社 光検出装置
JP5791461B2 (ja) 2011-10-21 2015-10-07 浜松ホトニクス株式会社 光検出装置
JP5810921B2 (ja) 2012-01-06 2015-11-11 凸版印刷株式会社 半導体装置の製造方法
US9006896B2 (en) 2012-05-07 2015-04-14 Xintec Inc. Chip package and method for forming the same
US8791578B2 (en) 2012-11-12 2014-07-29 Hong Kong Applied Science and Technology Research Institute Company Limited Through-silicon via structure with patterned surface, patterned sidewall and local isolation
JP2014110284A (ja) * 2012-11-30 2014-06-12 Ps4 Luxco S A R L 半導体装置の製造方法
KR102066087B1 (ko) * 2013-05-28 2020-01-15 엘지디스플레이 주식회사 플렉서블 표시장치 및 그의 제조방법
US9484325B2 (en) 2013-10-09 2016-11-01 Invensas Corporation Interconnections for a substrate associated with a backside reveal
CN103762198B (zh) * 2013-12-31 2016-07-06 中国科学院微电子研究所 一种tsv填孔方法
JP2016058655A (ja) 2014-09-11 2016-04-21 株式会社ジェイデバイス 半導体装置の製造方法
JP2016062996A (ja) 2014-09-16 2016-04-25 株式会社東芝 光検出器
US9659980B2 (en) 2014-12-19 2017-05-23 Sensl Technologies Ltd Semiconductor photomultiplier
JP6469213B2 (ja) * 2015-03-31 2019-02-13 浜松ホトニクス株式会社 半導体装置
US9502350B1 (en) 2016-01-28 2016-11-22 International Business Machines Corporation Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59126643A (ja) * 1983-01-07 1984-07-21 Matsushita Electric Ind Co Ltd 電子回路の被覆方法
JPH08330295A (ja) * 1995-03-24 1996-12-13 Fuji Electric Co Ltd 半導体装置の製造方法
JP2006215062A (ja) * 2005-02-01 2006-08-17 Sharp Corp 液晶表示パネル、液晶表示装置、および液晶表示パネルの製造方法
JP2007305955A (ja) * 2006-04-10 2007-11-22 Toshiba Corp 半導体装置及びその製造方法
JP2008277371A (ja) * 2007-04-26 2008-11-13 Sony Corp 半導体装置、電子機器、および半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020202353A (ja) * 2019-06-13 2020-12-17 キヤノン株式会社 半導体装置およびその製造方法
US11437299B2 (en) 2019-06-13 2022-09-06 Canon Kabushiki Kaisha Semiconductor apparatus and method of manufacturing the same
JP7340965B2 (ja) 2019-06-13 2023-09-08 キヤノン株式会社 半導体装置およびその製造方法

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