CN107360729A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN107360729A
CN107360729A CN201680018889.3A CN201680018889A CN107360729A CN 107360729 A CN107360729 A CN 107360729A CN 201680018889 A CN201680018889 A CN 201680018889A CN 107360729 A CN107360729 A CN 107360729A
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region
hole
insulating barrier
semiconductor device
distribution
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CN107360729B (zh
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细川畅郎
井上直
柴山胜己
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Hamamatsu Photonics KK
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Hamamatsu Photonics KK
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Abstract

半导体装置(1)包含:半导体基板(2),其形成有贯通孔(7);第1配线(3),其设置于半导体基板(2)的第1表面(2a);绝缘层(10),其设置在贯通孔(7)的内表面(7c)及半导体基板(2)的第2表面(2b);及第2配线(8),其设置在绝缘层(10)的表面(10b),且在开口(10a)中与第1配线(3)电连接。在绝缘层(10)的表面(10b),包含:第1区域(11);第2区域(12);第3区域(13);第4区域(14),其以将第1区域(1)与第2区域(12)连续地连接的方式弯曲;及第5区域(15),其以将第2区域(12)与第3区域(13)连续地连接的方式弯曲。第2区域(12)的平均倾斜角度较第1区域(11)的平均倾斜角度小,且较内表面(7c)的平均倾斜角度小。

Description

半导体装置及其制造方法
技术领域
本发明关于一种半导体装置及其制造方法。
背景技术
在光装置、电子装置等的半导体装置中,有经由形成于半导体基板的贯通孔而在半导体基板的表面侧与内表面侧之间实施电连接的情形(例如,参照专利文献1)。
现有技术文献
专利文献
专利文献1:日本特开2004-57507号公报
发明内容
发明所要解决的问题
在上述的半导体装置中,伴随着其小型化、高集成化等,半导体基板的经由贯通孔的电连接有变得脆弱的担忧。
因此,本发明的目的在于提供一种可将半导体基板的经由贯通孔的电连接确实化的半导体装置,及此种半导体装置的制造方法。
解决问题的技术手段
本发明的一形态的半导体装置包含:半导体基板,其具有彼此相对的第1表面及第2表面,且形成有自第1表面到达至第2表面的贯通孔;第1配线,其设置于第1表面,且一部分位在贯通孔的第1表面侧的第1开口上;绝缘层,其设置在贯通孔的内表面及第2表面,且经由贯通孔的第2表面侧的第2开口而连续;及第2配线,其设置在绝缘层的表面,且在绝缘层的第1表面侧的开口中与第1配线电连接;绝缘层的表面包含:在贯通孔的内侧到达至第1开口,且自第1表面向第2表面扩大的锥状的第1区域;在贯通孔的内侧到达至第2开口,且自第1表面向第2表面扩大的锥状的第2区域;第3区域,其在贯通孔的外侧中与第2表面相对;以将第1区域与第2区域连续地连接的方式弯曲的第4区域;及以将第2区域与第3区域连续地连接的方式弯曲的第5区域;且第2区域的平均倾斜角度较第1区域的平均倾斜角度小,且较贯通孔的内表面的平均倾斜角度小。
在该半导体装置中,绝缘层的表面中的到达至贯通孔的第1开口的第1区域、及到达至贯通孔的第2开口的第2区域为自半导体基板的第1表面向第2表面扩大的锥状的区域。然后,第2区域的平均倾斜角度成为较贯通孔的内表面的平均倾斜角度小。由此,绝缘层的表面中的与半导体基板的第2表面相对的第3区域及到达至贯通孔的第2开口的第2区域所成的角度成为较半导体基板的第2表面与贯通孔的内表面所成的角度大(即平缓)。因此,无论在制造时或制造后,均防止在贯通孔的第2开口部分的第2配线的断线。另外,与例如将绝缘层沿着贯通孔的内表面以均匀的厚度形成的情形相比,第2区域的倾斜成为平缓,故可容易且确实地形成第2配线。进而,可不依存于贯通孔的内表面的形状而形成第2配线,故即使在例如在贯通孔的内表面残留有尖锐的部分的情况下,也可防止起因于此种部分的第2配线的断线。另外,第2区域的平均倾斜角度成为较第1区域的平均倾斜角度小。换言之,到达至贯通孔的第1开口的第1区域的平均倾斜角度成为较第2区域的平均倾斜角度大。由此,即使在例如将贯通孔小径化的情况下,也可充分地确保半导体基板的第1表面侧的绝缘层的开口的宽度。因此,无论在制造时或制造后,均可防止在绝缘层的开口部分的第1配线与第2配线的断线。进而,在绝缘层的表面,第4区域以将第1区域与第2区域连续地连接的方式弯曲,且第5区域以将第2区域与第3区域连续地连接的方式弯曲。因此,无论在制造时或制造后,均防止在绝缘层的表面的整个区域的第2配线的断线。尤其在制造后,在绝缘层的表面的整个区域将应力集中进行缓和,故对于第2配线的断线的防止较有效。通过以上,根据该半导体装置,可将半导体基板的经由贯通孔的电连接确实化。另,在贯通孔的内表面的平均倾斜角度也包含贯通孔的内表面(在贯通孔的内表面为圆柱面等的曲面的情况下,为其曲面的切平面)与半导体基板的第1表面正交,且贯通孔的内表面相对于第1表面成90°的角度的情形。
在本发明的一形态的半导体装置中,也可为第1区域的平均倾斜角度较第2区域的平均倾斜角度更接近贯通孔的内表面的平均倾斜角度。由此,可获得为了使位于贯通孔的第1表面侧的第1开口上的第1配线的一部分露出而具有充分的宽度的开口,其结果,无论在制造时或制造后,均可确实地防止在绝缘层的开口部分的第1配线与第2配线的断线。
在本发明的一形态的半导体装置中,设置在贯通孔的内表面的绝缘层的平均厚度也可较设置于第2表面的绝缘层的平均厚度大。由此,在例如将半导体基板薄型化的情况下,设置在贯通孔的内表面的绝缘层也作为补强层发挥功能,故可充分确保贯通孔周边部分的强度。
在本发明的一形态的半导体装置中,第1区域也可为设置在贯通孔的内表面的绝缘层中的具有半导体基板的厚度与设置于第2表面的绝缘层的平均厚度的和的2/3以下的高度的部分的表面。由此,在绝缘层的表面中,将第1区域与第2区域平缓地连接,可确实地防止于第1区域与第2区域的边界的第2配线的断线。
在本发明的一形态的半导体装置中,第1区域也可为设置在贯通孔的内表面的绝缘层中的具有半导体基板的厚度与设置于第2表面的绝缘层的平均厚度的和的1/2以下的高度的部分的表面。由此,在绝缘层的表面中,将第1区域与第2区域进一步平缓地连接,可进一步确实地防止于第1区域与第2区域的边界的第2配线的断线。
在本发明的一形态的半导体装置中,第4区域也可为具有朝与贯通孔的内表面相反的一侧凸的最大曲率的区域。此种绝缘层的形状在将半导体基板的经由贯通孔的电连接确实化方面尤其有效。
在本发明的一形态的半导体装置中,贯通孔的内表面也可为自第1表面向第2表面扩大的锥状的面,或,贯通孔的内表面(在贯通孔的内表面为圆柱面等的曲面的情况下,为其曲面的切平面)也可为与第1表面及第2表面正交的面。在任一者的情况下,均可将半导体基板的经由贯通孔的电连接确实化。
在本发明的一形态的半导体装置中,绝缘层也可包含树脂。由此,可容易且确实地形成具有上述的形状的绝缘层。
本发明的一形态的半导体装置的制造方法为制造上述半导体装置的方法,且包含:第1工序,其在具有彼此相对的第1表面及第2表面的半导体基板的第1表面设置第1配线;第2工序,其在半导体基板形成自第1表面到达至第2表面的贯通孔,且在贯通孔的第1表面侧的第1开口使第1配线的一部分露出;第3工序,其在贯通孔的内表面及第2表面,设置经由贯通孔的第2表面侧的第2开口而连续的绝缘层;第4工序,其在绝缘层形成接触孔,且在绝缘层的第1表面侧的开口使第1配线的一部分露出;及第5工序,其在绝缘层的表面设置第2配线,且在绝缘层的第1表面侧的开口中将第1配线与第2配线电连接。
根据该半导体装置的制造方法,可效率良好地制造将半导体装置的经由贯通孔的电连接确实化的半导体装置。
在本发明的一形态的半导体装置的制造方法中,在第3工序中,也可使用具有10cp以上的粘度的树脂材料而实施浸渍涂布法,由此在贯通孔的内表面及第2表面设置绝缘层。由此,可容易且确实地获得具有上述的形状的绝缘层。
在本发明的一形态的半导体装置的制造方法中,也可在第3工序中,使用正型的树脂材料,在贯通孔的内表面及第2表面设置绝缘层,且在第4工序中,将在绝缘层中与接触孔对应的部分曝光及显影,由此在绝缘层形成接触孔。由此,可容易且确实地获得具有上述的形状的绝缘层。
发明的效果
根据本发明,可提供一种可将半导体基板的经由贯通孔的电连接确实化的半导体装置,及此种半导体装置的制造方法。
附图说明
图1为本发明的一实施方式的半导体装置的剖视图。
图2为图1的半导体装置的贯通孔及其周边部分的剖视图。
图3(a)及(b)为用以说明图1的半导体装置的制造方法的多个工序的剖视图。
图4(a)及(b)为用以说明图1的半导体装置的制造方法的多个工序的剖视图。
图5(a)及(b)为用以说明图1的半导体装置的制造方法的多个工序的剖视图。
图6为图1的半导体装置的变形例的部分剖视图。
图7为图1的半导体装置的变形例的部分剖视图。
图8为图1的半导体装置的变形例的部分剖视图。
图9为图1的半导体装置的贯通孔及其周边部分的变形例的剖视图。
具体实施方式
以下,对本发明的实施方式,参照图式详细地进行说明。另,在各图中对相同或相当部分标注相同符号,且省略重复的说明。
如图1所示那样,半导体装置1具备具有彼此相对的第1表面2a及第2表面2b的半导体基板2。半导体装置1为例如硅光电二极管等的光装置。在半导体装置1中,例如在由n型的硅构成的半导体基板2内的第1表面2a侧的特定区域,设置有选择性扩散有p型的杂质的p型区域2c。在半导体基板2的第1表面2a,例如由铝构成的第1配线3介由氧化膜4而设置。在氧化膜4中与第1配线3的焊垫部3a对应的部分,形成有开口4a。在氧化膜4中与p型区域2c的端部对应的部分,形成有开口4b。第1配线3经由开口4b而电连接于p型区域2c。另,也可取代氧化膜4,而设置SiN等由其他的绝缘材料构成的绝缘膜。
在半导体基板2的第1表面2a,配置有由玻璃等的光透过型材料构成的光透过基板5。半导体基板2与光透过基板5通过包含光学粘合剂的粘合层6光学性且物理性连接。在半导体装置1中,经由光透过基板5及粘合层6而在p型区域2c入射光。另,半导体基板2的厚度较光透过基板5的厚度小(薄)。作为一例,半导体基板2的厚度为数十μm左右,光透过基板5的厚度为数百μm左右。
在半导体基板2,形成自第1表面2a到达至第2表面2b的贯通孔7。贯通孔7的第1开口7a位于半导体基板2的第1表面2a,贯通孔7的第2开口7b位于半导体基板2的第2表面2b。第1开口7a与氧化膜4的开口4a连续,且由第1配线3的焊垫部3a覆盖。贯通孔7的内表面7c自第1表面2a朝第2表面2b扩大的锥状的面。例如,贯通孔7形成为自第1表面2a朝第2表面2b扩大的四角形锥台状。另,在自与贯通线7的中心线CL平行的方向观察的情况下,贯通孔7的第1开口7a的边缘与氧化膜4的开口4a的边缘不必一致,例如氧化膜4的开口4a的边缘也可相对在贯通孔7的第1开口7a的边缘而位于内侧。
贯通孔7的纵横比为0.2~10。所谓纵横比,是贯通孔7的深度(第1开口7a与第2开口7b的距离)除以第2开口7b的宽度(在第2开口7b为矩形的情况下为第2开口7b的对边间的距离,在第2开口7b为圆形的情况下为第2开口7b的直径)的值。作为一例,贯通孔7的深度为30μm,且第2开口7b的宽度为130μm。该情况下,纵横比成为0.23。
在贯通孔7的内表面7c及半导体基板2的第2表面2b,设置有绝缘层10。绝缘层10经由贯通孔7的第2开口7b而连续。绝缘层10在贯通孔7的内侧,经由氧化膜4的开口4a而到达至第1配线3的焊垫部3a,且在半导体基板2的第1表面2a侧具有开口10a。
在绝缘层10的表面10b(与贯通孔7的内表面7c及半导体基板2的第2表面2b相反的一侧的表面),设置有例如由铝构成的第2配线8。第2配线8在绝缘层10的开口10a中电连接于第1配线3的焊垫部3a。进而,在绝缘层10的表面10b(与半导体基板2的第2表面2b相反的一侧的表面),设置有例如由铝构成的第3配线22。第3配线22在形成在绝缘层10的开口10c中电连接于半导体基板2的第2表面2b。
第2配线8及第3配线22由树脂保护层21覆盖。在树脂保护层21中与贯通孔7对应的部分,形成有具有平滑的内表面的较浅的凹部21a。在树脂保护层21中与第2配线8的焊垫部8a对应的部分,形成有使焊垫部8a露出的开口21b。在树脂保护层21中与第3配线22的焊垫部22a对应的部分,形成有使焊垫部22a露出的开口21c。在树脂保护层21的开口21b,配置有凸块电极即取出电极9。取出电极9电连接于第2配线8的焊垫部8a。在树脂保护层21的开口21c,配置有凸块电极即取出电极23。取出电极23电连接于第3配线22的焊垫部22a。半导体装置1经由取出电极9及取出电极23而安装于电路基板,且取出电极9及取出电极23分别作为阳极电极及阴极电极而发挥功能。另,也可代替树脂保护层21,设置包含其他的绝缘材料的保护层(例如,氧化膜、氮化膜等)。另外,树脂保护层21的厚度可为与绝缘层10的厚度相同程度,或,也可设为较绝缘层10的厚度小。尤其,若树脂保护层21的厚度为与绝缘层10的厚度相同程度,则可降低作用于第2配线8及第3配线22的应力。
对上述的绝缘层10,一面参照图2,一面更详细地进行说明。另,在图2中,省略光透过基板5、粘合层6、取出电极9及树脂保护层21。
如图2所示那样,绝缘层10的表面10b包含:第1区域11,其在贯通孔7的内侧到达至第1开口7a;第2区域12,其在贯通孔7的内侧到达至第2开口7b;及第3区域13,其在贯通孔7的外侧与半导体基板2的第2表面2b相对。
第1区域11自半导体基板2的第1表面2a向第2表面2b扩大的锥状的区域。第1区域11具有平均倾斜角度α。所谓第1区域11的平均倾斜角度α,为关于包含贯通孔7的中心线CL的平面,着眼于中心线CL的一侧的区域的情况下,该平面与第1区域11的交线相对于第1表面2a所成的角度的平均值。在该交线为直线的情况下,该直线与第1表面2a所成的角度成为第1区域11的平均倾斜角度α。在该交线为曲线的情况下,该曲线的切线与第1表面2a所成角度的平均值,成为第1区域11的平均倾斜角度α。第1区域11的平均倾斜角度α大于0°且小于90°。
第2区域12自半导体基板2的第1表面2a向第2表面2b扩大的锥状的区域。第2区域12具有平均倾斜角度β。所谓第2区域12的平均倾斜角度β,为关于包含贯通孔7的中心线CL的平面,着眼于中心线CL的一侧的区域的情况下,该平面与第2区域12的交线相对于第1表面2a所成的角度的平均值。在该交线为直线的情况下,该直线与第1表面2a所成的角度成为第2区域12的平均倾斜角度β。在该交线为曲线的情况下,该曲线的切线与第1表面2a所成角度的平均值,成为第2区域12的平均倾斜角度β。第2区域12的平均倾斜角度β大于0°且小于90°。
第2区域12的平均倾斜角度β小于第1区域11的平均倾斜角度α。即,第2区域12为具有较第1区域11平缓的倾斜的区域。另外,第2区域12的平均倾斜角度β小于贯通孔7的内表面7c的平均倾斜角度γ。即,第2区域12具有较贯通孔7的内表面7c平缓的倾斜的区域。在本实施方式中,第1区域11的平均倾斜角度α较第2区域12的平均倾斜角度β更接近贯通孔7的内表面7c的平均倾斜角度γ。此处,第1区域11的平均倾斜角度α>贯通孔7的内表面7c的平均倾斜角度γ>第2区域12的平均倾斜角度β。所谓贯通孔7的内表面7c的平均倾斜角度γ,为关于包含贯通孔7的中心线CL的平面,着眼于中心线CL的一侧的区域的情况下,该平面与内表面7c的交线相对于第1表面2a所成的角度的平均值。在该交线为直线的情况下,该直线与第1表面2a所成的角度成为贯通孔7的内表面7c的平均倾斜角度γ。在该交线为曲线的情况下,该曲线的切线与第1表面2a所成角度的平均值成为贯通孔7的内表面7c的平均倾斜角度γ。
绝缘层10的表面10b进而包含:第4区域14,其具有朝与贯通孔7的内表面7c相反的一侧凸的最大曲率;及第5区域15,其沿着贯通孔7的第2开口7b的边缘。所谓朝与贯通孔的内表面7c相反的一侧凸的最大曲率,为在关于包含贯通线7的中心线CL的平面,着眼于中心线CL的一侧的区域的情况下,在该平面与表面10b的交线中的朝与贯通孔7的内表面7c相反的一侧凸状地弯曲的部分的曲率的最大值。另,第1区域11为在设置在贯通孔7的内表面7c的绝缘层10的表面10b中的较第4区域14更接近贯通孔7的第1开口7a侧(与贯通孔7的中心线CL平行的方向的第1开口7a侧)的区域。第2区域12设置在贯通孔7的内表面7c的绝缘层10的表面10b中的较第4区域14更接近贯通孔7的第2开口7b侧(与贯通孔7的中心线CL平行的方向的第2开口7b侧)的区域(即,第4区域14与第5区域15之间的区域)。
第4区域14以与第1区域11与第2区域12连续地连接的方式弯曲。即,第4区域14为带有圆角的曲面,且将第1区域11与第2区域12平滑地连接。此处,若假定第4区域14不存在,且使第1区域11朝半导体基板2的第2表面2b侧延伸,使第2区域12朝半导体基板2的第1表面2a侧延伸,则通过第1区域11与第2区域12形成交线(角、弯曲部位)。第4区域14为相当于将该交线(角、弯曲部位)进行R倒角时形成的曲面。第4区域14为在关于包含贯通孔7的中心线CL的平面,着眼于中心线CL的一侧的区域的情况下,该平面与表面10b的交线中的在与第1区域11对应的部分及与第2区域12对应的部分之间、朝与贯通孔7的内表面7c相反的一侧凸状地弯曲的部分。
第5区域15以将第2区域12与第3区域13连续地连接的方式弯曲。即,第5区域15为带有圆角的曲面,且将第2区域12与第3区域13平滑地连接。此处,若假定第5区域15不存在,且使第2区域12朝半导体基板2的第2表面2b侧延伸,使第3区域13朝贯通孔7的中心线CL延伸,则通过第2区域12与第3区域13形成交线(角、弯曲部位等)。第5区域15相当于将该交线(角、弯曲部位等)进行R倒角时形成的曲面。第5区域15为在关于包含贯通孔7的中心线CL的平面,着眼于中心线CL的一侧的区域的情况下,该平面与表面10b的交线中的与第2区域12对应的部分及与第3区域13对应的部分之间,朝与贯通孔7的第2开口7b的边缘相反的一侧凸状地弯曲的部分。
在本实施方式中,第1区域11、第4区域14及第5区域15为朝与贯通孔7的内表面7c相反的一侧凸状地弯曲的曲面。第2区域12为在贯通孔7的内表面7c侧凸状地弯曲的曲面(即,若自与贯通孔7的内表面7c相反的一侧观察,则凹状地弯曲的曲面)。第3区域13为与半导体基板2的第2表面2b大致平行的平面。如上述那样,第4区域14以将第1区域11与第2区域12连续地连接的方式弯曲,且第5区域15以将第2区域12与第3区域13连续地连接的方式弯曲,故绝缘层10的表面10b成为连续的面(不存在面与面的交线(角、弯曲部位等)等不连续部位,各区域11、12、13、14、15为平滑地连接的面)。
设置在贯通孔7的内表面7c的绝缘层10的平均厚度大于设置于半导体基板2的第2表面2b的绝缘层10的平均厚度。设置在贯通孔7的内表面7c的绝缘层10的平均厚度,为在与内表面7c垂直的方向的绝缘层10的厚度的平均值。所谓设置于半导体基板2的第2表面2b的绝缘层10的平均厚度,为在与第2表面2b垂直的方向的绝缘层10的厚度的平均值。
在半导体基板2的与第1表面2a及第2表面2b平行的方向上,绝缘层10中的与第1区域11对应的部分的平均厚度较树脂绝缘层10中的与第2区域12对应的部分的平均厚度大。在半导体基板2的与第1表面2a及第2表面2b平行的方向上,所谓与绝缘层10中的与第1区域11对应的部分的平均厚度,为在该方向的第1区域11与贯通孔7的内表面7c的距离的平均值。在半导体基板2的与第1表面2a及第2表面2b平行的方向上,所谓绝缘层10中的与第2区域12对应的部分的平均厚度,为该方向的第2区域12与贯通孔7的内表面7c的距离的平均值。
在绝缘层10中,第1区域11设置在贯通孔7的内表面7c的绝缘层10中的自半导体基板2的第1表面2a具有高度H的部分的表面。高度H为半导体基板2的厚度(即,第1表面2a与第2表面2b的距离)与设置于半导体基板2的第2表面2b的绝缘层10的平均厚度的和D的1/2以下。
在绝缘层10中,将通过绝缘层10的开口10a的边缘及贯通孔7的第2开口7b的边缘的面S设为边界面,若着眼于相对于面S的贯通孔7的内表面7c侧的部分P1、及相对于面S的与贯通孔7的内表面7c相反的一侧的部分P2,则部分P1的体积大于部分P2的体积。另外,在绝缘层10中,若对包含贯通孔7的中心线CL的平面,着眼于中心线CL的一侧的区域,则三角形T1的面积较三角形T2的面积大。三角形T1为在包含贯通孔7的中心线CL的平面中(即,在图2的剖面中),将贯通孔7的第1开口7a的边缘、贯通孔7的第2开口7b的边缘、及绝缘层10的开口10a的边缘设为顶点的三角形。三角形T2为在包含贯通孔7的中心线CL的平面中(即,图2的剖面中),将绝缘层10的开口10a的边缘、贯通孔7的第2开口7b的边缘、及第4区域14的顶部设为顶点的三角形。
如以上说明那样,在半导体装置1中,绝缘层10的表面10b中,到达至贯通孔7的第1开口7a的第1区域11、及到达至贯通孔7的第2开口7b的第2区域12为自半导体基板2的第1表面2a向第2表面2b扩大的锥状的区域。且,第2区域12的平均倾斜角度较贯通孔7的内表面7c的平均倾斜角度小。由此,绝缘层10的表面10b中的与半导体基板2的第2表面2b相对的第3区域13及到达至贯通孔7的第2开口7b的第2区域12所成的角度成为较半导体基板2的第2表面2b与贯通孔7的内表面7c所成的角度大(即平缓)。由此,无论在制造时或制造后,均可防止在贯通孔7的第2开口7b部分的第2配线8的断线。另外,与例如绝缘层10沿着贯通孔7的内表面7c以均匀的厚度形成的情形相比第2区域12的倾斜成为平缓,故可容易且确实地形成第2配线8。进而,可不依存于贯通孔7的内表面7c的形状而形成第2配线8,故例如在贯通孔7的内表面7c残存有尖锐部分的情况下,也可防止起因于此种部分的第2配线8的断线。另外,第2区域12的平均倾斜角度成为较第1区域11的平均倾斜角度小。换言的,到达至贯通孔7的第1开口7a的第1区域11的平均倾斜角度大于第2区域12的平均倾斜角度。由此,即使于例如将贯通孔7小径化的情况下,也可充分地确保半导体基板2的第1表面2a侧的绝缘层10的开口10a的宽度。因此,无论在制造时或制造后,均可防止在绝缘层10的开口10a部分的第1配线3与第2配线8的断线。进而,在绝缘层10的表面10b中,第4区域14以将第1区域11与第2区域12连续地连接的方式弯曲,第5区域15以将第2区域12与第3区域13连续地连接的方式弯曲。因此,无论制造时或制造后,均可防止在绝缘层10的表面10b的整个区域的第2配线8的断线。尤其在制造后,可在绝缘层10的表面10b的整个区域缓和应力集中,故对于第2配线8的断线的防止较有效。通过以上,根据半导体装置1,可将半导体基板2的经由贯通孔7的电连接确实化。
在半导体装置1中,绝缘层10的表面10b成为连续的面(不存在面与面的交线(角、弯曲部位等)等不连续部位,各区域11、12、13、14、15为平滑地连接的面)。由此,可缓和应力集中而防止第2配线8的断线。
在半导体装置1中,第1区域11的平均倾斜角度较第2区域12的平均倾斜角度更接近贯通孔7的内表面7c的平均倾斜角度。由此,可获得为了使第1配线3的焊垫部3a露出而具有充分的宽度的开口10a,其结果,无论在制造时或制造后,均可确实地防止在绝缘层10的开口10a部分的第1配线3与第2配线8的断线。
在半导体装置1中,成为第1区域11的平均倾斜角度α>贯通孔7的内表面7c的平均倾斜角度γ>第2区域12的平均倾斜角度β。由此,可防止第2配线8的断线,且可获得为了使第1配线3的焊垫部3a露出而具有充分的宽度的开口10a。
在半导体装置1中,设置在贯通孔7的内表面7c的绝缘层10的平均厚度成为大于设置于第2表面2b的绝缘层10的平均厚度。由此,即使在例如将半导体基板2薄型化的情况下,设置在贯通孔7的内表面7c的绝缘层10作为补强层发挥功能,故也可充分地确保贯通孔7周边部分的强度。另外,可将第1区域11的平均倾斜角度及第2区域12的平均倾斜角度设为期望的角度,可获得表面10b成为连续的面(不存在面与面的交线(角、弯曲部位等)等不连续部位,各区域11、12、13、14、15为平滑地连接的面)的绝缘层10。例如在绝缘层10为沿着贯通孔7的内表面7c而以均匀的厚度形成的情况下,不可能获得表面10b成为连续的面的绝缘层10。
在半导体装置1中,在半导体基板2的与第1表面2a及第2表面2b平行的方向上,绝缘层10中的与第1区域11对应的部分的平均厚度较绝缘层10中的与第2区域12对应的部分的平均厚度大。由此,可获得具有难以产生第2配线8的断线且难以产生第1配线3与第2配线8的断线的形状的绝缘层10。
在半导体装置1中,即使例如在贯通孔7的第2开口7b的边缘残存有突起(overhang)等,该突起等也被绝缘层10覆盖,成为在凸状地弯曲的曲面即第5区域15设置第2配线8。由此,可确实地防止在贯通孔7的第2开口7b部分的第2配线8的断线。
在半导体装置1中,设置在贯通孔7的内表面7c的绝缘层10中的具有半导体基板2的厚度与设置于第2表面2b的绝缘层10的平均厚度的和D的1/2以下的高度H的部分的表面成为第1区域11。由此,在绝缘层10的表面10b,平缓地连接第1区域11与第2区域12,而可确实地防止于第1区域11与第2区域12的边界的第2配线8的断线。
在半导体装置1的绝缘层10中,将通过绝缘层10的开口10a的边缘及贯通孔7的第2开口7b的边缘的面S设为边界面,若着眼于相对于面S的贯通孔7的内表面侧7c侧的部分P1、及相对于面S的与贯通孔7的内表面7c相反的一侧的部分P2,则部分P1的体积大于部分P2的体积。另外,关于包含贯通孔7的中心线CL的平面,若着眼于中心线CL的一侧的区域,则三角形T1的面积大于三角形T2的面积。即使通过这些,在绝缘层10的表面10b中,也可平缓地连接第1区域11与第2区域12,而可确实地防止于第1区域11与第2区域12的边界的第2配线8的断线。
在半导体装置1中,在设置在贯通孔7的内表面7c的绝缘层10的表面10b中的具有朝与贯通孔7的内表面7c相反侧凸的最大曲率的第4区域14更接近第1开口7a侧的区域成为第1区域11,较第4区域14更接近第2开口7b侧的区域成为第2区域12。此种绝缘层10的形状在将半导体基板2的经由贯通孔7的电连接确实化方面尤其有效。
在半导体装置1中,贯通孔7的内表面7c为自第1表面2a向第2表面2b扩大的锥状的面。在该情况下,也可将半导体基板2的经由贯通孔7的电连接确实化。
在半导体装置1中,绝缘层10包含树脂。由此,可容易且确实地形成具有上述的形状的绝缘层10。
接着,关于上述的半导体装置1的制造方法,一面参照图3~图5进行说明。首先,准备半导体基板2,且在半导体基板2的第1表面2a构成装置(即,在第1表面2a设置氧化膜4、第1配线3等)(第1工序)。然后,在半导体基板2的第1表面2a经由粘合层6而安装光透过基板5。
接着,如图3(a)所示那样,通过各向异性的湿式蚀刻在半导体基板2形成贯通孔7,进而,如图3(b)所示那样,在氧化膜4中去除与第1配线3的焊垫部3a对应的部分,而在氧化膜4形成开口4a。由此,在贯通孔7的第1开口7a使第1配线3的焊垫部3a露出(第2工序)。另,在自与贯通孔7的中心线CL平行的方向观察的情况下,不一定要以贯通孔7的第1开口7a的边缘与氧化膜4的开口4a的边缘一致的方式于氧化膜4形成开口4a,也可以例如氧化膜4的开口4a的边缘相对在贯通孔7的第1开口7a的边缘而位于内侧的方式在氧化膜4形成开口4a。
接着,准备具有10cp以上的粘度且正型的树脂材料,使用该树脂材料而实施浸渍涂布法(使对象物浸渍于树脂涂料,且将对象物自树脂涂料上拉,由此在对象物形成树脂层的方法),由此如图4的(a)所示那样,在贯通孔7的内表面7c及半导体基板2的第2表面2b设置绝缘层10(第3工序)。由此,在绝缘层10形成具有追随于第2区域12、第3区域13及第5区域15的内表面的凹部17。另,作为树脂材料,可使用例如酚醛树脂、聚酰亚胺树脂、及环氧树脂等。
接着,如图4(b)所示那样,在设置于半导体基板2的第2表面2b的绝缘层10上配置掩模30。掩模30于与第1配线3的焊垫部3a相对的位置具有光透过部31,在光透过部31的周围具有遮光部32。接着,在绝缘层10中与接触孔16对应的部分,经由掩模30的光透过部31而照射光,且将该部分曝光。进而,在绝缘层10中将与接触孔16对应的部分显影,由此在绝缘层10形成接触孔16。由此,在绝缘层10的开口10a使第1配线3的焊垫部3a露出(第4工序)。另,在形成接触孔16时,也可并用灰化处理等。
在曝光时,在掩模30的光透过部31及在绝缘层10中与接触孔16对应的部分之间,通过形成在绝缘层10的凹部17而形成间隙。由此,光衍射而照射至绝缘层10。因此,在显影时,形成具有自半导体基板2的第1表面2a向第2表面2b扩大的锥状的追随于第1区域11、及第2区域12的内表面的接触孔16。
接着,如图5(a)所示那样,通过例如使用铝而实施溅镀法,由此在绝缘层10的表面10b设置第2配线8,且在绝缘层10的开口10a中将第1配线3与第2配线8电连接(第5工序)。此时,接触孔16具有自半导体基板2的第1表面2a向第2表面2b扩大的锥状的追随于第1区域11的内表面,故在该内表面确实地形成金属膜,且进而在绝缘层10的开口10a中将第1配线3与第2配线8确实地连接。
接着,例如使用与绝缘层10相同的树脂材料而实施浸渍涂布法,由此如图5(b)所示那样,以树脂保护层21覆盖第2配线8。最后,在未被树脂保护层21覆盖的第2配线8的焊垫部8a配置取出电极9,获得上述的半导体装置1。
根据上述半导体装置1的制造方法,可效率良好地制造将半导体基板2的经由贯通孔7的电连接确实化的半导体装置1。
在上述半导体装置1的制造方法中,使用具有10cp以上的粘度的树脂材料而实施浸渍涂布法,由此在贯通孔7的内表面7c及半导体基板2的第2表面2b设置绝缘层10。由此,可容易且确实地获得具有上述的形状的绝缘层10。
另,在浸渍涂布法,一般而言使用粘性较低的树脂材料(例如使用于防水涂层的树脂材料等,例如具有1cp以下的粘度的树脂材料)。然而,即使使用此种树脂材料而实施浸渍涂布法,绝缘层10也沿着贯通孔7的内表面7c而以大致均匀的厚度形成。因此,在上述半导体装置1的制造方法中,通过使用具有10cp以上的粘度的树脂材料而实施浸渍涂布法,可容易且确实地获得具有上述的形状的绝缘层10。
在上述半导体装置1的制造方法中,使用正型的树脂材料,而在贯通孔7的内表面7c及半导体基板2的第2表面2b设置绝缘层10。然后,将在绝缘层10中与接触孔16对应的部分曝光及显影,由此在绝缘层10形成接触孔16。由此,可容易且确实地获得具有上述的形状的绝缘层10。另,在曝光及显影的时,通过形成在绝缘层10的凹部17,在绝缘层10中与接触孔16对应的部分的厚度变薄(即,与接触孔16对应的部分为绝缘层10中的具有半导体基板2的厚度与设置于第2表面2b的绝缘层10的平均厚度的和D的1/2以下的高度H的部分),故可容易且确实地获得具有期望的形状的接触孔16。
在上述半导体装置1的制造方法中,以在半导体基板2安装有光透过基板5的状态,实施浸渍涂布法。因此,可使用薄型化的半导体基板2。在薄型化的半导体基板2中,由在贯通孔7的深度变小,故即使通过使用10cp以上等具有较高的粘度的树脂材料的浸渍涂布法而绝缘层10变厚,也可在绝缘层10容易且确实地形成接触孔16。
以上,对本发明的一实施方式进行说明,但本发明并非限定于上述实施方式。例如,绝缘层10也可由树脂以外的绝缘材料形成。另外,在上述实施方式中,贯通孔7的第1开口7a由第1配线3的焊垫部3a覆盖,但只要第1配线3的一部分位于第1开口7a上即可,第1配线3也可不覆盖第1开口7a的整个区域。
另外,在上述实施方式中,第1区域11的平均倾斜角度较第2区域12的平均倾斜角度更接近贯通孔7的内表面7c的平均倾斜角度,但也可为第2区域12的平均倾斜角度较第1区域11的平均倾斜角度更接近贯通孔7的内表面7c的平均倾斜角度。
另外,如图6所示那样,也可不在半导体基板2的第1表面2a经由粘合层6安装光透过基板5。在该情况下,在第1表面2a,以覆盖第1配线3的方式设置氧化膜18。如此,在半导体基板2未安装有光透过基板5的情况下,在绝缘层10中自第1表面2a具有高度H的部分作为补强层发挥功能,故自充分地确保贯通孔7周边部分的强度的角度而言尤其有效。
另外,如图7及图8所示那样,也可以取出电极9自半导体基板2的第2表面2b突出的方式配置在贯通孔7的内侧。在该情况下,如图7所示那样,也可在半导体基板2的第1表面2a经由粘合层6安装光透过基板5,或如图8所示那样,也可不在半导体基板2的第1表面2a经由粘合层6而安装光透过基板5。
另外,如图9所示那样,在贯通孔7的内表面7c(在贯通孔7的内表面7c为圆柱面等的曲面的情况下,为其曲面的切平面)也可为与第1表面2a及第2表面2b正交的面。在该情况下,也可将半导体基板2的经由贯通孔7的电连接确实化。此处,贯通孔7的纵横比为0.2~10。作为一例,贯通孔7的深度为40μm,第2开口7b的宽度为30μm。该情况下,纵横比成为1.3。另,具有圆柱状、四角柱状等的形状的贯通孔7通过例如干式蚀刻而形成。
关于图9所示的贯通孔7,第2区域12的平均倾斜角度β也较第1区域11的平均倾斜角度α小,且较贯通孔7的内表面7c的平均倾斜角度γ(在该情况下为90°)小。即,第2区域12为较第1区域11具有更平缓的倾斜,且较贯通孔7的内表面7c具有更平缓的倾斜的区域。另外,第1区域11的平均倾斜角度α较第2区域12的平均倾斜角度β更接近贯通孔7的内表面7c的平均倾斜角度γ。此处,成为贯通孔7的内表面7c的平均倾斜角度γ>第1区域11的平均倾斜角度α>第2区域12的平均倾斜角度β。由此,可防止第2配线8的断线,且可获得为了使第1配线3的焊垫部3a露出具有充分的宽度的开口10a。另外,绝缘层10的表面10b成为连续的面(不存在面与面的交线(角、弯曲部位等)等不连续部位,各区域11、12、13、14、15为平滑地连接的面)。另外,在绝缘层10中,将通过绝缘层10的开口10a的边缘及贯通孔7的第2开口7b的边缘的面S设为边界面,若着眼于相对于面S的贯通孔7的内表面7c侧的部分P1、及相对于面S的与贯通孔7的内表面7c相反的一侧的部分P2,则部分P1的体积大于部分P2的体积。另外,在绝缘层10中,若关于包含贯通孔7的中心线CL的平面,着眼于中心线CL的一侧的区域,则三角形T1的面积大于三角形T2的面积。另外,在半导体基板2的与第1表面2a及第2表面2b平行的方向上,绝缘层10中的与第1区域11对应的部分的平均厚度较绝缘层10中的与第2区域12对应的部分的平均厚度大。
另外,第1区域11也可为设置在贯通孔7的内表面7c的绝缘层10中的具有半导体基板2的厚度与设置于半导体基板2的第2表面2b的绝缘层10的平均厚度的和D的2/3以下的高度H的部分的表面10b(参照图9)。在该情况下,在绝缘层10的表面10b中,将第1区域11与第2区域12平缓地连接,可确实地防止于第1区域11与第2区域12的边界的第2配线8的断线。另,在曝光及显影的时,通过形成在绝缘层10的凹部17,在绝缘层10中与接触孔16对应的部分的厚度变薄(即,与接触孔16对应的部分为绝缘层10中的具有半导体基板2的厚度与设置于第2表面2b的绝缘层10的平均厚度的和D的2/3以下的高度H的部分),故可容易且确实地获得具有期望的形状的接触孔16。
另外,在上述半导体装置1的制造方法中,通过实施浸渍涂布法,在贯通孔7的内表面7c及半导体基板2的第2表面2b设置绝缘层10,但本发明并非限定于此。例如,也可通过实施使用树脂片的层压法、使用树脂涂料的旋转涂布法等其他的方法,在贯通孔7的内表面7c及半导体基板2的第2表面2b设置绝缘层10。
另外,在上述半导体装置1的制造方法中,使用正型的树脂材料,在贯通孔7的内表面7c及半导体基板2的第2表面2b设置绝缘层10,且将在绝缘层10中与接触孔16对应的部分进行曝光及显影,由此在绝缘层10形成接触孔16,但本发明并非限定于此。例如,也可使用负型的树脂材料,在贯通孔7的内表面7c及半导体基板2的第2表面2b设置绝缘层10。该情况下,也可将绝缘层10中与接触孔16对应的部分以外的部分曝光,且将在绝缘层10中与接触孔16对应的部分显影,由此在绝缘层10形成接触孔16。起因于光的衰减、光的衍射等,虽仅通过显影,可形成自半导体基板2的表面2b向第1表面2a扩大的锥状的接触孔16,通过进而实施热处理等,可获得自半导体基板2的第1表面2a向第2表面2b扩大的锥状的接触孔16。
另外,在上述实施方式中,在例如由n型的硅构成的半导体基板2内的第1表面2a侧的特定区域,设置有选择性扩散有p型的杂质的p型区域2c,但各导电型也可为相反。该情况下,取出电极9及取出电极23分别作为阴极电极及阳极电极发挥功能。进而,并非限定于在第1导电型(p型及n型的一者)的半导体基板2内形成第2导电型(p型及n型的另一者)的区域,也可在第1导电型(p型及n型的一者)的半导体基板2上形成第2导电型(p型及n型的另一者)的半导体层,也可在基板上形成第1导电型(p型及n型的一者)的半导体层,且在该第1导电型的半导体层上形成第2导电型(p型及n型的另一者)的半导体层。即,只要在半导体基板2的第1导电型的区域形成第2导电型的区域者即可。另外,在上述实施方式中,半导体装置1为例如硅光电二极管等的光装置,但半导体装置1可为其他的光装置,也可为电子装置等。
[产业上的可利用性]
根据本发明,可提供可将半导体基板的经由贯通孔的电连接确实化的半导体装置、及此种半导体装置的制造方法。
符号说明
1…半导体装置、2…半导体基板、2a…第1表面、2b…第2表面、3…第1配线、7…贯通孔、7a…第1开口、7b…第2开口、7c…内表面、8…第2配线、10…绝缘层、10a…开口、10b…表面、11…第1区域、12…第2区域、13…第3区域、14…第4区域、15…第5区域、16…接触孔。

Claims (12)

1.一种半导体装置,其特征在于,
具备:
半导体基板,其具有彼此相对的第1表面及第2表面,且形成有自所述第1表面到达至所述第2表面的贯通孔;
第1配线,其设置于所述第1表面,且一部分位于所述贯通孔的所述第1表面侧的第1开口上;
绝缘层,其设置于所述贯通孔的内表面及所述第2表面,且经由所述贯通孔的所述第2表面侧的第2开口而连续;及
第2配线,其设置于所述绝缘层的表面,且在所述绝缘层的所述第1表面侧的开口中与所述第1配线电连接,
所述绝缘层的所述表面包含:
在所述贯通孔的内侧到达至所述第1开口,且自所述第1表面向所述第2表面扩大的锥状的第1区域;
在所述贯通孔的内侧到达至所述第2开口,且自所述第1表面向所述第2表面扩大的锥状的第2区域;
在所述贯通孔的外侧与所述第2表面相对的第3区域;
以将所述第1区域与所述第2区域连续地连接的方式弯曲的第4区域;及
以将所述第2区域与所述第3区域连续地连接的方式弯曲的第5区域,
所述第2区域的平均倾斜角度较所述第1区域的平均倾斜角度小,且较所述贯通孔的所述内表面的平均倾斜角度小。
2.如权利要求1所述的半导体装置,其中,
所述第1区域的所述平均倾斜角度较所述第2区域的所述平均倾斜角度更接近所述贯通孔的所述内表面的平均倾斜角度。
3.如权利要求1或2所述的半导体装置,其中,
设置于所述贯通孔的所述内表面的所述绝缘层的平均厚度较设置于所述第2表面的所述绝缘层的平均厚度大。
4.如权利要求1至3中任一项所述的半导体装置,其中,
所述第1区域为,设置于所述贯通孔的所述内表面的所述绝缘层中的、具有所述半导体基板的厚度与设置于所述第2表面的所述绝缘层的平均厚度的和的2/3以下的高度的部分的表面。
5.如权利要求4所述的半导体装置,其中,
所述第1区域为,设置于所述贯通孔的所述内表面的所述绝缘层中的、具有所述半导体基板的厚度与设置于所述第2表面的所述绝缘层的平均厚度的和的1/2以下的高度的部分的表面。
6.如权利要求1至5中任一项所述的半导体装置,其中,
所述第4区域为具有朝与所述贯通孔的所述内表面相反的一侧凸的最大曲率的区域。
7.如权利要求1至6中任一项所述的半导体装置,其中,
所述贯通孔的所述内表面为自所述第1表面向所述第2表面扩大的锥状的面。
8.如权利要求1至6中任一项所述的半导体装置,其中,
所述贯通孔的所述内表面为与所述第1表面及所述第2表面正交的面。
9.如权利要求1至8中任一项所述的半导体装置,其中,
所述绝缘层由树脂构成。
10.一种半导体装置的制造方法,其为制造权利要求1至9中任一项所述的半导体装置的方法,
包括:
第1工序,在具有彼此相对的第1表面及第2表面的半导体基板的所述第1表面设置第1配线;
第2工序,在所述半导体基板形成自所述第1表面到达至所述第2表面的贯通孔,且在所述贯通孔的所述第1表面侧的第1开口使所述第1配线的一部分露出;
第3工序,在所述贯通孔的内表面及所述第2表面,设置经由所述贯通孔的所述第2表面侧的第2开口而连续的绝缘层;
第4工序,在所述绝缘层形成接触孔,且在所述绝缘层的所述第1表面侧的开口使所述第1配线的一部分露出;及
第5工序,在所述绝缘层的表面设置第2配线,且在所述绝缘层的所述第1表面侧的所述开口中将所述第1配线与所述第2配线电连接。
11.如权利要求10所述的半导体装置的制造方法,其中,
在所述第3工序中,使用具有10cp以上的粘度的树脂材料而实施浸渍涂布法,由此在所述贯通孔的所述内表面及所述第2表面设置所述绝缘层。
12.如权利要求10或11所述的半导体装置的制造方法,其中,
在所述第3工序中,使用正型的树脂材料,而在所述贯通孔的所述内表面及所述第2表面设置所述绝缘层,
在所述第4工序中,将在所述绝缘层中与所述接触孔对应的部分曝光及显影,由此在所述绝缘层中形成所述接触孔。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111289771A (zh) * 2018-12-10 2020-06-16 三菱电机株式会社 半导体装置的制造方法、半导体装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230169471A (ko) * 2015-03-31 2023-12-15 하마마츠 포토닉스 가부시키가이샤 반도체 장치
JP6725231B2 (ja) * 2015-10-06 2020-07-15 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、および電子装置
JP6552547B2 (ja) 2017-05-24 2019-07-31 三菱電機株式会社 赤外線センサおよび赤外線固体撮像装置
WO2019171581A1 (ja) * 2018-03-09 2019-09-12 シャープ株式会社 表示装置
US11635186B2 (en) * 2018-03-13 2023-04-25 Motherson Innovations Company Limited Polymeric substrate and a method of providing same
JP6878338B2 (ja) * 2018-03-14 2021-05-26 株式会社東芝 受光装置および受光装置の製造方法
CN112368602B (zh) * 2018-07-12 2023-03-14 深圳帧观德芯科技有限公司 具有高时间分辨率的光学雷达
JP7251946B2 (ja) * 2018-10-31 2023-04-04 浜松ホトニクス株式会社 固体撮像装置
WO2020161937A1 (ja) * 2019-02-05 2020-08-13 パナソニックIpマネジメント株式会社 センサ装置
JP7340965B2 (ja) 2019-06-13 2023-09-08 キヤノン株式会社 半導体装置およびその製造方法
WO2021039825A1 (ja) * 2019-08-28 2021-03-04 京セラ株式会社 発光素子搭載用パッケージおよび発光装置
JP7257978B2 (ja) * 2020-01-20 2023-04-14 三菱電機株式会社 半導体装置
US11322639B2 (en) * 2020-04-09 2022-05-03 Globalfoundries U.S. Inc. Avalanche photodiode

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59126643A (ja) * 1983-01-07 1984-07-21 Matsushita Electric Ind Co Ltd 電子回路の被覆方法
JPH08330295A (ja) * 1995-03-24 1996-12-13 Fuji Electric Co Ltd 半導体装置の製造方法
JP2005019521A (ja) * 2003-06-24 2005-01-20 Sanyo Electric Co Ltd 半導体装置の製造方法
EP1519410A1 (en) * 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
JP2006215062A (ja) * 2005-02-01 2006-08-17 Sharp Corp 液晶表示パネル、液晶表示装置、および液晶表示パネルの製造方法
CN101055867A (zh) * 2006-04-10 2007-10-17 株式会社东芝 半导体器件及其制造方法
US20080265442A1 (en) * 2007-04-26 2008-10-30 Sony Corporation Semiconductor device, electronic device, and method of producing semiconductor device
US20120068327A1 (en) * 2010-09-17 2012-03-22 Tessera Research Llc Multi-function and shielded 3d interconnects
CN102655136A (zh) * 2011-02-11 2012-09-05 海力士半导体有限公司 半导体芯片及其制造方法

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4830706A (en) * 1986-10-06 1989-05-16 International Business Machines Corporation Method of making sloped vias
JPH02268416A (ja) 1989-04-11 1990-11-02 Matsushita Electron Corp 半導体装置の製造方法及びそれに使用するフオトマスク
JPH0414830A (ja) 1990-05-08 1992-01-20 Fujitsu Ltd 半導体装置の製造方法
KR0127271B1 (ko) 1993-11-23 1998-04-02 김주용 반도체 소자의 금속배선 형성방법
JP3577913B2 (ja) * 1997-02-27 2004-10-20 セイコーエプソン株式会社 半導体装置、およびこれを具備する電子機器
JPH10307305A (ja) * 1997-03-07 1998-11-17 Toshiba Corp アレイ基板、液晶表示装置及びそれらの製造方法
JP2003007921A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置およびその製造方法
JP2003101222A (ja) 2001-09-21 2003-04-04 Sony Corp 薄膜回路基板装置及びその製造方法
JP2004057507A (ja) 2002-07-29 2004-02-26 Toshiba Corp X線検出装置、貫通電極の製造方法及びx線断層撮影装置
JP2004273561A (ja) * 2003-03-05 2004-09-30 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4250038B2 (ja) 2003-08-20 2009-04-08 シャープ株式会社 半導体集積回路
JP2005101268A (ja) 2003-09-25 2005-04-14 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2005158907A (ja) * 2003-11-25 2005-06-16 Mitsui Chemicals Inc 配線板の製造方法
JP2007105859A (ja) 2005-10-17 2007-04-26 Canon Inc 配向性メソ構造体膜、配向性メソポーラス物質膜、及びその製造方法、及びそれを用いた半導体素子
CN101379615B (zh) 2006-02-01 2013-06-12 皇家飞利浦电子股份有限公司 盖革式雪崩光电二极管
JP2007305955A (ja) 2006-04-10 2007-11-22 Toshiba Corp 半導体装置及びその製造方法
JP2007305960A (ja) * 2006-04-14 2007-11-22 Sharp Corp 半導体装置およびその製造方法
CN101449377B (zh) 2006-05-19 2011-04-20 住友电木株式会社 半导体器件
JP5155536B2 (ja) * 2006-07-28 2013-03-06 一般財団法人電力中央研究所 SiC結晶の質を向上させる方法およびSiC半導体素子の製造方法
US20080036097A1 (en) 2006-08-10 2008-02-14 Teppei Ito Semiconductor package, method of production thereof and encapsulation resin
TW200915970A (en) 2007-09-27 2009-04-01 Sanyo Electric Co Circuit device, circuit module and outdoor equipment
WO2010032729A1 (ja) 2008-09-18 2010-03-25 国立大学法人東京大学 半導体装置の製造方法
JP5369608B2 (ja) * 2008-10-23 2013-12-18 富士電機株式会社 無停電電源装置および無停電電源装置の選択遮断方法
WO2010147187A1 (ja) 2009-06-18 2010-12-23 ローム株式会社 半導体装置
JP5423572B2 (ja) * 2010-05-07 2014-02-19 セイコーエプソン株式会社 配線基板、圧電発振器、ジャイロセンサー、配線基板の製造方法
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
JP5447316B2 (ja) * 2010-09-21 2014-03-19 株式会社大真空 電子部品パッケージ用封止部材、及び電子部品パッケージ
WO2012120653A1 (ja) 2011-03-08 2012-09-13 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
JP5791461B2 (ja) 2011-10-21 2015-10-07 浜松ホトニクス株式会社 光検出装置
JP5926921B2 (ja) 2011-10-21 2016-05-25 浜松ホトニクス株式会社 光検出装置
JP5832852B2 (ja) * 2011-10-21 2015-12-16 浜松ホトニクス株式会社 光検出装置
JP5810921B2 (ja) 2012-01-06 2015-11-11 凸版印刷株式会社 半導体装置の製造方法
US9006896B2 (en) 2012-05-07 2015-04-14 Xintec Inc. Chip package and method for forming the same
US8791578B2 (en) 2012-11-12 2014-07-29 Hong Kong Applied Science and Technology Research Institute Company Limited Through-silicon via structure with patterned surface, patterned sidewall and local isolation
JP2014110284A (ja) * 2012-11-30 2014-06-12 Ps4 Luxco S A R L 半導体装置の製造方法
KR102066087B1 (ko) * 2013-05-28 2020-01-15 엘지디스플레이 주식회사 플렉서블 표시장치 및 그의 제조방법
US9484325B2 (en) * 2013-10-09 2016-11-01 Invensas Corporation Interconnections for a substrate associated with a backside reveal
CN103762198B (zh) * 2013-12-31 2016-07-06 中国科学院微电子研究所 一种tsv填孔方法
JP2016058655A (ja) 2014-09-11 2016-04-21 株式会社ジェイデバイス 半導体装置の製造方法
JP2016062996A (ja) * 2014-09-16 2016-04-25 株式会社東芝 光検出器
US9659980B2 (en) 2014-12-19 2017-05-23 Sensl Technologies Ltd Semiconductor photomultiplier
KR20230169471A (ko) * 2015-03-31 2023-12-15 하마마츠 포토닉스 가부시키가이샤 반도체 장치
US9502350B1 (en) 2016-01-28 2016-11-22 International Business Machines Corporation Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59126643A (ja) * 1983-01-07 1984-07-21 Matsushita Electric Ind Co Ltd 電子回路の被覆方法
JPH08330295A (ja) * 1995-03-24 1996-12-13 Fuji Electric Co Ltd 半導体装置の製造方法
JP2005019521A (ja) * 2003-06-24 2005-01-20 Sanyo Electric Co Ltd 半導体装置の製造方法
EP1519410A1 (en) * 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
JP2006215062A (ja) * 2005-02-01 2006-08-17 Sharp Corp 液晶表示パネル、液晶表示装置、および液晶表示パネルの製造方法
CN101055867A (zh) * 2006-04-10 2007-10-17 株式会社东芝 半导体器件及其制造方法
US20080265442A1 (en) * 2007-04-26 2008-10-30 Sony Corporation Semiconductor device, electronic device, and method of producing semiconductor device
US20120068327A1 (en) * 2010-09-17 2012-03-22 Tessera Research Llc Multi-function and shielded 3d interconnects
CN102655136A (zh) * 2011-02-11 2012-09-05 海力士半导体有限公司 半导体芯片及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111289771A (zh) * 2018-12-10 2020-06-16 三菱电机株式会社 半导体装置的制造方法、半导体装置
US11148937B2 (en) 2018-12-10 2021-10-19 Mitsubishi Electric Corporation Method of manufacturing semiconductor device and semiconductor device

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