TWI594236B - 記憶體胞 - Google Patents
記憶體胞 Download PDFInfo
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- TWI594236B TWI594236B TW105102738A TW105102738A TWI594236B TW I594236 B TWI594236 B TW I594236B TW 105102738 A TW105102738 A TW 105102738A TW 105102738 A TW105102738 A TW 105102738A TW I594236 B TWI594236 B TW I594236B
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- 239000003990 capacitor Substances 0.000 claims description 241
- 239000000463 material Substances 0.000 claims description 202
- 239000000758 substrate Substances 0.000 claims description 28
- 229910052732 germanium Inorganic materials 0.000 claims description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 7
- 230000005684 electric field Effects 0.000 claims description 7
- 238000005192 partition Methods 0.000 claims description 7
- 229910052684 Cerium Inorganic materials 0.000 claims description 3
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 150000004770 chalcogenides Chemical class 0.000 claims description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 2
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims description 2
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 238000010276 construction Methods 0.000 description 35
- 230000010287 polarization Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 238000003491 array Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052726 zirconium Inorganic materials 0.000 description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 2
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000011575 calcium Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021644 lanthanide ion Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/008—Selection of materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- Microelectronics & Electronic Packaging (AREA)
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- Inorganic Chemistry (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Description
本文所揭示之實施例係針對記憶體胞。
記憶體係一類型之積體電路,且用於電腦系統中以儲存資料。可將記憶體製造成一或多個陣列之個別記憶體胞。可使用數位線(其亦可指稱位元線、資料線、感測線或資料/感測線)及存取線(其亦可指稱字線)來對記憶體胞寫入或自記憶體胞讀取。數位線可沿陣列之行導電地互連記憶體胞,且存取線可沿陣列之列導電地互連記憶體胞。可透過一數位線及一存取線之組合來唯一地定址各記憶體胞。
記憶體胞可為揮發性或非揮發性的。非揮發性記憶體胞可在較長時間段(其包含切斷電腦時)內儲存資料。揮發性記憶體耗散且因此在諸多例項中需要被每秒多次再新/重寫。無論如何,記憶體胞經組態以在至少兩個不同可選擇狀態中保存或儲存記憶體。在二進位系統中,將狀態視為一「0」或一「1」。在其他系統中,至少一些個別記憶體胞可經組態以儲存資訊之兩個以上位準或狀態。
一電容器係可用於一記憶體胞中之一類型之電子組件。一電容器具有由電絕緣材料分離之兩個電導體。作為一電場之能量可靜電地儲存於此材料內。一類型之電容器係一鐵電電容器,其具有鐵電材料作為絕緣材料之至少部分。鐵電材料之特徵在於具有兩個穩定極化狀態。鐵電材料之極化狀態可藉由施加適合程式化電壓來改變且在移除
該程式化電壓之後保持(至少達一段時間)。各極化狀態具有不同於另一極化狀態之一電荷儲存電容,且其可在無需使該極化狀態反轉之情況下理想地用於寫入(即,儲存)及讀取一記憶體狀態,直至期望使此極化狀態反轉。不太令人滿意的是,在具有鐵電電容器之某一記憶體中,讀取記憶體狀態之動作會使極化反轉。據此,在判定極化狀態之後,進行記憶體胞之一重寫以在其判定之後使記憶體胞即時進入預讀取狀態中。無論如何,併入一鐵電電容器之一記憶體胞理想地係非揮發性的,此歸因於形成電容器之一部分之鐵電材料之雙穩態特性。
一類型之記憶體胞具有與一鐵電電容器串聯電耦合之一選擇裝置。即使當選擇裝置閒置時(即,當非作用中或「切斷」時),電流通常透過選擇裝置來洩漏至相鄰基板材料。此導致鐵電電容器之相鄰電極處之電壓下降,因此在兩個電容器電極之間產生一電壓差。此導致當記憶體胞閒置時橫跨鐵電材料來施加一電場。即使此一電場較小,其會使鐵電材料中之個別偶極開始翻轉且一直至所有偶極被翻轉,因此擦除記憶體胞之一程式化狀態。此可在短時間內發生,藉此破壞或防止記憶體胞之非揮發性。
10‧‧‧記憶體胞/建構
10a‧‧‧記憶體胞
10b‧‧‧記憶體胞
10c‧‧‧記憶體胞
10d‧‧‧記憶體胞
10e‧‧‧記憶體胞
10f‧‧‧記憶體胞
11‧‧‧導電路徑
12‧‧‧選擇裝置
13‧‧‧組件/導電路徑
14‧‧‧電容器
14a‧‧‧電容器
14b‧‧‧電容器建構
14c‧‧‧電容器
14d‧‧‧電容器
14e‧‧‧電容器
14f‧‧‧電容器
16‧‧‧組件/導電路徑
18‧‧‧電容器電極
18c‧‧‧第二電容器電極/材料
18f‧‧‧第二電容器電極/材料
19‧‧‧鐵電材料
19a‧‧‧鐵電材料
19b‧‧‧鐵電材料
19c‧‧‧鐵電材料
19d‧‧‧鐵電材料
19e‧‧‧鐵電材料
19f‧‧‧鐵電材料
20‧‧‧電容器電極
20c‧‧‧第一電容器電極/材料
21‧‧‧材料
22‧‧‧本徵電流洩漏路徑
24‧‧‧電阻器
26‧‧‧平行電流洩漏路徑
26b‧‧‧平行路徑
26c‧‧‧平行電流洩漏路徑
26e‧‧‧平行電流洩漏路徑
26f‧‧‧平行電流洩漏路徑
28‧‧‧電阻器
30‧‧‧選擇裝置電流洩漏路徑
32‧‧‧電阻
34‧‧‧材料
34b‧‧‧材料
34c‧‧‧材料
34d‧‧‧材料
34e‧‧‧材料
34f‧‧‧材料
35‧‧‧橫向側
40‧‧‧基底
41‧‧‧表面
42‧‧‧壁
43‧‧‧側表面
44‧‧‧側表面
45‧‧‧壁
48‧‧‧環形物
50‧‧‧環形物
50f‧‧‧環形物
54‧‧‧基底
60‧‧‧表面
61‧‧‧表面
65‧‧‧立向最外表面
66‧‧‧立向最外表面
70‧‧‧環形物
圖1係根據本發明之一實施例之一記憶體胞之一示意圖。
圖2係根據本發明之一實施例之一記憶體胞之一部分之一示意性截面圖。
圖3係根據本發明之一實施例之一記憶體胞之一部分之一示意性截面圖。
圖4係根據本發明之一實施例之一記憶體胞之一部分之一示意性截面圖。
圖5係根據本發明之一實施例之一記憶體胞之一部分之一示意性截面圖。
圖6係圖5建構之一記憶體胞之一俯視圖。
圖7係根據本發明之一實施例之一記憶體胞之一部分之一示意性截面圖。
圖8係根據本發明之一實施例之一記憶體胞之一部分之一示意性截面圖。
圖9係根據本發明之一實施例之一記憶體胞之一部分之一示意性截面圖。
圖10係圖9建構之一記憶體胞之一俯視圖。
參考一示意圖1來展示及首先描述根據本發明之一實施例之一記憶體胞10。具有記憶體胞10之積體電路(圖中未展示)可具有相對於一記憶體陣列或子陣列而製造之數千個或數百萬個此等記憶體胞,且並非為本文之揭示內容之特別材料。此等陣列或子陣列可具有複數個存取線及選擇線,其等在其等之間之交叉處具有個別記憶體胞10。個別記憶體胞可被視為構成一個別存取線及一交叉個別選擇線之部分。
記憶體胞10包括一選擇裝置12及(例如)藉由一導電(即,電)路徑16來與選擇裝置12串聯(即,電路)電耦合之一電容器14,如圖中所展示。在所描繪之圖式中,電容器14可被視為包括兩個導電電容器電極18及20,其等具有介於其等之間之鐵電材料19。實體地,路徑16可僅為由電容器14及選擇裝置12共用之一單一電極。電容器14包括自電容器電極18或20之一者穿過鐵電材料19而至另一電容器電極之一本徵電流(即,電)洩漏路徑。為清楚起見,圖1中將此本徵路徑示意性地展示為圍繞鐵電材料19運行之一路徑22中之一虛線。然而,實際上,路徑22將本徵地/固有地穿過鐵電材料19而至電容器電極18及20之各者,且介於電容器電極18及20之各者之間。本徵路徑22將具有某一相對較高之整體/總電阻(即,電),當裝置14在操作中用作一電容器時,
該電阻被示意性地指示為一電阻器24。電阻器24之總電阻將取決於鐵電材料19之組合物、鐵電材料19之厚度,及鐵電材料19內之偶極定向。電阻器24可固有地為一非線性/可變電阻器,藉此其電阻具電壓相依性。
記憶體胞10包括自一電容器電極18或20至另一電容器電極之一平行(即,電路平行)電流洩漏路徑26。在一實施例中,平行路徑26具有0.4eV至5.0eV之一主導帶隙,且在一實施例中,該主導帶隙小於鐵電材料19之主導帶隙。若平行路徑26之長度遠短於路徑22,則此主導帶隙可大於鐵電材料19之主導帶隙。無論如何,在一實施例中,平行路徑26具有低於本徵路徑22之總電阻之某一總電阻(例如,展示為一電阻器28)。僅舉例而言,通過本徵洩漏路徑22之總電阻可為1×1011歐姆至1×1018歐姆,且通過平行洩漏路徑26之總電阻可為1×109歐姆至1×1017歐姆。
選擇裝置12可為任何既有或待開發之選擇裝置,其包含多個裝置。實例包含二極體、場效電晶體及雙極電晶體。在操作中,當記憶體胞閒置時(即,當與記憶體胞10相關聯之積體電路在操作上係「接通的」但不發生記憶體胞10之「讀取」或「寫入」操作時),選擇裝置12將展現電流洩漏。存在一選擇裝置電流洩漏路徑30且將其示意性地展示為圍繞選擇裝置12之一虛線,但此路徑將本徵地/固有地穿過選擇裝置12或到達下伏基板(例如,保持於接地或其他電位處)。洩漏路徑30經展示為具有某一總電阻32。在一實施例中,平行路徑26經組態,使得記憶體胞10在閒置時通過其之電流大於或等於記憶體胞10在閒置時通過路徑30之電流洩漏。此將取決於選擇裝置12、電容器14、平行路徑26之建構及材料,且取決於正常操作中之記憶體胞10內之各種點處之電壓。理想地且無論如何,此使閒置時之電極18及20處之電壓彼此相等或至少非常接近(例如,差值在50毫伏特內),藉此當記憶
體胞10閒置時,鐵電材料19內不產生電場或產生可忽略之電場。例如且進一步而言,閒置時之橫跨電容器之任何電壓差理想地使得鐵電材料19中之任何電場比鐵電材料19之本徵矯頑場低至少20倍。此可排除鐵電材料19內之非所欲偶極方向變化。替代地,作為實例,此可至少減小時間風險或增加鐵電材料19內之非所欲偶極方向變化之前的時間。
在一實施例中,平行路徑26中之電阻器28係電容器電極18與20之間之一非線性電阻器,其在較高電壓(例如,在1伏特至5伏特之間)處展現比較低電壓(例如,小於250毫伏特)處之總電阻高的總電阻。理想地,此一非線性電阻器經形成以趨向於提供比較低電壓處於閒置時大之較高電壓「讀取」及「寫入」操作期間之平行路徑26中之電流洩漏的減小量值。
一存取線及一選擇線(兩者圖中未展示)可與記憶體胞10相關聯。例如,選擇裝置12可為一簡單兩端子二極體或其他兩端子裝置。接著,可使用一交叉點狀陣列來建構,藉此作為電容器電極18之部分之一導電路徑11而與一存取線或選擇線(圖中未展示)連接,或係一存取線或選擇線(圖中未展示)的部分,且作為選擇裝置12之部分之一導電路徑13而與一存取線或選擇線(圖中未展示)之另一者連接,或係一存取線或選擇線(圖中未展示)之另一者的部分。作為一替代實例,選擇裝置12可為一場效電晶體。接著,作為一實例,導電路徑11可為共同用於一記憶體陣列或子陣列內之多個電容器14(圖中未展示)之一電容器電極18的部分,組件16可為電晶體之一源極/汲極區域,且組件13可為電晶體之另一源極/汲極區域。電晶體之閘極(圖中未展示)可為一存取線(圖中未展示)的一部分,且源極/汲極組件13可與一感測線(圖中未展示)之部分連接,或可為一感測線(圖中未展示)之部分。當然,可替代地使用其他架構及建構。
圖2示意性地展示包括電容器14及平行電流洩漏路徑26之一記憶體胞10之一部分之一實例性實體建構。已適當地使用來自上述實施例之相同元件符號,其中使用不同元件符號來指示一些差異。選擇裝置12(圖中未展示)可電耦合至電容器電極18或20之任一者。材料將位於記憶體胞建構10之兩側、立面內及立面外。例如,積體電路之其他部分或全部製造組件可提供於圍繞建構10之某一位置處,且並非特別與本文所揭示之發明密切相關(除包含任何適合選擇裝置12之外,如圖1示意圖中所展示)。
用於電容器電極18及20之實例性導電材料包含元素金屬、兩種或兩種以上元素金屬之一合金、導電金屬化合物及導電摻雜半導電材料之一或多者。實例性鐵電材料19包含具有過渡金屬氧化物、鋯、氧化鋯、鉿、氧化鉿、鈦酸鋯鉛及鈦酸鍶鋇之一或多者之鐵電體,且可在其內具有包括矽、鋁、鑭、釔、鉺、鈣、鎂、鍶及一稀土元素之一或多者之摻雜物。兩個具體實例係HfxSiyOz及HfxZryOz。除非另有指示,否則本文所描述之材料及/或結構之任何者可為均質或非均質的,且無論如何,可連續或不連續地上覆於任何材料上。此外,除非另有指示,否則可使用任何適合既有或待開發之技術(例如原子層沈積、化學氣相沈積、物理氣相沈積、磊晶生長、擴散摻雜及離子植入)來形成各材料。電容器電極18及20之各者之一實例性厚度係25埃至300埃,而鐵電材料19之實例性厚度係15埃至200埃。在本發明中,將「厚度」本身(非前面之方向形容詞)界定為自不同組合物之一緊鄰材料或一緊鄰區域之一最接近表面垂直地通過一給定材料或區域之平均直線距離。另外,本文所描述之各種材料可具有實質上恆定厚度或具有可變厚度。若具有可變厚度,則除非另有指示,否則厚度係指平均厚度。
平行路徑26經展示為由一材料34包圍或位於一材料34內。實例
性材料34包含非晶矽、多晶矽、鍺、硫屬化物(例如,金屬二硫屬化物)、富矽氮化矽、富矽氧化矽及適當地摻雜有導電性增強摻雜物(例如摻雜有Ti、Ta、Nb、Mo、Sr、Y、Cr、Hf、Zr及鑭系離子之SiO2及/或Si3N4)之本徵介電材料之一或多者。材料34及藉此平行路徑26可主要(即,大於50原子%)包括此(等)材料。此等材料之任何者可經摻雜或未經摻雜以提供在記憶體胞10閒置時流動通過其之電流洩漏之所要總電阻。在一實施例中,材料34係均質的,藉此電容器電極18與20之間之平行路徑26係均質的。在一實施例中,材料34係非均質的,藉此電容器電極18與20之間之平行電路係非均質的。在其中材料34及藉此平行路徑26係非均質之一實施例中,平行路徑26可歸因於其內之不同組合物材料具有不同帶隙而具有多個帶隙。然而,平行路徑26將具有可取決於平行路徑26內之個別不同材料之各自容量之0.4eV至5.0eV之一主導(意謂主控)帶隙。據此且無論如何,「主導」被使用且應用於本文,不論特定路徑/材料之均質性如何。在一實施例中,鐵電材料19之主導帶隙可低於平行路徑26之主導帶隙。在一實施例中,使平行路徑26之最小長度長於鐵電材料19之最小厚度。作為一實例,當鐵電材料及平行路徑之主導帶隙大致相同時,可在平行路徑中之狀態之密度等於或大於鐵電材料中之狀態之密度時使用此一長度關係。作為另一實例,當鐵電材料之主導帶隙小於平行路徑之主導帶隙時,可在平行路徑中之狀態之密度等於或大於鐵電材料中之狀態之密度時使用此一長度關係。
在一實施例中且如圖2中所展示,材料34及藉此平行路徑26係直接抵靠鐵電材料19。在本發明中,當所陳述之材料或結構相對於彼此存在至少某一實體觸摸接觸時,一材料或結構係「直接抵靠」另一材料或結構。相比而言,前面未加「直接」之「上方」、「上」及「抵靠」涵蓋「直接抵靠」以及其中(若干)介入材料或結構導致所陳述之
材料或結構相對於彼此之非實體觸摸接觸的建構。若兩個所陳述之材料並非直接彼此抵靠,則具有不同組合物之一材料介於其等之間。如本文所使用,例如,若此等材料係非均質的,「不同組合物」僅需要可直接彼此抵靠之兩個所陳述材料的部分在化學上及/或物理上係不同的。若兩個所陳述之材料並非直接彼此抵靠,則「不同組合物」僅需要:若此等材料係非均質的,則彼此最接近之兩個所陳述材料的部分在化學上及/或物理上係不同的。圖3描繪一替代實施例記憶體胞10a,其中平行路徑26並非直接抵靠鐵電材料19a。已適當地使用來自上述實施例之相同元件符號,其中使用後綴「a」或使用不同元件符號來指示一些建構差異。電容器14a經展示為包括間隔於材料34與19a之間之某一材料21(例如介電材料,諸如二氧化矽及/或氮化矽),藉此平行路徑26並非直接抵靠鐵電材料19a。可使用如上文所描述之(若干)任何其他屬性或建構。
圖4展示另一實例性實施例記憶體胞10b。已適當地使用來自上述實施例之相同元件符號,其中使用後綴「b」或不同元件符號來指示一些建構差異。記憶體胞10b中之材料34b(及藉此平行路徑26b)本質上經展示為穿過鐵電材料19b,藉此構成電容器建構14b之一內部部分且具有兩個橫向側35(即,在至少一直線橫截面中),兩個橫向側35之各者係直接抵靠鐵電材料19b。可使用如上文所描述之(若干)任何其他屬性或建構。
平行電流洩漏路徑可具有等於、大於或小於兩個電容器電極之間之鐵電材料之最小厚度的最小長度。在一實施例中,平行路徑具有兩個電容器電極之間之鐵電材料之最小厚度之5%內的最小長度。圖2至圖4本質上將平行路徑26展示為具有實質上等於鐵電材料19/19a/19b之最小厚度的最小長度。例如,即使在圖2及圖3實施例中,穿過材料34之最短路徑(例如最小長度)係自電容器電極18之材料的最右下角至
電極20之材料的最右上角,但為清楚起見,圖2及圖3中將平行路徑26示意性地展示為穿過材料34之一寬拱形路徑。在一些實施例中,平行路徑可具有大於兩個電容器電極之間之鐵電材料之最小厚度的最小長度,在一實施例中,其係在兩個電容器電極之間之鐵電材料之最小厚度的30%內,且在一實施例中,其係兩個電容器電極之間之鐵電材料之最小厚度的至少兩倍。
圖5及圖6中展示另一實例性實施例記憶體胞10c。已適當地使用來自上述實施例之相同元件符號,其中使用後綴「c」或使用不同元件符號來指示一些建構差異。電容器14c包括第一導電電容器電極20c,其具有一基底40及自基底40延伸之橫向間隔(即,在至少一直線橫截面中)壁42。橫向間隔壁42具有對向側表面43。第二導電電容器電極18c係橫向地介於第一電容器電極20c的壁42之間。鐵電材料19c係橫向地介於第一電容器電極20c的壁42之間,且橫向地介於第二電容器電極18c與第一電容器電極20c之間。在一實施例中,鐵電材料19c包括具有側表面44之橫向間隔壁45(圖5)。電容器14c包括自第一電容器電極20c及第二電容器電極18c之一者穿過鐵電材料19c而至另一電容器電極之一本徵電流洩漏路徑22。
一平行電流洩漏路徑26c係介於第二電容器電極18c與第一電容器電極20c之基底40之一表面41之間。平行路徑26係電路平行於本徵路徑22且具有比本徵路徑22低之總電阻。在一實施例中,平行路徑26c係在具有0.4eV至5.0eV之一主導帶隙之一材料34c內且穿過該材料34c,且在一實施例中,其帶隙小於鐵電材料19c之帶隙。圖5展示一實例性實施例,其中平行路徑26c之最小長度比鐵電材料19c之最小厚度大兩倍。在一實施例中,材料34c係直接抵靠第一電容器電極42之基底40之表面41。在一實施例中,材料34c係直接抵靠鐵電材料19c之橫向間隔壁45之側表面44。一選擇裝置12(圖中未展示)將與電容器
14c串聯電耦合,具體而言,與第一電容器電極20c或第二電容器電極18c之一者串聯電耦合。在一實施例中且如圖中所展示,材料34c並非直接抵靠第一電容器電極20c之橫向間隔壁42之側表面43。在一實施例中且如圖中所展示,第一電容器電極20c包括一環形物48,且在一實施例中,鐵電材料19c包括一環形物50。可使用如上文所描述之(若干)任何其他屬性或建構。
任何適合技術可用於製造圖5及圖6建構。作為一實例,可形成第一電容器電極20c及鐵電材料19c作為介電材料(圖中未展示)中之一開口內之各自襯層。接著,可使鐵電材料19c各向異性地蝕刻穿過第一電容器電極20c之基底以產生如圖5中所展示之材料19c建構。接著,材料34c可經沈積且經回蝕以產生如圖5中所展示之其建構,接著沈積且回拋或回蝕材料18c。
圖7描繪由圖5及圖6展示之記憶體胞之一替代實施例記憶體胞10d。已適當地使用來自上述實施例之相同元件符號,其中使用後綴「d」或使用不同元件符號來指示一些建構差異。鐵電材料19d具有橫向間隔壁45自其延伸之一基底54。材料34d延伸穿過鐵電材料19d之基底54。在一實施例中且如圖中所展示,材料34d並非直接抵靠鐵電材料19d之橫向間隔壁45之橫向側表面44。一選擇裝置12(圖中未展示)將與電容器14d串聯電耦合,具體而言,電耦合至電容器電極18d或20c之一者。當然,任何適合技術可用於製造圖7建構。例如,可形成第一電容器電極20c及鐵電材料19d作為介電材料(圖中未展示)中之一開口內之各自襯層。接著,可首先形成材料18d作為剩餘開口內之一襯層,其具有鐵電材料19d作為其側壁且留下具有等於材料34d之橫向寬度之橫向寬度之一空隙空間。接著,可使材料18d襯層各向異性地蝕刻穿過鐵電材料19d之基底。此接著蝕刻穿過鐵電材料19d之基底而至材料20c以產生圖7中所展示之材料19d之最終建構。接著,材料34d
可經沈積且經回蝕以產生其最終建構,接著沈積且回拋或回蝕剩餘材料18d。可使用如上文所描述之(若干)任何其他屬性或建構。
圖8中展示另一實施例記憶體胞10e。已適當地使用來自上述實施例之相同元件符號,其中使用後綴「e」或使用不同元件符號來指示一些建構差異。不論是否具有一基底40,第一電容器電極20c具有橫向間隔壁42。材料34e內之平行電流洩漏路徑26e介於第二電容器電極18c與第一電容器電極20c之橫向間隔壁42之一表面60之間。在一實施例中且如圖中所展示,表面60包括第一電容器電極20c之橫向間隔壁42之一橫向側表面。無論如何,在一實施例中且如圖中所展示,材料34e係直接抵靠第一電容器電極20c之壁42之表面60。在其中第一電容器電極20c具有一基底40(橫向間隔壁42自其延伸)之一實施例中,材料34e可直接抵靠第一電容器電極20c之基底40之一表面61。一選擇裝置12(圖中未展示)將與電容器14e串聯電耦合,具體而言,電耦合至電容器電極18c或20c之一者。當然,任何適合技術可用於製造圖8建構。例如,可形成第一電容器電極20c作為介電材料(圖中未展示)中之一開口內之一襯層。接著,材料34e可經沈積且經回蝕以產生其建構,如圖8中所展示。此可接著沈積鐵電材料19e作為剩餘開口內之一襯層且隨後使其各向異性地蝕刻穿過材料19e之基底。接著,可沈積材料18c且將其回拋或回蝕成其所描繪之最終建構。可使用如上文所描述之(若干)任何其他屬性或建構。
圖9及圖10中展示另一實施例記憶體胞10f。已適當地使用來自上述實施例之相同元件符號,其中使用後綴「f」或使用不同元件符號來指示一些建構差異。記憶體胞10f與記憶體胞10e之相近類似點在於:一平行電流洩漏路徑26f係介於第二電容器電極18f與第一電容器電極20c之橫向間隔壁42之一表面之間。然而,在記憶體胞10f中,此表面包括第一電容器電極20c之橫向間隔壁42之一立向最外表面65。
此外,在一實施例中且如圖中所展示,材料34f係直接抵靠鐵電材料19f之一立向最外表面66。此外,在一實施例中且如圖中所展示,材料34f包括一環狀物70。當然,任何適合技術可用於製造圖9及圖10建構。例如,可形成第一電容器電極20c及鐵電材料19f作為介電材料(圖中未展示)中之一開口內之各自襯層。接著,材料18f可經沈積以填充具有鐵電材料19f作為其側壁之剩餘開口。接著,可將材料20c、19f及18f共同回蝕或回拋至表面65及66之高度。接著,可沈積材料34f作為剩餘開口內之一襯層且隨後使材料34f各向異性地蝕刻穿過其基底以產生如圖9及圖10中所展示之其最終建構。接著,可沈積剩餘材料18f且將回拋或回蝕成其所描繪之最終建構。可使用如上文所描述之(若干)任何其他屬性或建構。
在一實施例中,一記憶體胞(例如10e或10f)具有包括一環形物48之一第一電容器電極20c。第二電容器電極18c/18f係徑向地位於第一電容器電極20c之環形物48內。鐵電材料19e/19f係徑向地位於第一電容器電極20c之環形物48內。電容器14e/14f包括自第一電容器電極及第二電容器電極之一者穿過鐵電材料19e/19f而至另一電容器電極之一本徵電流洩漏路徑22。平行電流洩漏路徑26e/26f係介於第二電容器電極18c/18f與第一電容器電極20c之環形物48之一表面之間。平行路徑26e/26f係電路平行於本徵路徑22且具有比本徵路徑22低之總電阻。
在一實施例中,材料34f包括一環形物70。在一實施例中,材料34f係直接抵靠環形物48之一立向最外表面65。在一實施例中,鐵電材料19f包括一環形物50f,且材料34f係直接抵靠環形物50f之一立向最外表面66。可使用如上文所描述之(若干)任何其他屬性或建構。
總結
在一些實施例中,一種記憶體胞包括一選擇裝置及與該選擇裝置串聯電耦合之一電容器。該電容器包括兩個導電電容器電極,其等
具有介於其等之間之鐵電材料。該電容器包括自該等電容器電極之一者穿過該鐵電材料而至另一電容器電極之一本徵電流洩漏路徑。存在自該電容器電極至該另一電容器電極之一平行電流洩漏路徑。該平行電流洩漏路徑係電路平行於該本徵路徑且具有比該本徵路徑低之總電阻。
在一些實施例中,一種記憶體胞包括一選擇裝置及與該選擇裝置串聯電耦合之一電容器。該電容器包括兩個導電電容器電極,其等具有介於其等之間之鐵電材料。該電容器包括自該等電容器電極之一者穿過該鐵電材料而至另一電容器電極之一本徵電流洩漏路徑。存在自該電容器電極至該另一電容器電極之一平行電流洩漏路徑。該平行電流洩漏路徑係電路平行於該本徵路徑且具有0.4eV至5.0eV之一主導帶隙。
在一些實施例中,一種記憶體胞包括一選擇裝置及與該選擇裝置串聯電耦合之一電容器。該電容器包括具有一基底及自該基底延伸之橫向間隔壁之一第一導電電容器電極。一第二導電電容器電極係橫向地介於該第一電容器電極之該等壁之間。一鐵電材料係橫向地介於該第一電容器電極之該等壁之間且橫向地介於該第二電容器電極與該第一電容器電極之間。該電容器包括自該第一電容器電極及該第二電容器電極之一者穿過該鐵電材料而至另一電容器電極之一本徵電流洩漏路徑。在該第二電容器電極與該第一電容器電極之該基底之一表面之間存在一平行電流洩漏路徑。該平行電流洩漏路徑係電路平行於該本徵路徑且具有比該本徵路徑低之總電阻。
在一些實施例中,一種記憶體胞包括一選擇裝置及與該選擇裝置串聯電耦合之一電容器。該電容器包括具有橫向間隔壁之一第一導電電容器電極。一第二導電電容器電極係橫向地介於該第一電容器電極之該等壁之間。鐵電材料係橫向地介於第一電容器電極之該等壁之
間且橫向地介於該第二電容器電極與該第一電容器電極之間。該電容器包括自該第一電容器電極及該第二電容器電極之一者穿過該鐵電材料而至另一電容器電極之一本徵電流洩漏路徑。在該第二電容器電極與該第一電容器電極之該等橫向間隔壁之一表面之間存在一平行電流洩漏路徑。該平行電流洩漏路徑係電路平行於該本徵路徑且具有比該本徵路徑低之總電阻。
在一些實施例中,一種記憶體胞包括一選擇裝置及與該選擇裝置串聯電耦合之一電容器。該電容器包括一第一導電電容器電極,其包括一環形物。一第二導電電容器電極係徑向地位於該第一電容器電極之該環形物內。鐵電材料係徑向地位於該第二電容器電極與該第一電容器電極之間之該第一電容器電極之該環形物內。該電容器包括自該第一電容器電極及該第二電容器電極之一者穿過該鐵電材料而至另一電容器電極之一本徵電流洩漏路徑。在該第二電容器電極與該第一電容器電極之該環狀物之一表面之間存在一平行電流洩漏路徑。該平行電流洩漏路徑係電路平行於該本徵路徑且具有比該本徵路徑低之總電阻。
在遵守法規之情況下,已用或多或少專針對結構及方法特徵之語言描述本文所揭示之標的。然而,應瞭解,申請專利範圍不受限於所展示及所描述之特定特徵,此係因為本文所揭示之構件包括實例性實施例。因此,申請專利範圍應被給予如字面措詞之全範疇且應根據等效物之教義來適當地加以解譯。
10‧‧‧記憶體胞/建構
11‧‧‧導電路徑
12‧‧‧選擇裝置
13‧‧‧組件/導電路徑
14‧‧‧電容器
16‧‧‧導電路徑/組件
18‧‧‧電容器電極
19‧‧‧鐵電材料
20‧‧‧電容器電極
22‧‧‧本徵電流洩漏路徑
24‧‧‧電阻器
26‧‧‧平行電流洩漏路徑
28‧‧‧電阻器
30‧‧‧選擇裝置電流洩漏路徑
32‧‧‧電阻
Claims (20)
- 一種記憶體胞,其包括:一選擇裝置;一電容器,其與該選擇裝置串聯電耦合,該電容器包括兩個導電電容器電極,該兩個導電電容器電極具有介於其等之間之鐵電材料,該電容器包括自該等電容器電極之一者穿過該鐵電材料而至另一電容器電極之一本徵電流洩漏路徑;及一平行電流洩漏路徑,其自該電容器電極至該另一電容器電極,該平行電流洩漏路徑係電路平行於該本徵路徑且具有比該本徵路徑低之總電阻,該平行電流洩漏路徑係非直接抵靠該鐵電材料。
- 如請求項1之記憶體胞,其中在操作中,當該記憶體胞閒置時,該選擇裝置展現電流洩漏,該平行電流洩漏路徑經組態使得該記憶體胞閒置時通過該平行路徑之電流大於或等於該記憶體胞閒置時之該選擇裝置之該電流洩漏。
- 如請求項1之記憶體胞,其中該平行電流洩漏路徑具有0.4eV至5.0eV之一主導帶隙,且該主導帶隙小於該鐵電材料之主導帶隙。
- 如請求項1之記憶體胞,其中在操作中,閒置時橫跨該電容器之任何電壓差使得該鐵電材料中之任何電場比該鐵電材料之本徵矯頑場低至少20倍。
- 如請求項1之記憶體胞,其中該平行電流洩漏路徑包括介於該兩個電容器電極之間之一非線性電阻器,該非線性電阻器在較高電壓處展現比較低電壓處之電阻高的電阻。
- 如請求項1之記憶體胞,其中該平行電流洩漏路徑具有大於該兩 個電容器電極之間之該鐵電材料之最小厚度的最小長度。
- 如請求項1之記憶體胞,其中該平行電流洩漏路徑具有在該兩個電容器電極之間之該鐵電材料之最小厚度之95%至105%內的最小長度。
- 一種記憶體胞,其包括:一選擇裝置;一電容器,其與該選擇裝置串聯電耦合,該電容器包括兩個導電電容器電極,該兩個導電電容器電極具有介於其等之間之鐵電材料,該電容器包括自該等電容器電極之一者穿過該鐵電材料而至另一電容器電極之一本徵電流洩漏路徑;及一平行電流洩漏路徑,其自該電容器電極至該另一電容器電極,該平行電流洩漏路徑係電路平行於該本徵路徑,該平行電流洩漏路徑具有0.4eV至5.0eV之一主導帶隙,該平行電流洩漏路徑係非直接抵靠該鐵電材料。
- 如請求項8之記憶體胞,其中該平行電流洩漏路徑主要包括非晶矽、多晶矽及鍺中之一或多者。
- 如請求項8之記憶體胞,其中該平行電流洩漏路徑主要包括一或多個硫屬化物。
- 如請求項8之記憶體胞,其中該平行電流洩漏路徑主要包括富矽氮化矽、富矽氧化矽,及摻雜有導電性增強摻雜物之本徵介電材料中之一或多者。
- 一種記憶體胞,其包括:一選擇裝置;一電容器,其與該選擇裝置串聯電耦合,該電容器包括:一第一導電電容器電極,其具有一基底及自該基底延伸之橫向間隔壁; 一第二導電電容器電極,其橫向地介於該第一電容器電極之該等壁之間;及鐵電材料,其橫向地介於該第一電容器電極之該等壁之間且橫向地介於該第二電容器電極與該第一電容器電極之間,該電容器包括自該第一電容器電極及該第二電容器電極之一者穿過該鐵電材料而至另一電容器電極之一本徵電流洩漏路徑;及一平行電流洩漏路徑,其介於該第二電容器電極與該第一電容器電極之該基底之一表面之間,該平行電流洩漏路徑係電路平行於該本徵路徑,且具有比該本徵路徑低的總電阻。
- 如請求項12之記憶體胞,其中該第二電容器電極與該第一電容器電極之該基底之該表面之間的該平行電流洩漏路徑係位於具有0.4eV至5.0eV之一主導帶隙的材料內且穿過該材料,具有0.4eV至5.0eV之主導帶隙的該材料係直接抵靠該第一電容器電極之該基底的該表面。
- 如請求項12之記憶體胞,其中該鐵電材料具有一基底及自該基底延伸之橫向間隔壁;及該第二電容器電極與該第一電容器電極之該基底之該表面之間的該平行電流洩漏路徑係位於具有0.4eV至5.0eV之一主導帶隙的材料內且穿過該材料,具有0.4eV至5.0eV之主導帶隙的該材料延伸穿過該鐵電材料的該基底。
- 一種記憶體胞,其包括:一選擇裝置;一電容器,其與該選擇裝置串聯電耦合,該電容器包括:一第一導電電容器電極,其具有橫向間隔壁;一第二導電電容器電極,其橫向地介於該第一電容器電極 之該等壁之間;及鐵電材料,其橫向地介於該第一電容器電極之該等壁之間且橫向地介於該第二電容器電極與該第一電容器電極之間,該電容器包括自該第一電容器電極及該第二電容器電極之一者穿過該鐵電材料而至另一電容器電極之一本徵電流洩漏路徑;及一平行電流洩漏路徑,其介於該第二電容器電極與該第一電容器電極之該等橫向間隔壁之一表面之間,該平行電流洩漏路徑係電路平行於該本徵路徑,且具有比該本徵路徑低的總電阻。
- 如請求項15之記憶體胞,其中該第二電容器電極與該第一電容器電極之該等橫向間隔壁之該表面之間的該平行電流洩漏路徑係位於具有0.4eV至5.0eV之一主導帶隙的材料內且穿過該材料,具有0.4eV至5.0eV之主導帶隙的該材料係直接抵靠該第一電容器電極之該等橫向間隔壁的該表面。
- 如請求項15之記憶體胞,其中該表面包括該第一電容器電極之該等橫向間隔壁之一橫向側表面。
- 一種記憶體胞,其包括:一選擇裝置;一電容器,其與該選擇裝置串聯電耦合,該電容器包括:一第一導電電容器電極,其包括一環形物;一第二導電電容器電極,其徑向地位於該第一電容器電極之該環形物內;及鐵電材料,其徑向地位於該第二電容器電極與該第一電容器電極之間之該第一電容器電極之該環形物內,該電容器包括自該第一電容器電極及該第二電容器電極之一者穿過該鐵 電材料而至另一電容器電極之一本徵電流洩漏路徑;及一平行電流洩漏路徑,其介於該第二電容器電極與該第一電容器電極之該環形物之一表面之間,該平行電流洩漏路徑係電路平行於該本徵電路,且具有比該本徵路徑低的總電阻。
- 如請求項18之記憶體胞,其中該環形物之該表面係該環形物之一立向最外表面;及該第二電容器電極與該第一電容器電極之該環形物之該表面之間之該平行電流洩漏路徑係位於具有0.4eV至5.0eV之一主導帶隙之材料內且穿過該材料,具有0.4eV至5.0eV之主導帶隙之該材料係直接抵靠該環形物之該立向最外表面。
- 如請求項18之記憶體胞,其中該鐵電材料包括具有一立向最外表面之一環形物;及該第二電容器電極與該第一電容器電極之該環形物之該表面之間之該平行電流洩漏路徑係位於具有0.4eV至5.0eV之一主導帶隙之材料內且穿過該材料,具有0.4eV至5.0eV之主導帶隙之該材料係直接抵靠該鐵電材料之該立向最外表面。
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US20160240545A1 (en) | 2016-08-18 |
TW201635286A (zh) | 2016-10-01 |
KR102369843B1 (ko) | 2022-03-03 |
EP3259757A1 (en) | 2017-12-27 |
US9673203B2 (en) | 2017-06-06 |
US20200350323A1 (en) | 2020-11-05 |
EP3259757A4 (en) | 2018-09-19 |
US11706929B2 (en) | 2023-07-18 |
US20170236828A1 (en) | 2017-08-17 |
KR102087488B1 (ko) | 2020-03-11 |
KR20170105604A (ko) | 2017-09-19 |
US11244951B2 (en) | 2022-02-08 |
US20180145084A1 (en) | 2018-05-24 |
CN107251223A (zh) | 2017-10-13 |
US10741567B2 (en) | 2020-08-11 |
CN107251223B (zh) | 2021-03-16 |
US20220122998A1 (en) | 2022-04-21 |
CN112802844A (zh) | 2021-05-14 |
WO2016133611A1 (en) | 2016-08-25 |
US9305929B1 (en) | 2016-04-05 |
KR20210022151A (ko) | 2021-03-02 |
US20190189626A1 (en) | 2019-06-20 |
US10217753B2 (en) | 2019-02-26 |
KR20200027573A (ko) | 2020-03-12 |
KR102220284B1 (ko) | 2021-02-26 |
US9887204B2 (en) | 2018-02-06 |
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