US20150028280A1 - Memory cell with independently-sized elements - Google Patents
Memory cell with independently-sized elements Download PDFInfo
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- US20150028280A1 US20150028280A1 US13/952,357 US201313952357A US2015028280A1 US 20150028280 A1 US20150028280 A1 US 20150028280A1 US 201313952357 A US201313952357 A US 201313952357A US 2015028280 A1 US2015028280 A1 US 2015028280A1
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- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors
Definitions
- the present disclosure relates generally to semiconductor devices, and more particularly to memory cell architectures and methods of forming the same.
- RAM random-access memory
- ROM read only memory
- DRAM dynamic random access memory
- SDRAM synchronous dynamic random access memory
- resistance variable memory flash memory
- PCM phase change material
- RRAM resistive random access memory
- Non-volatile memory are utilized as memory devices for a wide range of electronic applications in need of high memory densities, high reliability, and data retention without power.
- Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices.
- Constant challenges related to memory device fabrication are to decrease the size of a memory device, increase the storage density of a memory device, reduce power consumption, and/or limit memory device cost.
- Some memory devices include memory cells arranged in a two dimensional array, in which memory cells are all arranged in a same plane.
- various memory devices include memory cells arranged into a three dimensional (3D) array having multiple levels of memory cells.
- FIG. 1 is a perspective view of a portion of a memory array in accordance with a number of embodiments of the present disclosure.
- FIG. 2 illustrates a three dimensional memory array in accordance with a number of embodiments of the present disclosure.
- FIGS. 3A and 3B illustrate cross-sectional views of memory cells in perpendicular directions in accordance with a number of embodiments of the present disclosure.
- FIGS. 4A and 4B illustrate cross-sectional views in a same cross section of different sized stacks corresponding to a memory cell in accordance with a number of embodiments of the present disclosure.
- FIGS. 5A and 5B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory elements in accordance with a number of embodiments of the present disclosure.
- FIGS. 6A and 6B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized switch elements in accordance with a number of embodiments of the present disclosure.
- FIGS. 7A and 7B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory and switch elements in accordance with a number of embodiments of the present disclosure.
- FIGS. 8A and 8B illustrate cross-sectional views of stacks corresponding to a memory cell having non-vertical stack wall and different sized switch elements in accordance with a number of embodiments of the present disclosure.
- An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
- Embodiments of the present disclosure implement a memory cell in a cross point memory array in which the switch element dimensions are independent from the memory element dimensions. Size independence between the switch element and the memory element allows for an unlimited number of combinations of memory element size relative to select element size, which in turn facilitates addressing specific electrical properties associated with particular cross point array applications. With the ability to independently size the switch element and the memory element in a same stack of materials forming a memory cell, e.g., using phase change material (PCM), in a cross point array, the current density for the memory element can be different than the current density for the switch element. For example, in a phase change mechanism in the memory element can be improved without resulting in undue switching stress on the switch element.
- PCM phase change material
- 106 may reference element “ 06 ” in FIG. 1
- a similar element may be referenced as 306 in FIG. 3A .
- “a number of” a particular element and/or feature can refer to one or more of such elements and/or features.
- the term “substantially” intends that the modified characteristic needs not be absolute, but is close enough so as to achieve the advantages of the characteristic.
- “substantially parallel” is not limited to absolute parallelism, and can include orientations that are at least closer to a parallel orientation than a perpendicular orientation.
- “substantially orthogonal” is not limited to absolute orthogonalism, and can include orientations that are at least closer to a perpendicular orientation than a parallel orientation.
- FIG. 1 is a perspective view of a portion of a memory array 100 in accordance with a number of embodiments of the present disclosure.
- memory array 100 is a cross point memory/switch memory array, e.g., a phase change memory array.
- embodiments of the present disclosure are not so limited.
- Embodiments of the present disclosure can comprise a two dimensional (2D) cross point memory array, or a three dimensional (3D) cross point memory array with more decks between word lines and bit lines.
- Array 100 can be a cross-point array having memory cells 102 located at the intersections of a number of conductive lines, e.g., access lines 104 , which may be referred to herein as word lines, and a number of conductive lines, e.g., data/sense lines 106 , which may be referred to herein as bit lines.
- word lines 104 can be parallel or substantially parallel to each other and can be orthogonal to bit lines 106 , which can be parallel or substantially parallel to each other.
- Word lines 104 and/or bit lines 106 can be a conductive material such as tungsten, copper, titanium, aluminum, and/or other metals, for example.
- array 100 can be a portion, e.g., a level, of a three-dimensional array, e.g., a multi-level array, (described further with respect to FIG. 2 ) in which other arrays similar to array 100 are at different levels, for example above and/or below array 100 .
- Each memory cell 102 can include a memory element 114 , e.g., storage element, coupled in series with a respective switch element 110 , e.g., selector device, and/or access device.
- the memory cell can have a number of electrodes adjacent the memory element 114 and switch element 110 , including a first, e.g., top, electrode, second, e.g., middle, electrode, and/or third, e.g., bottom, electrode.
- the memory element 114 can be, for example, a resistive memory element.
- the memory element 114 can be formed between a pair of electrodes, e.g., first electrode 116 and second electrode 112 .
- the memory element can be comprised of a resistance variable material such as a phase change memory (PCM) material, for example.
- PCM phase change memory
- the PCM material can be a chalcogenide alloy such as a Germanium-Antimony-Tellurium (GST) material, e.g., Ge—Sb—Te materials such as Ge 2 Sb 2 Te 5 , Ge 1 Sb 2 Te 4 , Ge 1 Sb 4 Te 7 , Ge 8 Sb 5 Te 8 , Ge 4 Sb 4 Te 7 , etc., or an indium(In)-antimony(Sb)-tellurium(Te) (IST) material, e.g., In 2 Sb 2 Te 5 , In 1 Sb 2 Te 4 , In 1 Sb 4 Te 7 , etc., among other phase change memory materials.
- GST Germanium-Antimony-Tellurium
- GST Germanium-Antimony-Tellurium
- GST Germanium-Antimony-Tellurium
- GST Germanium-Antimony
- phase change memory materials can include Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—Sb—Ge, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—Sb—Te—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—
- embodiments of the present disclosure are not limited to a particular type of PCM material. Further, embodiments are not limited to memory elements comprising PCM materials.
- the memory elements can comprise a number of resistance variable materials such as binary metal oxides, colossal magnetoresistive materials, and/or various polymer-based resistive variable materials, among others.
- FIG. 1 shows the memory element 114 and the switch element 110 having similar dimensions.
- a memory cell 102 can be formed with a memory element 114 having different dimension(s), e.g., critical dimension, cross-sectional area, etc., than the switch element 110 .
- the switch element 110 can be a two terminal device such as a diode, an ovonic threshold switch (OTS), or an ovonic memory switch (OMS).
- OTS ovonic threshold switch
- OMS ovonic memory switch
- the switch element 110 can be a field effect transistor (FET), a bipolar junction transistor (BJT), or a diode, among other types of selector devices.
- FET field effect transistor
- BJT bipolar junction transistor
- the switch element 110 can be formed between a pair of electrodes, e.g., the second electrode and a third electrode 112 and 108 .
- FIG. 1 illustrates a configuration having the memory element 114 formed over the switch element 110
- the switch element 110 can be formed over the memory element 114 , for example.
- Electrodes 108 , 112 , and/or 116 can comprise materials such as Ti, Ta, W, Al, Cr, Zr, Nb, Mo, Hf, B, C, conductive nitrides of the aforementioned materials, e.g., TiN, TaN, WN, CN, etc.), and/or combinations thereof.
- the switch elements 110 corresponding to memory cells 102 can be OTS's having a chalcogenide selector device material.
- the chalcogenide material of the switch element 110 may not actively change phase, e.g., between amorphous and crystalline, such as a chalcogenide resistance variable material of the memory element.
- the chalcogenide material of the switch element can change between an “on” and “off” state depending on the voltage potential applied across memory cell 102 .
- the “state” of the OTS can change when a current through the OTS exceeds a threshold current or a voltage across the OTS exceeds a threshold voltage. Once the threshold current or voltage is reached, an on state can be triggered and the OTS can be in a conductive state. In this example, if the current or voltage potential drops below a threshold value, the OTS can return to a non-conductive state.
- the memory element 114 can comprise one or more of the same material(s) as the switch element 110 .
- embodiments are not so limited.
- memory element 114 and switch element 110 can comprise different materials.
- Memory cells 102 can be programmed to a target data state, e.g., corresponding to a particular resistance state, by applying sources of an electrical field or energy, such as positive or negative electrical pulses, to the cells, e.g., to the storage element of the cells, for a particular duration.
- the electrical pulses can be, for example, positive or negative voltage or current pulses.
- FIG. 2 illustrates a three dimensional (3D) memory array in accordance with a number of embodiments of the present disclosure.
- the 3D memory array comprises a plurality of memory cells 202 - 1 , 202 - 2 , e.g., memory element in series with a switch element as described with respect to FIG. 1 .
- FIG. 2 shows a first memory array comprising memory cells 202 - 1 formed between word lines 204 - 1 and bits lines 206 , and a second memory array comprising memory cells 202 - 2 formed between word lines 204 - 2 and bits lines 206 . That is, the first memory array formed below bit lines 206 and the second memory array formed above bit lines 206 share common bit lines 206 therebetween.
- FIG. 2 is a simplified diagram that does not precisely reflect the three dimensional physical dimensions of the various features illustrated, including the exact proximity of features to one another.
- FIG. 2 should not be considered as to be representative of the precise topological positioning of the various elements. Rather, FIG. 2 provides an overview of the electrical scheme for a 3D memory array, and the approximate relative arrangement of the various features.
- FIG. 2 shows a 3D array comprising 2 memory arrays, embodiments of the present invention are not so limited, and can include additional memory array(s) arranged into a number of levels.
- FIGS. 3A and 3B illustrate cross-sectional views of memory cells in perpendicular directions in accordance with a number of embodiments of the present disclosure.
- FIG. 3A shows a cross-section in a first direction, e.g., side view, of a portion of a memory array, such as that shown in FIG. 1 .
- FIG. 3B shows a cross-section in a second direction, e.g., end view, of a portion of a memory array, such as that shown in FIG. 1 .
- FIGS. 3A and 3B show some additional detail than that shown and described with respect to FIG. 1 .
- the memory cells shown in FIGS. 3A and 3B can be similar to those described with respect to FIGS. 1 and 2 .
- a stack of materials can be formed over a word line 304 .
- the stack of materials can include a third electrode 308 formed over the word line 304 , a switch element 310 formed over the third electrode 308 , a second electrode 312 formed over the switch element 310 , a memory element 314 formed over the second electrode 312 , and a first electrode 316 formed over the memory element 314 .
- a bit line 306 can be formed over the stack extending left-to-right in FIG. 3A and into-and-out-of the paper in FIG. 3B .
- Word line 304 extends perpendicularly to bit line 306 . That is, word line 304 extends into-and-out-of the paper in FIG. 3A and left-to-right in FIG. 3B .
- the third electrode 308 can extend similarly to the word line 304 , as shown in FIGS. 3A and 3B .
- the memory element 314 and switch element 310 can have one or more different directions from one another and/or electrode(s).
- the stack of materials is shown being square when viewed from the side and end perspectives.
- sealing material 321 can be formed around the word line stacks and filling material 320 can be formed in the areas between the word line stacks.
- a dielectric material 322 can be formed over sealing material 321 and filling material 320 in the areas between the word line stacks, as shown in FIG. 3A .
- sealing material 324 can be formed around the bit line stacks and filling material 323 can be formed in the areas between the bit line stacks.
- Dielectric material 322 can be formed over sealing material 324 and filling material 323 in the areas between the bit line stacks, as shown in FIG. 3B .
- the cross point array 100 of memory cells shown in FIGS. 1 and 2 can be created through dry etch patterning in two perpendicular directions, e.g., corresponding to the direction of the word lines 304 and the bit lines 306 .
- Materials corresponding to respective conductive lines and components of the memory cell can be bulk deposited and etched to form the various features.
- the dry etch patterning in two perpendicular directions forms the various conductive lines and the stacks corresponding to individual memory cells.
- a first etch can define one direction of the stack, e.g., a row structure separated by first trenches, self-aligned to the underlying conductive lines, e.g., word lines 304 , which in turn can be connected to other circuitry.
- the row structures and trenches can be sealed in between the word line 304 , e.g., with sealing material 321 , and filled with filling material 320 and dielectric material 322 .
- a material comprising the bit lines 306 e.g., conductive material, can be deposited on top of the row structures, sealing material 321 , filling material 320 , and dielectric material 322 .
- a second etch process can be used to form second trenches that define the bit lines 306 in a direction perpendicular to the word lines 304 , and again self-aligned to the stacks associated with the memory cells (down to the third electrodes 308 ).
- the second trenches and third electrodes 308 can be sealed, e.g., by sealing materials 324 and filling material 323 , and the second trenches filled by dielectric material 322 .
- the result of the above-described sequence is an array of stacks, e.g., active pillars, corresponding to respective memory cells and isolated from one another by dielectric material 322 .
- Word lines 304 below the memory cells connect the stacks in one direction
- bit lines 306 above the memory cells connect the stacks in a perpendicular direction.
- FIGS. 4A and 4B illustrate cross-sectional views in a same cross section of different sized stacks corresponding to a memory cell in accordance with a number of embodiments of the present disclosure. That is, FIGS. 4A and 4B show the same cross section before ( FIG. 4A ) and after ( FIG. 4B ) a dimension modification, e.g., isotropic etch.
- the respective stacks shown in FIGS. 4A and 4B can be formed by dry etch patterning in two perpendicular directions described above with respect to FIGS. 3A and 3B . For example, dry etching can be used to form the stacks corresponding to individual memory cells.
- dry etching can be used to control the various dimensions of the stack, e.g., width and length of a cross-sectional area of the switch and memory elements, in a plane perpendicular to a direction between the switch element and the memory element.
- the dry etch patterning in two perpendicular directions can be used to form a relatively wider stack (comprising word line 404 A, third electrode 408 A, switch element 410 A, second electrode 412 A, memory element 414 A, and first electrode 416 A).
- a relatively thinner stack (comprising word line 404 B, third electrode 408 B, switch element 410 B, second electrode 412 B, memory element 414 B, and first electrode 416 B). Because the dry etch patterning in two perpendicular directions is self-aligning, all of the components of the relatively wider stack, shown in FIG. 4A , have the same dimensions.
- all of the components are wider than all of the components of the relatively thinner stack shown in FIG. 4B . That is, using the dry etch patterning in two perpendicular directions to control width of the memory element, for example, results in the widths of all other components in the stack being likewise controlled to the same width.
- Critical dimension is the finest line resolvable associated with etch patterning, e.g., etching using a pattern to delineate areas to be etched from areas not to be etched.
- lateral dimension is a dimension in a plane that is perpendicular to a direction between the switch element and a corresponding memory element of a memory cell, e.g., perpendicular to the orientation of the stack of materials comprising the memory cell.
- the LD can be a CD (discussed above) or a modified dimension (discussed below).
- a stack can have a rectangular volume. The rectangular volume can have a longest dimension in a direction the switch element and the corresponding memory element.
- Modified dimension is a lateral dimension of a memory cell stack that has been modified from those dimensions achieved by etch patterning, e.g., such as by an additional isotropic etch.
- MD can be a desired design rule implementation dimension.
- Smallest lateral dimension is a stack component, e.g., memory element, select element, etc., dimension other than length, e.g., width, depth, having the least magnitude, where length is oriented in the direction between memory element and select element.
- the word line CD can be defined by lithography or pitch multiplication, hard mask, and dry etch, mainly during a first part of the process through hard masking.
- the MD can be further defined from a CD by additional selective etching, e.g., isotropic etching.
- the lateral dimension, e.g., CD, of the relatively wider stack shown in FIG. 4A is greater than the lateral dimension, e.g., CD, of the relatively thinner stack shown in FIG. 4B .
- the LD of the memory element 414 A is the same as the LD of the switch element 410 A, in the stack shown in FIG. 4A .
- the LD of the memory element 414 B is the same as the LD of the switch element 410 B in the stack shown in FIG. 4B . That is, the ratio of LD of the memory element to LD of the switch element, e.g., LD(ME)/LD(SE), is 1 for the stacks shown in FIGS. 4A and 4B .
- Electrical performance of a memory cell is related to the LD and profile of the memory elements 414 A/B and switch elements 410 A/B. Therefore, the electrical performance of the memory elements 414 A/B and switch elements 410 A/B is not independent in the stacks shown in FIGS. 4A and 4B .
- FIGS. 5A and 5B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory elements in accordance with a number of embodiments of the present disclosure.
- FIGS. 5A and 5B illustrate a configuration and method by which the LD of the memory element and the LD of the switch element can be independent.
- Functionality of a memory cell can be modulated by controlling the dimension(s), e.g., LD, of the memory element with respect to the dimension(s), e.g., LD, of the switch element.
- the dimension(s) of the memory element are not independent of the dimension(s) of the switch element
- increasing the current density in the memory element by decreasing the dimension(s) of the memory element causes the current density to correspondingly increase by the same amount in the switch element.
- This can be detrimental to the functional characteristics of the switch element. That is, improving the operability of the memory element may decrease the operability of the switch element where the dimension(s) of the memory element are not independent of the dimension(s) of the switch element.
- FIG. 5A shows a stack formed by having word line 504 , third electrode 508 , switch element 510 , second electrode 512 , memory element 514 A, and first electrode 516 .
- FIG. 5B shows a stack formed by having word line 504 , third electrode 508 , switch element 510 , second electrode 512 , memory element 514 B, and first electrode 516 .
- memory element 514 A is relatively wider than memory element 514 B shown in FIG. 5B . All other stack components are substantially the same size in the stacks of FIGS. 5A and 5B .
- the stack shown in FIG. 5B can be formed from the stack shown in FIG. 5A .
- the stack shown in FIG. 5A can be subjected to a selective/isotropic process, which is step able to etch the memory element selectively with respect to other materials in a non-directional manner, e.g., selective to a particular material such as that from which the memory element is formed more than other materials and isotropic such that etching can have a horizontal effect.
- a selective/isotropic process which is step able to etch the memory element selectively with respect to other materials in a non-directional manner, e.g., selective to a particular material such as that from which the memory element is formed more than other materials and isotropic such that etching can have a horizontal effect.
- an isotropic dry etch that is able to selectively etch the memory element material can recess the memory element sidewalls without affecting the other exposed stack component materials.
- the selective/isotropic process includes an etch with an isotropic component (but does not necessarily intend that the etch be 100% isotropic). Also, selectivity need not be 100% selective to the intended particular material and completely exclude all other materials. For example, the same chemistry can have different etch rates for PCM and OTS material, neither of which may be null.
- the memory element sidewalls 513 shown in FIG. 5B are recessed with respect to other portions of the stack, e.g., relative to word line 504 , relative to switch element 510 , relative to an electrode, etc. Since the resulting lateral dimension of the memory element 514 B is less than the lateral dimension of the switch element 510 (switch element dimension did not change by the selective isotropic dry etch that is selective to the memory element material), LD(ME)/LD(SE) ⁇ 1.
- FIG. 5A shows a complete stack is formed, which might then be subjected to an etch selective to the memory element material, e.g., selective isotropic dry etch to a particular component material with respect to other materials
- the selective etch e.g., selective to the memory element material with respect to other materials
- can be implemented after directional etching of the memory element, but before directional etching of the underlying component, e.g., second electrode 512 . Therefore, another example dry etching sequence to accomplish a memory element of reduced dimension relative to other stack components, and/or word line 504 width, can be:
- the selective isotropic dry etch can have a same chemistry as the directional etch for a particular material, e.g., memory element material.
- the etch conditions can be altered to achieve an isotropic etch.
- a directional etch of the memory element 514 A can be implemented with a strong plasma, whereas the selective isotropic dry etch can use the same chemistry but different plasma conditions such as different pressure and/or by changing the (ion) bias voltage.
- the bias voltage (Vb) of a conductor dry etching chamber can be turned off with the pressure set to be higher relative to the directional etch bias voltage.
- ions in the plasma may be less accelerated to a surface of an in-situ wafer which is being processed in the etching chamber, e.g., upon which the stack is formed.
- the plasma-wafer interaction is chemical rather than physical.
- a gas mixture including hydrogen-based components can be used for the step able to etch the memory element material selectively with respect to other materials, e.g., selective isotropic dry etch where the gas mixture is selective to etch the memory element material more than other materials.
- an X-based gas mixture can be used for the step able to etch the switch element material selectively with respect to other materials, e.g., selective isotropic dry etch where the gas mixture is selective to etch the switch element material more than other materials.
- X can be one or more of fluorine (F), chlorine (Cl) or bromine (Br).
- Other isotropic etch processes can be used under certain circumstances such as a wet etch, e.g., where other stack components that may be affected are not yet exposed by a directional dry etch.
- FIGS. 6A and 6B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized switch elements in accordance with a number of embodiments of the present disclosure.
- FIGS. 6A and 6B also illustrate a configuration and method by which the LD of the memory element and the LD of the switch element can be independent by changing the dimension(s) of a switch element relative to a memory element.
- FIG. 6A shows a stack formed by having a word line 604 , third electrode 608 , switch element 610 A, second electrode 612 , memory element 614 , and first electrode 616 .
- FIG. 6B shows a stack formed by having word line 604 , third electrode 608 , switch element 610 B, second electrode 612 , memory element 614 , and first electrode 616 .
- switch element 610 A in the stack is relatively wider than switch element 610 B shown in the stack of FIG. 6B .
- all other stack components can be substantially the same size between the stacks shown in FIGS. 6A and 6B .
- the stack shown in FIG. 6B can be formed from the stack shown in FIG. 6A .
- the stack shown in FIG. 6A can be subjected to a step able to etch the memory element material selectively to other materials, e.g., selective isotropic dry etch selective to etch a particular material such as that from which the memory element is formed more than other materials and isotropic such that etching can have a horizontal etching effect on the switch element 610 A.
- a step able to etch the memory element material selectively to other materials e.g., selective isotropic dry etch selective to etch a particular material such as that from which the memory element is formed more than other materials and isotropic such that etching can have a horizontal etching effect on the switch element 610 A.
- an etch selective to the switch element material with respect to other materials can recess the switch element sidewalls without affecting the other exposed stack component materials, including the memory element.
- the switch element sidewalls 615 shown in FIG. 6B are recessed with respect to other portions of the stack, e.g., relative to word line 604 , relative to memory element 614 , relative to an electrode, etc. Since the resulting lateral dimension of the switch element 610 B is less than the lateral dimension of the memory element 614 (memory element dimension did not change by the selective isotropic dry etch that is selective to the switch element material), LD(ME)/LD(SE)>1.
- FIG. 6A shows a complete stack is first formed, which might then be subjected to a selective isotropic dry etch (selective to a particular component material), according to various embodiments of the present disclosure, the step able to etch the switch element material selectively to other materials, e.g., selective dry etch that etches the switch element material more than other materials, can be implemented after directional etching of the switch element 610 A, but before directional etching of the underlying component, e.g., third electrode 608 . Therefore, another example dry etching sequence to accomplish a switch element of reduced dimension relative to other stack components, and/or word line 604 width, can be:
- the selective isotropic dry etch can be similar to that described above with respect to the memory element 514 A shown in FIG. 5A , except instead being selective to the switch element 610 A material. In this manner, it is possible to modulate the switch element 610 B lateral dimension(s) as desired relative to lateral dimension(s) of other stack components, e.g., memory element 614 and/or electrode(s) and/or word line 604 .
- stack component dimension(s) including critical dimension and/or area in a plane perpendicular to the stack orientation, can be controlled in one or more of the following ways:
- FIGS. 7A and 7B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory and switch elements in accordance with a number of embodiments of the present disclosure.
- FIGS. 7A and 7B illustrate a combined configuration and method by which the lateral dimension(s), e.g., CD, of the memory element and the lateral dimension(s), e.g., CD, of the switch element can be independent.
- the lateral dimension(s) of both a switch element and a memory element can be changed relative to other stack components, e.g., electrodes, word line, bit line, etc.
- the lateral dimension(s) of the switch element and memory element can both be reduced by a same, or different, amount relative to one another.
- FIG. 7A shows a stack formed by having a word line 704 , third electrode 708 , switch element 710 A, second electrode 712 , memory element 714 A, and first electrode 716 .
- FIG. 7B shows a stack formed by having a word line 704 , third electrode 708 , switch element 710 B, second electrode 712 , memory element 714 B, and first electrode 716 .
- switch element 710 A is relatively wider than switch element 710 B shown in FIG. 7B .
- Memory element 714 A shown in FIG. 7A is relatively wider than memory element 714 B shown in FIG. 7B .
- FIG. 7B also shows that memory element 714 B is thinner relative to switch element 710 B.
- switch element 710 B can be reduced by an amount such that the switch element 710 B has the same dimension(s) as the memory element 714 B, or is thinner relative to memory element 714 B.
- all other stack components can be substantially the same size between the stacks shown in FIGS. 7A and 7B .
- the stack shown in FIG. 7B can be formed from the stack shown in FIG. 7A .
- the stack shown in FIG. 7A can be subjected to a plurality of selective isotropic dry etches, e.g., reach selective to a different material) so as to recess the material of the selected stack component without affecting the other exposed stack component materials.
- the memory element sidewalls 717 and switch element sidewalls 719 are both recessed with respect to other portions of the stack, e.g., relative to word line 704 , relative to an electrode, etc.
- the resulting lateral dimension of the memory element is less than the lateral dimension of the switch element, LD(ME)/LD(SE) ⁇ 1. According to various other embodiments, the resulting lateral dimension of the memory element is greater than the lateral dimension of the switch element such that LD(ME)/LD(SE)>1.
- FIG. 7A a completely formed stack is shown in FIG. 7A , which can be subjected to a plurality of selective isotropic dry etches, e.g., one selective to memory element material and one selective to switch element material
- the selective isotropic dry etches can be implemented respectively after directional etching of the particular stack component to be subjected to a selective isotropic dry etch, but before directional etching of the underlying stack component. Therefore, another example dry etching sequence that can be used to accomplish the result shown by the stack shown in FIG. 7B can be:
- FIGS. 8A and 8B illustrate cross-sectional views of stacks corresponding to a memory cell having non-vertical stack wall and different sized switch elements in accordance with a number of embodiments of the present disclosure. For any number of reasons, stack walls may not be formed to be completely vertical.
- FIGS. 8A and 8B show that the selective isotropic dry etch techniques described above can be applied to components of a stack having non-vertical stack wall to compensate for the different component dimensions that can result when the stack walls are not completely vertical.
- one or more selective isotropic dry etch can be used to modulate the stack sidewall slope, e.g., the memory element and/or switch element portions of the stack. Improving the verticality of a stack sidewall initially having a tapered profile can improve the verticality of the word line and/or bit line as well. Generally, better stack sidewall verticality facilitates better etching performance for memory cells with a large aspect ratio, and can reduce the risk of bit line-to-bit line leakage, as well.
- FIG. 8A shows a stack formed by having word line 804 , third electrode 808 , switch element 810 A, second electrode 812 , memory element 814 , and first electrode 816 .
- FIG. 8B shows a stack formed by having a word line 804 , third electrode 808 , switch element 810 B, second electrode 812 , memory element 814 , and first electrode 816 . Similar to that shown and described with respect to FIGS. 6A and 6B , the dimension(s) of switch element 810 A in the stack shown in FIG. 8A can be reduced to the result shown for switch element 810 B in the stack of FIG. 8B by a selective isotropic dry etch.
- the switch element 810 B in the stack shown in FIG. 8B is shown being reduced in lateral dimension(s) to those of the memory element 814 .
- Current density through a particular stack component e.g., memory element, switch element, is determined by the area of the component through which current can flow.
- the memory element 814 in the stack shown in FIG. 8A can have a higher current density than the switch element 810 A since the lateral dimension(s) of the memory element 814 (and thus the area bounded by the lateral dimension(s)) are less than the lateral dimension(s) of the switch element 810 A.
- switch element 810 B is now the same size as memory element 814 . Therefore, current densities can be made similar, e.g., brought back to an intended proportionality associated with vertical stack sidewall.
- a selective isotropic dry etch process can help in removing resputtered polymers, e.g., directional dry etch by-products, from the stack sidewalls corresponding to the word line and/or bit line respectively. Often the polymers on the stack sidewalls can induce a high vertical leakage in an array having such memory cells if not completely removed by wet cleaning. According to some embodiments, the selective isotropic dry etch process described herein can function to clean the stack sidewalls from even very low volatile polymers.
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Abstract
Description
- The present disclosure relates generally to semiconductor devices, and more particularly to memory cell architectures and methods of forming the same.
- Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistance variable memory, and flash memory, among others. Types of resistance variable memory include phase change material (PCM) memory, programmable conductor memory, and resistive random access memory (RRAM), among others.
- Non-volatile memory are utilized as memory devices for a wide range of electronic applications in need of high memory densities, high reliability, and data retention without power. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices.
- Constant challenges related to memory device fabrication are to decrease the size of a memory device, increase the storage density of a memory device, reduce power consumption, and/or limit memory device cost. Some memory devices include memory cells arranged in a two dimensional array, in which memory cells are all arranged in a same plane. In contrast, various memory devices include memory cells arranged into a three dimensional (3D) array having multiple levels of memory cells.
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FIG. 1 is a perspective view of a portion of a memory array in accordance with a number of embodiments of the present disclosure. -
FIG. 2 illustrates a three dimensional memory array in accordance with a number of embodiments of the present disclosure. -
FIGS. 3A and 3B illustrate cross-sectional views of memory cells in perpendicular directions in accordance with a number of embodiments of the present disclosure. -
FIGS. 4A and 4B illustrate cross-sectional views in a same cross section of different sized stacks corresponding to a memory cell in accordance with a number of embodiments of the present disclosure. -
FIGS. 5A and 5B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory elements in accordance with a number of embodiments of the present disclosure. -
FIGS. 6A and 6B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized switch elements in accordance with a number of embodiments of the present disclosure. -
FIGS. 7A and 7B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory and switch elements in accordance with a number of embodiments of the present disclosure. -
FIGS. 8A and 8B illustrate cross-sectional views of stacks corresponding to a memory cell having non-vertical stack wall and different sized switch elements in accordance with a number of embodiments of the present disclosure. - Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
- Embodiments of the present disclosure implement a memory cell in a cross point memory array in which the switch element dimensions are independent from the memory element dimensions. Size independence between the switch element and the memory element allows for an unlimited number of combinations of memory element size relative to select element size, which in turn facilitates addressing specific electrical properties associated with particular cross point array applications. With the ability to independently size the switch element and the memory element in a same stack of materials forming a memory cell, e.g., using phase change material (PCM), in a cross point array, the current density for the memory element can be different than the current density for the switch element. For example, in a phase change mechanism in the memory element can be improved without resulting in undue switching stress on the switch element.
- The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 106 may reference element “06” in
FIG. 1 , and a similar element may be referenced as 306 inFIG. 3A . Also, as used herein, “a number of” a particular element and/or feature can refer to one or more of such elements and/or features. - As used herein, the term “substantially” intends that the modified characteristic needs not be absolute, but is close enough so as to achieve the advantages of the characteristic. For example, “substantially parallel” is not limited to absolute parallelism, and can include orientations that are at least closer to a parallel orientation than a perpendicular orientation. Similarly, “substantially orthogonal” is not limited to absolute orthogonalism, and can include orientations that are at least closer to a perpendicular orientation than a parallel orientation.
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FIG. 1 is a perspective view of a portion of amemory array 100 in accordance with a number of embodiments of the present disclosure. In the example shown inFIG. 1 ,memory array 100 is a cross point memory/switch memory array, e.g., a phase change memory array. However, embodiments of the present disclosure are not so limited. Embodiments of the present disclosure can comprise a two dimensional (2D) cross point memory array, or a three dimensional (3D) cross point memory array with more decks between word lines and bit lines. -
Array 100 can be a cross-point array havingmemory cells 102 located at the intersections of a number of conductive lines, e.g.,access lines 104, which may be referred to herein as word lines, and a number of conductive lines, e.g., data/sense lines 106, which may be referred to herein as bit lines. As illustrated inFIG. 1 ,word lines 104 can be parallel or substantially parallel to each other and can be orthogonal tobit lines 106, which can be parallel or substantially parallel to each other. However, embodiments are not so limited.Word lines 104 and/orbit lines 106 can be a conductive material such as tungsten, copper, titanium, aluminum, and/or other metals, for example. However, embodiments are not so limited. In a number of embodiments,array 100 can be a portion, e.g., a level, of a three-dimensional array, e.g., a multi-level array, (described further with respect toFIG. 2 ) in which other arrays similar toarray 100 are at different levels, for example above and/or belowarray 100. - Each
memory cell 102 can include amemory element 114, e.g., storage element, coupled in series with arespective switch element 110, e.g., selector device, and/or access device. The memory cell can have a number of electrodes adjacent thememory element 114 andswitch element 110, including a first, e.g., top, electrode, second, e.g., middle, electrode, and/or third, e.g., bottom, electrode. Thememory element 114 can be, for example, a resistive memory element. Thememory element 114 can be formed between a pair of electrodes, e.g.,first electrode 116 andsecond electrode 112. The memory element can be comprised of a resistance variable material such as a phase change memory (PCM) material, for example. As an example, the PCM material can be a chalcogenide alloy such as a Germanium-Antimony-Tellurium (GST) material, e.g., Ge—Sb—Te materials such as Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge8Sb5Te8, Ge4Sb4Te7, etc., or an indium(In)-antimony(Sb)-tellurium(Te) (IST) material, e.g., In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc., among other phase change memory materials. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. Other phase change memory materials can include Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—Sb—Ge, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—Sb—Te—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, Ge—Te—Sn—Ni, Ge—Te—Sn—Pd, and Ge—Te—Sn—Pt, for example. However, embodiments of the present disclosure are not limited to a particular type of PCM material. Further, embodiments are not limited to memory elements comprising PCM materials. For instance, the memory elements can comprise a number of resistance variable materials such as binary metal oxides, colossal magnetoresistive materials, and/or various polymer-based resistive variable materials, among others. - For simplicity,
FIG. 1 shows thememory element 114 and theswitch element 110 having similar dimensions. However, as is discussed below, amemory cell 102 can be formed with amemory element 114 having different dimension(s), e.g., critical dimension, cross-sectional area, etc., than theswitch element 110. - The
switch element 110 can be a two terminal device such as a diode, an ovonic threshold switch (OTS), or an ovonic memory switch (OMS). However, embodiments of the present disclosure are not limited to a particular type ofswitch element 110. For example, theswitch element 110 can be a field effect transistor (FET), a bipolar junction transistor (BJT), or a diode, among other types of selector devices. Theswitch element 110 can be formed between a pair of electrodes, e.g., the second electrode and athird electrode FIG. 1 illustrates a configuration having thememory element 114 formed over theswitch element 110, embodiments of the present disclosure are not so limited. According to various embodiments of the present disclosure theswitch element 110 can be formed over thememory element 114, for example. -
Electrodes - In a number of embodiments, the
switch elements 110 corresponding tomemory cells 102 can be OTS's having a chalcogenide selector device material. In such embodiments, the chalcogenide material of theswitch element 110 may not actively change phase, e.g., between amorphous and crystalline, such as a chalcogenide resistance variable material of the memory element. Instead, the chalcogenide material of the switch element can change between an “on” and “off” state depending on the voltage potential applied acrossmemory cell 102. For example, the “state” of the OTS can change when a current through the OTS exceeds a threshold current or a voltage across the OTS exceeds a threshold voltage. Once the threshold current or voltage is reached, an on state can be triggered and the OTS can be in a conductive state. In this example, if the current or voltage potential drops below a threshold value, the OTS can return to a non-conductive state. - In a number of embodiments, the
memory element 114 can comprise one or more of the same material(s) as theswitch element 110. However, embodiments are not so limited. For example,memory element 114 andswitch element 110 can comprise different materials. -
Memory cells 102 can be programmed to a target data state, e.g., corresponding to a particular resistance state, by applying sources of an electrical field or energy, such as positive or negative electrical pulses, to the cells, e.g., to the storage element of the cells, for a particular duration. The electrical pulses can be, for example, positive or negative voltage or current pulses. -
FIG. 2 illustrates a three dimensional (3D) memory array in accordance with a number of embodiments of the present disclosure. The 3D memory array comprises a plurality of memory cells 202-1, 202-2, e.g., memory element in series with a switch element as described with respect toFIG. 1 .FIG. 2 shows a first memory array comprising memory cells 202-1 formed between word lines 204-1 andbits lines 206, and a second memory array comprising memory cells 202-2 formed between word lines 204-2 and bits lines 206. That is, the first memory array formed belowbit lines 206 and the second memory array formed abovebit lines 206 sharecommon bit lines 206 therebetween. -
FIG. 2 is a simplified diagram that does not precisely reflect the three dimensional physical dimensions of the various features illustrated, including the exact proximity of features to one another.FIG. 2 should not be considered as to be representative of the precise topological positioning of the various elements. Rather,FIG. 2 provides an overview of the electrical scheme for a 3D memory array, and the approximate relative arrangement of the various features. AlthoughFIG. 2 shows a 3D array comprising 2 memory arrays, embodiments of the present invention are not so limited, and can include additional memory array(s) arranged into a number of levels. -
FIGS. 3A and 3B illustrate cross-sectional views of memory cells in perpendicular directions in accordance with a number of embodiments of the present disclosure.FIG. 3A shows a cross-section in a first direction, e.g., side view, of a portion of a memory array, such as that shown inFIG. 1 .FIG. 3B shows a cross-section in a second direction, e.g., end view, of a portion of a memory array, such as that shown inFIG. 1 .FIGS. 3A and 3B show some additional detail than that shown and described with respect toFIG. 1 . The memory cells shown inFIGS. 3A and 3B can be similar to those described with respect toFIGS. 1 and 2 . - As shown in
FIG. 3A , a stack of materials can be formed over aword line 304. For example, the stack of materials can include athird electrode 308 formed over theword line 304, aswitch element 310 formed over thethird electrode 308, asecond electrode 312 formed over theswitch element 310, amemory element 314 formed over thesecond electrode 312, and afirst electrode 316 formed over thememory element 314. Abit line 306 can be formed over the stack extending left-to-right inFIG. 3A and into-and-out-of the paper inFIG. 3B .Word line 304 extends perpendicularly tobit line 306. That is,word line 304 extends into-and-out-of the paper inFIG. 3A and left-to-right inFIG. 3B . Likewise, thethird electrode 308 can extend similarly to theword line 304, as shown inFIGS. 3A and 3B . - For simplicity, all the components of the stack are shown having similar measurements in each of several directions. However, according to embodiments disclosed herein, the
memory element 314 andswitch element 310 can have one or more different directions from one another and/or electrode(s). InFIGS. 3A and 3B , the stack of materials is shown being square when viewed from the side and end perspectives. - As shown in
FIG. 3A , sealingmaterial 321 can be formed around the word line stacks and fillingmaterial 320 can be formed in the areas between the word line stacks. Adielectric material 322 can be formed over sealingmaterial 321 and fillingmaterial 320 in the areas between the word line stacks, as shown inFIG. 3A . - As shown in
FIG. 3B , sealingmaterial 324 can be formed around the bit line stacks and fillingmaterial 323 can be formed in the areas between the bit line stacks.Dielectric material 322 can be formed over sealingmaterial 324 and fillingmaterial 323 in the areas between the bit line stacks, as shown inFIG. 3B . - The
cross point array 100 of memory cells shown inFIGS. 1 and 2 can be created through dry etch patterning in two perpendicular directions, e.g., corresponding to the direction of the word lines 304 and the bit lines 306. Materials corresponding to respective conductive lines and components of the memory cell can be bulk deposited and etched to form the various features. The dry etch patterning in two perpendicular directions forms the various conductive lines and the stacks corresponding to individual memory cells. For example, a first etch can define one direction of the stack, e.g., a row structure separated by first trenches, self-aligned to the underlying conductive lines, e.g., word lines 304, which in turn can be connected to other circuitry. - As shown in
FIG. 3A and described above, the row structures and trenches can be sealed in between theword line 304, e.g., with sealingmaterial 321, and filled with fillingmaterial 320 anddielectric material 322. Subsequently, a material comprising thebit lines 306, e.g., conductive material, can be deposited on top of the row structures, sealingmaterial 321, fillingmaterial 320, anddielectric material 322. A second etch process can be used to form second trenches that define thebit lines 306 in a direction perpendicular to the word lines 304, and again self-aligned to the stacks associated with the memory cells (down to the third electrodes 308). Thereafter, the second trenches andthird electrodes 308 can be sealed, e.g., by sealingmaterials 324 and fillingmaterial 323, and the second trenches filled bydielectric material 322. The result of the above-described sequence is an array of stacks, e.g., active pillars, corresponding to respective memory cells and isolated from one another bydielectric material 322.Word lines 304 below the memory cells connect the stacks in one direction, and bitlines 306 above the memory cells connect the stacks in a perpendicular direction. -
FIGS. 4A and 4B illustrate cross-sectional views in a same cross section of different sized stacks corresponding to a memory cell in accordance with a number of embodiments of the present disclosure. That is,FIGS. 4A and 4B show the same cross section before (FIG. 4A ) and after (FIG. 4B ) a dimension modification, e.g., isotropic etch. The respective stacks shown inFIGS. 4A and 4B can be formed by dry etch patterning in two perpendicular directions described above with respect toFIGS. 3A and 3B . For example, dry etching can be used to form the stacks corresponding to individual memory cells. As will be further described according to embodiments herein, dry etching can be used to control the various dimensions of the stack, e.g., width and length of a cross-sectional area of the switch and memory elements, in a plane perpendicular to a direction between the switch element and the memory element. - For example in
FIG. 4A , the dry etch patterning in two perpendicular directions can be used to form a relatively wider stack (comprisingword line 404A,third electrode 408A,switch element 410A,second electrode 412A,memory element 414A, andfirst electrode 416A). InFIG. 4B , a relatively thinner stack (comprisingword line 404B,third electrode 408B,switch element 410B,second electrode 412B,memory element 414B, andfirst electrode 416B). Because the dry etch patterning in two perpendicular directions is self-aligning, all of the components of the relatively wider stack, shown inFIG. 4A , have the same dimensions. Further, all of the components are wider than all of the components of the relatively thinner stack shown inFIG. 4B . That is, using the dry etch patterning in two perpendicular directions to control width of the memory element, for example, results in the widths of all other components in the stack being likewise controlled to the same width. - During the dry etch patterning in two perpendicular directions to form stacks corresponding to memory cells, it is beneficial to have a constant vertical etch profile so as to better define bottom components. This ensures proper isolation throughout the stack (particularly for bottom components), and avoids worsening aspect ratios.
- Critical dimension (CD) is the finest line resolvable associated with etch patterning, e.g., etching using a pattern to delineate areas to be etched from areas not to be etched. As used herein, lateral dimension (LD) is a dimension in a plane that is perpendicular to a direction between the switch element and a corresponding memory element of a memory cell, e.g., perpendicular to the orientation of the stack of materials comprising the memory cell. The LD can be a CD (discussed above) or a modified dimension (discussed below). For example, a stack can have a rectangular volume. The rectangular volume can have a longest dimension in a direction the switch element and the corresponding memory element.
- Modified dimension (MD) is a lateral dimension of a memory cell stack that has been modified from those dimensions achieved by etch patterning, e.g., such as by an additional isotropic etch. For example, MD can be a desired design rule implementation dimension. Smallest lateral dimension is a stack component, e.g., memory element, select element, etc., dimension other than length, e.g., width, depth, having the least magnitude, where length is oriented in the direction between memory element and select element.
- For dry etch patterning in two perpendicular directions, the word line CD can be defined by lithography or pitch multiplication, hard mask, and dry etch, mainly during a first part of the process through hard masking. According to various embodiments of the present disclosure, and as described below, the MD can be further defined from a CD by additional selective etching, e.g., isotropic etching.
- The lateral dimension, e.g., CD, of the relatively wider stack shown in
FIG. 4A is greater than the lateral dimension, e.g., CD, of the relatively thinner stack shown inFIG. 4B . However, the LD of thememory element 414A is the same as the LD of theswitch element 410A, in the stack shown inFIG. 4A . The LD of thememory element 414B is the same as the LD of theswitch element 410B in the stack shown inFIG. 4B . That is, the ratio of LD of the memory element to LD of the switch element, e.g., LD(ME)/LD(SE), is 1 for the stacks shown inFIGS. 4A and 4B . Electrical performance of a memory cell is related to the LD and profile of thememory elements 414A/B and switchelements 410A/B. Therefore, the electrical performance of thememory elements 414A/B and switchelements 410A/B is not independent in the stacks shown inFIGS. 4A and 4B . -
FIGS. 5A and 5B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory elements in accordance with a number of embodiments of the present disclosure.FIGS. 5A and 5B illustrate a configuration and method by which the LD of the memory element and the LD of the switch element can be independent. Functionality of a memory cell can be modulated by controlling the dimension(s), e.g., LD, of the memory element with respect to the dimension(s), e.g., LD, of the switch element. Where the dimension(s) of the memory element are not independent of the dimension(s) of the switch element, increasing the current density in the memory element by decreasing the dimension(s) of the memory element causes the current density to correspondingly increase by the same amount in the switch element. This can be detrimental to the functional characteristics of the switch element. That is, improving the operability of the memory element may decrease the operability of the switch element where the dimension(s) of the memory element are not independent of the dimension(s) of the switch element. -
FIG. 5A shows a stack formed by havingword line 504,third electrode 508,switch element 510,second electrode 512,memory element 514A, andfirst electrode 516.FIG. 5B shows a stack formed by havingword line 504,third electrode 508,switch element 510,second electrode 512,memory element 514B, andfirst electrode 516. As shown inFIG. 5A ,memory element 514A is relatively wider thanmemory element 514B shown inFIG. 5B . All other stack components are substantially the same size in the stacks ofFIGS. 5A and 5B . - According to various embodiments, the stack shown in
FIG. 5B can be formed from the stack shown inFIG. 5A . To form the stack shown inFIG. 5B , the stack shown inFIG. 5A can be subjected to a selective/isotropic process, which is step able to etch the memory element selectively with respect to other materials in a non-directional manner, e.g., selective to a particular material such as that from which the memory element is formed more than other materials and isotropic such that etching can have a horizontal effect. As shown, an isotropic dry etch that is able to selectively etch the memory element material can recess the memory element sidewalls without affecting the other exposed stack component materials. The selective/isotropic process includes an etch with an isotropic component (but does not necessarily intend that the etch be 100% isotropic). Also, selectivity need not be 100% selective to the intended particular material and completely exclude all other materials. For example, the same chemistry can have different etch rates for PCM and OTS material, neither of which may be null. - After the selective etch, e.g., selective isotropic dry etch to the memory element material with respect to other materials, the memory element sidewalls 513 shown in
FIG. 5B are recessed with respect to other portions of the stack, e.g., relative toword line 504, relative to switchelement 510, relative to an electrode, etc. Since the resulting lateral dimension of thememory element 514B is less than the lateral dimension of the switch element 510 (switch element dimension did not change by the selective isotropic dry etch that is selective to the memory element material), LD(ME)/LD(SE)<1. - Although
FIG. 5A shows a complete stack is formed, which might then be subjected to an etch selective to the memory element material, e.g., selective isotropic dry etch to a particular component material with respect to other materials, according to various embodiments of the present disclosure, the selective etch, e.g., selective to the memory element material with respect to other materials, can be implemented after directional etching of the memory element, but before directional etching of the underlying component, e.g.,second electrode 512. Therefore, another example dry etching sequence to accomplish a memory element of reduced dimension relative to other stack components, and/orword line 504 width, can be: -
- 1. Directional etch
first electrode 516 - 2. Directional
etch memory element 514A - 3. Selective etch able to etch the
memory element 514A selective with respect to other materials) - 4. Directional etch
second electrode 512 - 5. Directional
etch switch element 510 - 6. Directional etch
third electrode 508 - 7. Directional
etch word line 504
The selective etch step can alternatively be performed at other times during the process, e.g., after the directional etch ofword line 504, since the etch is performed to etch the memory element and to avoid etching materials other than the memory element material. The amount of reduction in a lateral dimension of the material removed by the selective isotropic dry etch can be controlled, for example, by the duration of the selective isotropic dry etch, among others. With the ability to independently adjust dimension(s) of one stack component, e.g.,memory element 514A lateral dimension relative to switchelement 510 lateral dimensions, electrical characteristics of the stack, e.g., current density inmemory element 514B andswitch element 510 can be independently controlled to improve operating characteristics.
- 1. Directional etch
- According to a number of embodiments of the present disclosure, the selective isotropic dry etch can have a same chemistry as the directional etch for a particular material, e.g., memory element material. However, the etch conditions can be altered to achieve an isotropic etch. For example, a directional etch of the
memory element 514A can be implemented with a strong plasma, whereas the selective isotropic dry etch can use the same chemistry but different plasma conditions such as different pressure and/or by changing the (ion) bias voltage. According to a number of embodiments, the bias voltage (Vb) of a conductor dry etching chamber can be turned off with the pressure set to be higher relative to the directional etch bias voltage. As a result, ions in the plasma may be less accelerated to a surface of an in-situ wafer which is being processed in the etching chamber, e.g., upon which the stack is formed. Thus, there may be little, if any, bombardment on exposed surface layers. Hence, the plasma-wafer interaction is chemical rather than physical. - According to some embodiments, a gas mixture including hydrogen-based components can be used for the step able to etch the memory element material selectively with respect to other materials, e.g., selective isotropic dry etch where the gas mixture is selective to etch the memory element material more than other materials. Further, an X-based gas mixture can be used for the step able to etch the switch element material selectively with respect to other materials, e.g., selective isotropic dry etch where the gas mixture is selective to etch the switch element material more than other materials. In this example, X can be one or more of fluorine (F), chlorine (Cl) or bromine (Br). Other isotropic etch processes can be used under certain circumstances such as a wet etch, e.g., where other stack components that may be affected are not yet exposed by a directional dry etch.
-
FIGS. 6A and 6B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized switch elements in accordance with a number of embodiments of the present disclosure.FIGS. 6A and 6B also illustrate a configuration and method by which the LD of the memory element and the LD of the switch element can be independent by changing the dimension(s) of a switch element relative to a memory element. -
FIG. 6A shows a stack formed by having aword line 604,third electrode 608,switch element 610A,second electrode 612,memory element 614, andfirst electrode 616.FIG. 6B shows a stack formed by havingword line 604,third electrode 608,switch element 610B,second electrode 612,memory element 614, andfirst electrode 616. As shown inFIG. 6A ,switch element 610A in the stack is relatively wider thanswitch element 610B shown in the stack ofFIG. 6B . In this example embodiment, all other stack components can be substantially the same size between the stacks shown inFIGS. 6A and 6B . - According to various embodiments, the stack shown in
FIG. 6B can be formed from the stack shown inFIG. 6A . To form the stack shown inFIG. 6B , the stack shown inFIG. 6A can be subjected to a step able to etch the memory element material selectively to other materials, e.g., selective isotropic dry etch selective to etch a particular material such as that from which the memory element is formed more than other materials and isotropic such that etching can have a horizontal etching effect on theswitch element 610A. As shown, an etch selective to the switch element material with respect to other materials can recess the switch element sidewalls without affecting the other exposed stack component materials, including the memory element. - After the selective etch, e.g., selective dry etch to etch the switch element material more than other materials, the switch element sidewalls 615 shown in
FIG. 6B are recessed with respect to other portions of the stack, e.g., relative toword line 604, relative tomemory element 614, relative to an electrode, etc. Since the resulting lateral dimension of theswitch element 610B is less than the lateral dimension of the memory element 614 (memory element dimension did not change by the selective isotropic dry etch that is selective to the switch element material), LD(ME)/LD(SE)>1. - Although
FIG. 6A shows a complete stack is first formed, which might then be subjected to a selective isotropic dry etch (selective to a particular component material), according to various embodiments of the present disclosure, the step able to etch the switch element material selectively to other materials, e.g., selective dry etch that etches the switch element material more than other materials, can be implemented after directional etching of theswitch element 610A, but before directional etching of the underlying component, e.g.,third electrode 608. Therefore, another example dry etching sequence to accomplish a switch element of reduced dimension relative to other stack components, and/orword line 604 width, can be: -
- 1. Directional etch
first electrode 616 - 2. Directional
etch memory element 614 - 3. Directional etch
second electrode 612 - 4. Directional
etch switch element 610A - 5. Selective etch able to etch the
switch element 610A selective to other materials. - 6. Directional etch
third electrode 608 - 7. Directional
etch word line 604
The selective etch step can alternatively be performed at other times during the process, e.g., after the directional etch ofword line 610A, since the etch is performed to etch the switch element material and to avoid etching materials other than the switch element material. The amount of reduction in a lateral dimension of the material removed by the selective isotropic dry etch can be controlled, for example, by the duration of the selective isotropic dry etch, among others. With the ability to independently adjust dimension(s) of another stack component, e.g.,switch element 610A lateral dimension relative to selectelement 510 lateral dimensions, electrical characteristics of the stack, e.g., current density inmemory element 614 and switch element 61011 can further be independently controlled to improve operating characteristics.
- 1. Directional etch
- According to a number of embodiments of the present disclosure, the selective isotropic dry etch can be similar to that described above with respect to the
memory element 514A shown inFIG. 5A , except instead being selective to theswitch element 610A material. In this manner, it is possible to modulate theswitch element 610B lateral dimension(s) as desired relative to lateral dimension(s) of other stack components, e.g.,memory element 614 and/or electrode(s) and/orword line 604. Considering the directional and selective isotropic dry etches, stack component dimension(s), including critical dimension and/or area in a plane perpendicular to the stack orientation, can be controlled in one or more of the following ways: -
- 1. Reduce lateral dimension(s) of all components of the entire stack (including both memory element and switch element) by directional dry etch, e.g., via lithography or pitch multiplication and hard mask etch process.
- 2. Reduce the lateral dimension(s) of only the memory element via a selective isotropic dry etch (selective to memory element material).
- 3. Reduce the lateral dimension(s) of only the switch element via a selective isotropic dry etch (selective to switch element material).
Reduction of lateral dimensions of components in the stack can be implemented on walls of a stack, e.g., stack walls having a direction parallel to edges of the word line and/or stack walls having a direction parallel to edges of the word line. For example, the reduction can be applied to walls along a single direction or along multiple, e.g., perpendicular, directions, as discussed further below. Stack component lateral dimension(s) can be relatively increased, for example, by increasing the lateral dimension(s) of the entire stack and selectively reducing lateral dimension(s) of certain components, thus leaving lateral dimension(s) of other stack components relatively wider.
-
FIGS. 7A and 7B illustrate cross-sectional views of stacks corresponding to a memory cell having different sized memory and switch elements in accordance with a number of embodiments of the present disclosure.FIGS. 7A and 7B illustrate a combined configuration and method by which the lateral dimension(s), e.g., CD, of the memory element and the lateral dimension(s), e.g., CD, of the switch element can be independent. According to this example embodiment the lateral dimension(s) of both a switch element and a memory element can be changed relative to other stack components, e.g., electrodes, word line, bit line, etc. Furthermore, the lateral dimension(s) of the switch element and memory element can both be reduced by a same, or different, amount relative to one another. -
FIG. 7A shows a stack formed by having aword line 704,third electrode 708,switch element 710A,second electrode 712,memory element 714A, andfirst electrode 716.FIG. 7B shows a stack formed by having aword line 704,third electrode 708, switch element 710B,second electrode 712,memory element 714B, andfirst electrode 716. As shown inFIG. 7A ,switch element 710A is relatively wider than switch element 710B shown inFIG. 7B .Memory element 714A shown inFIG. 7A is relatively wider thanmemory element 714B shown inFIG. 7B . Furthermore,FIG. 7B also shows thatmemory element 714B is thinner relative to switch element 710B. Although,FIG. 7B showsmemory element 714B being reduced by an amount such that it is thinner relative to switch element 710B, according to other embodiments switch element 710B can be reduced by an amount such that the switch element 710B has the same dimension(s) as thememory element 714B, or is thinner relative tomemory element 714B. In this example embodiment, all other stack components can be substantially the same size between the stacks shown inFIGS. 7A and 7B . - According to various embodiments, the stack shown in
FIG. 7B can be formed from the stack shown inFIG. 7A . To form the stack shown inFIG. 7B , the stack shown inFIG. 7A can be subjected to a plurality of selective isotropic dry etches, e.g., reach selective to a different material) so as to recess the material of the selected stack component without affecting the other exposed stack component materials. - After a step able to etch the switch element material selectively to other materials, e.g., selective dry etch to etch the switch element material more than other materials, and after a step able to etch the memory element material selectively to other materials, e.g., selective isotropic dry etch to etch the memory element material more than other materials, the memory element sidewalls 717 and switch element sidewalls 719 are both recessed with respect to other portions of the stack, e.g., relative to
word line 704, relative to an electrode, etc. Also the resulting lateral dimension of the memory element is less than the lateral dimension of the switch element, LD(ME)/LD(SE)<1. According to various other embodiments, the resulting lateral dimension of the memory element is greater than the lateral dimension of the switch element such that LD(ME)/LD(SE)>1. - As discussed with respect to
FIGS. 5A , 5B, 6A, and 6B, although a completely formed stack is shown inFIG. 7A , which can be subjected to a plurality of selective isotropic dry etches, e.g., one selective to memory element material and one selective to switch element material, according to various embodiments of the present disclosure, the selective isotropic dry etches can be implemented respectively after directional etching of the particular stack component to be subjected to a selective isotropic dry etch, but before directional etching of the underlying stack component. Therefore, another example dry etching sequence that can be used to accomplish the result shown by the stack shown inFIG. 7B can be: -
- 1. Directional etch
first electrode 716 - 2. Directional
etch memory element 714A - 3. Selective etch able to etch the
memory element 714A selective to other materials - 4. Directional etch
second electrode 712 - 5. Directional
etch switch element 710A - 6. Selective able to etch the
switch element 710A selective to other materials - 7. Directional etch
third electrode 708 - 8. Directional
etch word line 704
The respective selective etch steps can alternatively be performed in an order other than that shown in the process above. The amount of reduction in a lateral dimension of the material removed by a particular selective isotropic dry etch can be controlled, for example, by the duration of the particular selective isotropic dry etch. Respective selective isotropic dry etches can have different durations, for example, so as to independently control amounts of the selected material to be removed thereby.
- 1. Directional etch
-
FIGS. 8A and 8B illustrate cross-sectional views of stacks corresponding to a memory cell having non-vertical stack wall and different sized switch elements in accordance with a number of embodiments of the present disclosure. For any number of reasons, stack walls may not be formed to be completely vertical.FIGS. 8A and 8B show that the selective isotropic dry etch techniques described above can be applied to components of a stack having non-vertical stack wall to compensate for the different component dimensions that can result when the stack walls are not completely vertical. - That is, one or more selective isotropic dry etch can be used to modulate the stack sidewall slope, e.g., the memory element and/or switch element portions of the stack. Improving the verticality of a stack sidewall initially having a tapered profile can improve the verticality of the word line and/or bit line as well. Generally, better stack sidewall verticality facilitates better etching performance for memory cells with a large aspect ratio, and can reduce the risk of bit line-to-bit line leakage, as well.
-
FIG. 8A shows a stack formed by havingword line 804,third electrode 808,switch element 810A,second electrode 812,memory element 814, andfirst electrode 816.FIG. 8B shows a stack formed by having aword line 804,third electrode 808,switch element 810B,second electrode 812,memory element 814, andfirst electrode 816. Similar to that shown and described with respect toFIGS. 6A and 6B , the dimension(s) ofswitch element 810A in the stack shown inFIG. 8A can be reduced to the result shown forswitch element 810B in the stack ofFIG. 8B by a selective isotropic dry etch. - The
switch element 810B in the stack shown inFIG. 8B is shown being reduced in lateral dimension(s) to those of thememory element 814. Current density through a particular stack component, e.g., memory element, switch element, is determined by the area of the component through which current can flow. As such, thememory element 814 in the stack shown inFIG. 8A can have a higher current density than theswitch element 810A since the lateral dimension(s) of the memory element 814 (and thus the area bounded by the lateral dimension(s)) are less than the lateral dimension(s) of theswitch element 810A. After a selective isotropic dry etch is used to reduce lateral dimension(s) ofswitch element 810A, as shown in the stack ofFIG. 8B ,switch element 810B is now the same size asmemory element 814. Therefore, current densities can be made similar, e.g., brought back to an intended proportionality associated with vertical stack sidewall. - Some additional benefits can be realized from the memory cell configurations and methods for achieving same than those previously discussed including word line and/or bit line cleaning. A selective isotropic dry etch process can help in removing resputtered polymers, e.g., directional dry etch by-products, from the stack sidewalls corresponding to the word line and/or bit line respectively. Often the polymers on the stack sidewalls can induce a high vertical leakage in an array having such memory cells if not completely removed by wet cleaning. According to some embodiments, the selective isotropic dry etch process described herein can function to clean the stack sidewalls from even very low volatile polymers.
- Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.
- In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
Claims (35)
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Cited By (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140349413A1 (en) * | 2013-05-22 | 2014-11-27 | Sungyoon CHUNG | Semiconductor devices and methods of manufacturing the same |
US20160072061A1 (en) * | 2014-09-10 | 2016-03-10 | Kabushiki Kaisha Toshiba | Non-volatile memory device |
US9691475B2 (en) * | 2015-03-19 | 2017-06-27 | Micron Technology, Inc. | Constructions comprising stacked memory arrays |
CN107104121A (en) * | 2016-02-22 | 2017-08-29 | 三星电子株式会社 | Memory device and the method for manufacturing memory device |
US20180254412A1 (en) * | 2017-03-01 | 2018-09-06 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
US20180315475A1 (en) * | 2017-04-28 | 2018-11-01 | Micron Technology, Inc. | Programming enhancement in self-selecting memory |
US20180331283A1 (en) * | 2015-07-24 | 2018-11-15 | Micron Technology, Inc. | Array Of Cross Point Memory Cells |
US10141502B2 (en) | 2016-03-15 | 2018-11-27 | Samsung Electronics Co., Ltd. | Semiconductor memory devices |
US20190044061A1 (en) * | 2018-09-28 | 2019-02-07 | Intel Corporation | Memory cells having increased structural stability |
US10424730B2 (en) | 2018-02-09 | 2019-09-24 | Micron Technology, Inc. | Tapered memory cell profiles |
US10541364B2 (en) | 2018-02-09 | 2020-01-21 | Micron Technology, Inc. | Memory cells with asymmetrical electrode interfaces |
CN110875353A (en) * | 2018-08-30 | 2020-03-10 | 台湾积体电路制造股份有限公司 | Memory device and forming method thereof |
US10680057B2 (en) | 2017-01-12 | 2020-06-09 | Micron Technology, Inc. | Methods of forming a capacitor comprising ferroelectric material and including current leakage paths having different total resistances |
US10686013B2 (en) | 2018-09-03 | 2020-06-16 | Samsung Electronics Co., Ltd. | Memory device |
US10693065B2 (en) | 2018-02-09 | 2020-06-23 | Micron Technology, Inc. | Tapered cell profile and fabrication |
US10727336B2 (en) | 2014-04-24 | 2020-07-28 | Micron Technology, Inc. | Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors |
US10741567B2 (en) | 2015-02-17 | 2020-08-11 | Micron Technology, Inc. | Memory cells |
US10784374B2 (en) | 2014-10-07 | 2020-09-22 | Micron Technology, Inc. | Recessed transistors containing ferroelectric material |
US10811462B2 (en) | 2015-10-27 | 2020-10-20 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
US10854813B2 (en) | 2018-02-09 | 2020-12-01 | Micron Technology, Inc. | Dopant-modulated etching for memory devices |
US10862031B2 (en) * | 2019-03-01 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to effectively suppress heat dissipation in PCRAM devices |
CN112349746A (en) * | 2019-08-07 | 2021-02-09 | 美光科技公司 | Access line formation for memory arrays |
US20210057645A1 (en) * | 2019-08-23 | 2021-02-25 | Globalfoundries Singapore Pte. Ltd. | Memory device and method of forming the same |
US11133465B2 (en) * | 2019-10-14 | 2021-09-28 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional phase-change memory devices |
US11170834B2 (en) | 2019-07-10 | 2021-11-09 | Micron Technology, Inc. | Memory cells and methods of forming a capacitor including current leakage paths having different total resistances |
US11195999B2 (en) * | 2019-11-13 | 2021-12-07 | International Business Machines Corporation | Phase change material with reduced reset state resistance drift |
US20210384427A1 (en) * | 2020-06-09 | 2021-12-09 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices |
US11227991B2 (en) | 2016-03-18 | 2022-01-18 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US11309490B2 (en) * | 2020-02-10 | 2022-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory devices and methods of forming the same |
US11348871B2 (en) * | 2017-08-29 | 2022-05-31 | Micron Technology, Inc. | Integrated assemblies |
US11355554B2 (en) * | 2020-05-08 | 2022-06-07 | Micron Technology, Inc. | Sense lines in three-dimensional memory arrays, and methods of forming the same |
US20220181550A1 (en) * | 2019-03-04 | 2022-06-09 | International Business Machines Corporation | Stacked access device and resistive memory |
US20230042701A1 (en) * | 2021-08-09 | 2023-02-09 | Micron Technology, Inc. | On-die formation of single-crystal semiconductor structures |
US11711987B2 (en) | 2020-08-31 | 2023-07-25 | Micron Technology, Inc. | Memory electrodes and formation thereof |
US11849655B2 (en) | 2021-04-14 | 2023-12-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory devices with electrically isolated stacked bit lines and methods of manufacture |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150028280A1 (en) * | 2013-07-26 | 2015-01-29 | Micron Technology, Inc. | Memory cell with independently-sized elements |
WO2016161367A1 (en) | 2015-04-03 | 2016-10-06 | The Regents Of The University Of California | Polymeric materials for electrochemical cells and ion separation processes |
US9876169B2 (en) * | 2015-06-12 | 2018-01-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM devices and methods |
TWI603512B (en) * | 2015-07-03 | 2017-10-21 | 力晶科技股份有限公司 | Resistive random access memory structure |
CN109804496A (en) | 2016-09-28 | 2019-05-24 | 赛鹏科技有限公司 | Porous barrier provides the electrochemical cell of ion isolation |
US10276555B2 (en) * | 2016-10-01 | 2019-04-30 | Samsung Electronics Co., Ltd. | Method and system for providing a magnetic cell usable in spin transfer torque applications and including a switchable shunting layer |
JP7298845B2 (en) | 2016-12-07 | 2023-06-27 | セピオン テクノロジーズ,インコーポレイティド | Microstructured ion-conducting composites and uses thereof |
US10593399B2 (en) * | 2018-03-19 | 2020-03-17 | Micron Technology, Inc. | Self-selecting memory array with horizontal bit lines |
US10729012B2 (en) | 2018-04-24 | 2020-07-28 | Micron Technology, Inc. | Buried lines and related fabrication techniques |
US10825867B2 (en) | 2018-04-24 | 2020-11-03 | Micron Technology, Inc. | Cross-point memory array and related fabrication techniques |
US10950663B2 (en) | 2018-04-24 | 2021-03-16 | Micron Technology, Inc. | Cross-point memory array and related fabrication techniques |
US10622063B2 (en) * | 2018-06-27 | 2020-04-14 | Sandisk Technologies Llc | Phase change memory device with reduced read disturb and method of making the same |
US11011576B2 (en) | 2018-06-28 | 2021-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Resistive random access memory device |
KR102546686B1 (en) * | 2018-07-17 | 2023-06-23 | 삼성전자주식회사 | Variable resistance memory device |
KR102557911B1 (en) * | 2018-08-31 | 2023-07-19 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
KR102630031B1 (en) | 2018-10-05 | 2024-01-30 | 삼성전자주식회사 | Variable resistance memory device |
KR20200106681A (en) * | 2019-03-05 | 2020-09-15 | 에스케이하이닉스 주식회사 | Electronic device and method for fabricating the same |
KR20210124843A (en) | 2020-04-07 | 2021-10-15 | 삼성전자주식회사 | Memory devices |
US11482571B2 (en) * | 2020-06-23 | 2022-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory array with asymmetric bit-line architecture |
KR102675158B1 (en) | 2020-08-24 | 2024-06-12 | 삼성전자주식회사 | Semiconductor memory device and method for fabricating the same |
KR20220027595A (en) | 2020-08-27 | 2022-03-08 | 삼성전자주식회사 | Semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060157683A1 (en) * | 2005-01-19 | 2006-07-20 | Matrix Semiconductor, Inc. | Nonvolatile phase change memory cell having a reduced thermal contact area |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4376191B2 (en) * | 2003-04-03 | 2009-12-02 | ヒューレット−パッカード デベロップメント カンパニー エル.ピー. | 3D memory array |
US20050062087A1 (en) * | 2003-09-19 | 2005-03-24 | Yi-Chou Chen | Chalcogenide phase-change non-volatile memory, memory device and method for fabricating the same |
US7687830B2 (en) * | 2004-09-17 | 2010-03-30 | Ovonyx, Inc. | Phase change memory with ovonic threshold switch |
US7655938B2 (en) * | 2005-07-20 | 2010-02-02 | Kuo Charles C | Phase change memory with U-shaped chalcogenide cell |
US8188454B2 (en) * | 2005-10-28 | 2012-05-29 | Ovonyx, Inc. | Forming a phase change memory with an ovonic threshold switch |
EP1801896B1 (en) * | 2005-12-23 | 2010-05-19 | STMicroelectronics Srl | Process for manufacturing a selection device with reduced current leakage, and selection device, in particular for phase change memory devices |
JP2007214419A (en) * | 2006-02-10 | 2007-08-23 | Toshiba Corp | Semiconductor device |
KR101309111B1 (en) | 2006-07-27 | 2013-09-17 | 삼성전자주식회사 | Method for forming of poly-Si pattern and multi-layer cross point resistive memory device comprising poly-Si pattern and method for manufacturing the same |
US7442603B2 (en) * | 2006-08-16 | 2008-10-28 | Macronix International Co., Ltd. | Self-aligned structure and method for confining a melting point in a resistor random access memory |
KR100780964B1 (en) * | 2006-11-13 | 2007-12-03 | 삼성전자주식회사 | Phase change memory device having cell diode and method of fabricating the same |
KR100810617B1 (en) * | 2007-02-09 | 2008-03-06 | 삼성전자주식회사 | Multi bit pram and method of fabricating the same |
US7786461B2 (en) | 2007-04-03 | 2010-08-31 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
EP2003651A1 (en) | 2007-06-14 | 2008-12-17 | Samsung Electronics Co., Ltd. | Memory devices and methods of manufacturing the same |
KR101168977B1 (en) * | 2007-11-19 | 2012-07-26 | 삼성전자주식회사 | method of fabricating integrated circuit memory device having a growth- inhibiting layer on the interlayer insulating layer adjacent a contact hole |
WO2010019789A1 (en) * | 2008-08-13 | 2010-02-18 | Sandisk 3D, Llc | Methods and apparatus for increasing memory density using diode layer sharing |
US8063394B2 (en) | 2008-10-08 | 2011-11-22 | Qimonda Ag | Integrated circuit |
US8097870B2 (en) | 2008-11-05 | 2012-01-17 | Seagate Technology Llc | Memory cell with alignment structure |
TWI415316B (en) * | 2008-11-07 | 2013-11-11 | Macronix Int Co Ltd | Memory cell access device having a pn-junction with polycrystalline and single-crystal semiconductor regions |
US8148707B2 (en) * | 2008-12-30 | 2012-04-03 | Stmicroelectronics S.R.L. | Ovonic threshold switch film composition for TSLAGS material |
US20100165716A1 (en) * | 2008-12-30 | 2010-07-01 | Stmicroelectronics S.R.L. | Nonvolatile memory with ovonic threshold switches |
JP4881400B2 (en) * | 2009-03-23 | 2012-02-22 | 株式会社東芝 | Nonvolatile semiconductor memory device and screening method thereof |
JP2010225741A (en) * | 2009-03-23 | 2010-10-07 | Toshiba Corp | Nonvolatile semiconductor memory device |
KR101097436B1 (en) * | 2009-09-30 | 2011-12-23 | 주식회사 하이닉스반도체 | Phase Change Random Access Memory And Method of manufacturing The Same |
US8551855B2 (en) * | 2009-10-23 | 2013-10-08 | Sandisk 3D Llc | Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same |
JP5443965B2 (en) * | 2009-12-17 | 2014-03-19 | 株式会社東芝 | Semiconductor memory device |
US8278641B2 (en) * | 2009-12-23 | 2012-10-02 | Intel Corporation | Fabricating current-confining structures in phase change memory switch cells |
US8431492B2 (en) * | 2010-02-02 | 2013-04-30 | Sandisk 3D Llc | Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same |
JP2011222952A (en) * | 2010-03-24 | 2011-11-04 | Toshiba Corp | Resistance change memory |
KR101143485B1 (en) * | 2010-07-30 | 2012-05-10 | 에스케이하이닉스 주식회사 | Phase Change Random Access Memory And Fabricating The Same |
US8243506B2 (en) * | 2010-08-26 | 2012-08-14 | Micron Technology, Inc. | Phase change memory structures and methods |
US20120080725A1 (en) * | 2010-09-30 | 2012-04-05 | Seagate Technology Llc | Vertical transistor memory array |
CN102270739A (en) | 2011-05-10 | 2011-12-07 | 天津理工大学 | Resistive random access memory unit having snap switch device and making method of resistive random access memory unit |
KR20130043533A (en) * | 2011-10-20 | 2013-04-30 | 삼성전자주식회사 | Non-volatile memory device having conductive buffer pattern and method of forming the same |
US8710481B2 (en) * | 2012-01-23 | 2014-04-29 | Sandisk 3D Llc | Non-volatile memory cell containing a nano-rail electrode |
US20150028280A1 (en) * | 2013-07-26 | 2015-01-29 | Micron Technology, Inc. | Memory cell with independently-sized elements |
-
2013
- 2013-07-26 US US13/952,357 patent/US20150028280A1/en not_active Abandoned
-
2014
- 2014-07-24 CN CN201480050146.5A patent/CN105531820B/en active Active
- 2014-07-24 KR KR1020167004710A patent/KR101866108B1/en active IP Right Grant
- 2014-07-24 SG SG11201600610XA patent/SG11201600610XA/en unknown
- 2014-07-24 EP EP19187059.1A patent/EP3576149B1/en active Active
- 2014-07-24 WO PCT/US2014/047939 patent/WO2015013478A1/en active Application Filing
- 2014-07-24 CN CN201910660401.2A patent/CN110429176B/en active Active
- 2014-07-24 EP EP14828854.1A patent/EP3033769B1/en active Active
- 2014-07-25 TW TW103125594A patent/TWI571966B/en active
-
2015
- 2015-09-28 US US14/867,185 patent/US9640588B2/en active Active
-
2017
- 2017-04-05 US US15/479,403 patent/US10163978B2/en active Active
-
2018
- 2018-12-07 US US16/212,861 patent/US10573689B2/en active Active
-
2020
- 2020-01-07 US US16/736,252 patent/US10886332B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060157683A1 (en) * | 2005-01-19 | 2006-07-20 | Matrix Semiconductor, Inc. | Nonvolatile phase change memory cell having a reduced thermal contact area |
Cited By (81)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9525128B2 (en) * | 2013-05-22 | 2016-12-20 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
US20140349413A1 (en) * | 2013-05-22 | 2014-11-27 | Sungyoon CHUNG | Semiconductor devices and methods of manufacturing the same |
US10038136B2 (en) | 2013-05-22 | 2018-07-31 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
US10727336B2 (en) | 2014-04-24 | 2020-07-28 | Micron Technology, Inc. | Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors |
US9812639B2 (en) * | 2014-09-10 | 2017-11-07 | Toshiba Memory Corporation | Non-volatile memory device |
US20160072061A1 (en) * | 2014-09-10 | 2016-03-10 | Kabushiki Kaisha Toshiba | Non-volatile memory device |
US10784374B2 (en) | 2014-10-07 | 2020-09-22 | Micron Technology, Inc. | Recessed transistors containing ferroelectric material |
US11706929B2 (en) | 2015-02-17 | 2023-07-18 | Micron Technology, Inc. | Memory cells |
US10741567B2 (en) | 2015-02-17 | 2020-08-11 | Micron Technology, Inc. | Memory cells |
US11244951B2 (en) | 2015-02-17 | 2022-02-08 | Micron Technology, Inc. | Memory cells |
US10396127B2 (en) * | 2015-03-19 | 2019-08-27 | Micron Technology, Inc. | Constructions comprising stacked memory arrays |
US9881973B2 (en) | 2015-03-19 | 2018-01-30 | Micron Technology, Inc. | Constructions comprising stacked memory arrays |
US9691475B2 (en) * | 2015-03-19 | 2017-06-27 | Micron Technology, Inc. | Constructions comprising stacked memory arrays |
US10147764B2 (en) | 2015-03-19 | 2018-12-04 | Micron Technology, Inc. | Constructions comprising stacked memory arrays |
US20190006423A1 (en) * | 2015-03-19 | 2019-01-03 | Micron Technology, Inc. | Constructions Comprising Stacked Memory Arrays |
US10741755B2 (en) * | 2015-07-24 | 2020-08-11 | Micron Technology, Inc. | Array of cross point memory cells |
US20180331283A1 (en) * | 2015-07-24 | 2018-11-15 | Micron Technology, Inc. | Array Of Cross Point Memory Cells |
US11393978B2 (en) | 2015-07-24 | 2022-07-19 | Micron Technology, Inc. | Array of cross point memory cells |
US10811462B2 (en) | 2015-10-27 | 2020-10-20 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
US11587977B2 (en) | 2016-02-22 | 2023-02-21 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
US20170317139A1 (en) * | 2016-02-22 | 2017-11-02 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
US9780144B2 (en) | 2016-02-22 | 2017-10-03 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
US20190305044A1 (en) * | 2016-02-22 | 2019-10-03 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
US10374008B2 (en) * | 2016-02-22 | 2019-08-06 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
US11770938B2 (en) | 2016-02-22 | 2023-09-26 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
CN107104121A (en) * | 2016-02-22 | 2017-08-29 | 三星电子株式会社 | Memory device and the method for manufacturing memory device |
US10957740B2 (en) | 2016-02-22 | 2021-03-23 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
KR102473660B1 (en) * | 2016-02-22 | 2022-12-02 | 삼성전자주식회사 | Memory device and method of manufacturing the same |
KR20170098580A (en) * | 2016-02-22 | 2017-08-30 | 삼성전자주식회사 | Memory device and method of manufacturing the same |
US10141502B2 (en) | 2016-03-15 | 2018-11-27 | Samsung Electronics Co., Ltd. | Semiconductor memory devices |
US11227991B2 (en) | 2016-03-18 | 2022-01-18 | Samsung Electronics Co., Ltd. | Semiconductor devices |
US10680057B2 (en) | 2017-01-12 | 2020-06-09 | Micron Technology, Inc. | Methods of forming a capacitor comprising ferroelectric material and including current leakage paths having different total resistances |
US10553791B2 (en) * | 2017-03-01 | 2020-02-04 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
US20180254412A1 (en) * | 2017-03-01 | 2018-09-06 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
US10424374B2 (en) * | 2017-04-28 | 2019-09-24 | Micron Technology, Inc. | Programming enhancement in self-selecting memory |
JP2020519010A (en) * | 2017-04-28 | 2020-06-25 | マイクロン テクノロジー,インク. | Improved programming in self-selected memory |
TWI679639B (en) * | 2017-04-28 | 2019-12-11 | 美商美光科技公司 | Programming enhancement in self-selecting memory |
US11735261B2 (en) | 2017-04-28 | 2023-08-22 | Micron Technology, Inc. | Programming enhancement in self-selecting memory |
US11200950B2 (en) * | 2017-04-28 | 2021-12-14 | Micron Technology, Inc. | Programming enhancement in self-selecting memory |
US20180315475A1 (en) * | 2017-04-28 | 2018-11-01 | Micron Technology, Inc. | Programming enhancement in self-selecting memory |
EP3616202A4 (en) * | 2017-04-28 | 2020-12-30 | Micron Technology, INC. | Programming enhancement in self-selecting memory |
US11348871B2 (en) * | 2017-08-29 | 2022-05-31 | Micron Technology, Inc. | Integrated assemblies |
US10868248B2 (en) | 2018-02-09 | 2020-12-15 | Micron Technology, Inc. | Tapered memory cell profiles |
US10541364B2 (en) | 2018-02-09 | 2020-01-21 | Micron Technology, Inc. | Memory cells with asymmetrical electrode interfaces |
US10424730B2 (en) | 2018-02-09 | 2019-09-24 | Micron Technology, Inc. | Tapered memory cell profiles |
US11545625B2 (en) | 2018-02-09 | 2023-01-03 | Micron Technology, Inc. | Tapered memory cell profiles |
US10672981B2 (en) | 2018-02-09 | 2020-06-02 | Micron Technology, Inc. | Memory cells with asymmetrical electrode interfaces |
US10847719B2 (en) * | 2018-02-09 | 2020-11-24 | Micron Technology, Inc. | Tapered cell profile and fabrication |
US11133463B2 (en) | 2018-02-09 | 2021-09-28 | Micron Technology, Inc. | Memory cells with asymmetrical electrode interfaces |
US10693065B2 (en) | 2018-02-09 | 2020-06-23 | Micron Technology, Inc. | Tapered cell profile and fabrication |
US11404637B2 (en) | 2018-02-09 | 2022-08-02 | Micron Technology, Inc. | Tapered cell profile and fabrication |
US10854813B2 (en) | 2018-02-09 | 2020-12-01 | Micron Technology, Inc. | Dopant-modulated etching for memory devices |
US11800816B2 (en) * | 2018-02-09 | 2023-10-24 | Micron Technology, Inc. | Dopant-modulated etching for memory devices |
US20210043838A1 (en) * | 2018-02-09 | 2021-02-11 | Micron Technology, Inc. | Dopant-modulated etching for memory devices |
US11088323B2 (en) * | 2018-08-30 | 2021-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Top electrode last scheme for memory cell to prevent metal redeposit |
US11800818B2 (en) | 2018-08-30 | 2023-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Top electrode last scheme for memory cell to prevent metal redeposit |
CN110875353A (en) * | 2018-08-30 | 2020-03-10 | 台湾积体电路制造股份有限公司 | Memory device and forming method thereof |
US10686013B2 (en) | 2018-09-03 | 2020-06-16 | Samsung Electronics Co., Ltd. | Memory device |
US11367833B2 (en) * | 2018-09-28 | 2022-06-21 | Intel Corporation | Memory cells having increased structural stability |
US20190044061A1 (en) * | 2018-09-28 | 2019-02-07 | Intel Corporation | Memory cells having increased structural stability |
US10862031B2 (en) * | 2019-03-01 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to effectively suppress heat dissipation in PCRAM devices |
US11588106B2 (en) | 2019-03-01 | 2023-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to effectively suppress heat dissipation in PCRAM devices |
US20220181550A1 (en) * | 2019-03-04 | 2022-06-09 | International Business Machines Corporation | Stacked access device and resistive memory |
US11170834B2 (en) | 2019-07-10 | 2021-11-09 | Micron Technology, Inc. | Memory cells and methods of forming a capacitor including current leakage paths having different total resistances |
US11276731B2 (en) * | 2019-08-07 | 2022-03-15 | Micron Technology, Inc. | Access line formation for a memory array |
CN112349746A (en) * | 2019-08-07 | 2021-02-09 | 美光科技公司 | Access line formation for memory arrays |
US20210043685A1 (en) * | 2019-08-07 | 2021-02-11 | Micron Technology, Inc. | Access line formation for a memory array |
US20210057645A1 (en) * | 2019-08-23 | 2021-02-25 | Globalfoundries Singapore Pte. Ltd. | Memory device and method of forming the same |
US11133465B2 (en) * | 2019-10-14 | 2021-09-28 | Yangtze Memory Technologies Co., Ltd. | Methods for forming three-dimensional phase-change memory devices |
US11195999B2 (en) * | 2019-11-13 | 2021-12-07 | International Business Machines Corporation | Phase change material with reduced reset state resistance drift |
US11309490B2 (en) * | 2020-02-10 | 2022-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory devices and methods of forming the same |
US11744165B2 (en) * | 2020-02-10 | 2023-08-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory devices and methods of forming the same |
US20220246844A1 (en) * | 2020-02-10 | 2022-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory devices and methods of forming the same |
US11616098B2 (en) | 2020-05-08 | 2023-03-28 | Micron Technology, Inc. | Three-dimensional memory arrays, and methods of forming the same |
US11355554B2 (en) * | 2020-05-08 | 2022-06-07 | Micron Technology, Inc. | Sense lines in three-dimensional memory arrays, and methods of forming the same |
US20210384427A1 (en) * | 2020-06-09 | 2021-12-09 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices |
US11950517B2 (en) * | 2020-06-09 | 2024-04-02 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices |
US11711987B2 (en) | 2020-08-31 | 2023-07-25 | Micron Technology, Inc. | Memory electrodes and formation thereof |
US11849655B2 (en) | 2021-04-14 | 2023-12-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory devices with electrically isolated stacked bit lines and methods of manufacture |
US11683937B2 (en) * | 2021-08-09 | 2023-06-20 | Micron Technology, Inc. | On-die formation of single-crystal semiconductor structures |
US20230042701A1 (en) * | 2021-08-09 | 2023-02-09 | Micron Technology, Inc. | On-die formation of single-crystal semiconductor structures |
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CN110429176B (en) | 2023-04-18 |
EP3033769B1 (en) | 2019-10-16 |
US10163978B2 (en) | 2018-12-25 |
WO2015013478A1 (en) | 2015-01-29 |
EP3033769A4 (en) | 2017-06-21 |
TW201517214A (en) | 2015-05-01 |
TWI571966B (en) | 2017-02-21 |
US20170207273A1 (en) | 2017-07-20 |
CN110429176A (en) | 2019-11-08 |
US10573689B2 (en) | 2020-02-25 |
EP3576149A1 (en) | 2019-12-04 |
US20190109176A1 (en) | 2019-04-11 |
US20160020256A1 (en) | 2016-01-21 |
CN105531820A (en) | 2016-04-27 |
EP3576149B1 (en) | 2021-03-24 |
US9640588B2 (en) | 2017-05-02 |
CN105531820B (en) | 2019-08-16 |
US10886332B2 (en) | 2021-01-05 |
KR20160039228A (en) | 2016-04-08 |
SG11201600610XA (en) | 2016-02-26 |
EP3033769A1 (en) | 2016-06-22 |
KR101866108B1 (en) | 2018-06-08 |
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