WO2008126961A1 - Mfmis-fet, mfmis-ferroelectric memory device, and methods of manufacturing the same - Google Patents

Mfmis-fet, mfmis-ferroelectric memory device, and methods of manufacturing the same Download PDF

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Publication number
WO2008126961A1
WO2008126961A1 PCT/KR2007/002887 KR2007002887W WO2008126961A1 WO 2008126961 A1 WO2008126961 A1 WO 2008126961A1 KR 2007002887 W KR2007002887 W KR 2007002887W WO 2008126961 A1 WO2008126961 A1 WO 2008126961A1
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Prior art keywords
ferroelectric
layer
electrode layer
mfmis
memory device
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PCT/KR2007/002887
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French (fr)
Inventor
Byung-Eun Park
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University Of Seoul Foundation Of Industry-Academic Cooperation
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Priority claimed from KR1020070058184A external-priority patent/KR100876136B1/en
Publication of WO2008126961A1 publication Critical patent/WO2008126961A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Definitions

  • the present invention relates to a metal- ferroelectric-metal-insulator-semiconductor (MFMIS) type field-effect transistor (FET) and an MFMIS type ferroelectric memory device with a simple structure and having excellent data retention characteristics, and methods of manufacturing the same.
  • MFMIS metal- ferroelectric-metal-insulator-semiconductor
  • FET field-effect transistor
  • FIG. 1 is a cross-sectional view showin ⁇ j a typical structure of a metal-ferroelectric- semiconductor (MFS) type memory device using a ferroelectric material.
  • MFS metal-ferroelectric- semiconductor
  • source and drain regions 2 and 3 are formed in predetermined areas of a silicon substrate 1, and a ferroelectric layer 5 is formed on a channel region 4 between the source and drain regions 2 and 3.
  • the ferroelectric layer 5 comprises an inorganic material having ferroelectric properties such as PbZr x Tii_ x ⁇ 3 (PZT) , SrBi 2 Ta 2 O 9 (SBT), (Bi, La) 4Ti 3 Oi 2 (BLT), and the like.
  • a source electrode 6, a drain electrode 7 and a gate electrode 8 formed of a metal material, respectively, are arranged on the top of the source and drain regions 2 and 3 and the ferroelectric layer 5.
  • the ferroelectric layer 5 has polarization characteristics according to a voltage applied through the gate electrode 8, and a conductive channel is formed between the source region 2 and the drain region 3 by the polarization characteristics. As a result, a current flows between the source electrode 6 and the drain electrode 7. Especially, in the above-described structure, even in the case where the voltage applied through the gate electrode 8 is cut off, the polarization characteristics of the ferroelectric layer 5 are continuously maintained. Accordingly, the above-described structure has attracted much attention since it can form a non-volatile memory only with one transistor (IT) even though a capacitor is not provided.
  • IT transistor
  • the ferroelectric memory having the above- described structure has the following problems. That is, when the ferroelectric layer 5 is directly formed on the silicon substrate 1, a transition layer of low quality is formed on the boundary between the ferroelectric layer 5 and the silicon substrate 1 during the formation of the ferroelectric layer 5, and chemical elements such as Pb and Bi in the ferroelectric layer 5 are diffused into the silicon substrate 1, thus making it difficult to form a ferroelectric layer 5 of high quality. As a result, there occurs a problem that the polarization characteristics of the ferroelectric layer 5 are deteriorated, that is, the data retention time of the ferroelectric memory becomes very short.
  • MFIS metal- ferroelectric-insulator-semiconductor
  • the above MFIS type ferroelectric memory has some problems in that it requires an additional process of forming the buffer layer 20, the data retention effect is not greiat, and the data retention time cannot exceed 30 days even in case of an excellent product manufactured in a laboratory.
  • FIG. 3 is a cross-sectional view showing a typical structure of the MFMIS type ferroelectric memory device, in which substantially the same elements as those of FIG. 2 have the same reference numerals.
  • the MFMIS type ferroelectric memory device has a structure in which a source region 2, a drain region 3 and a channel region 4 are formed on a silicon substrate 1, and an insulating layer 31 as a gate oxide layer, for example, a floating gate 32, a ferroelectric layer 33 and a control gate 34 are sequentially stacked on the channel region 4.
  • the MFMIS type ferroelectric memory device has a characteristic feature in that the effect area of the ferroelectric layer 33 is changed using the floating gate 32 so as to saturate the polarization of the ferroelectric layer 33 at a relative low voltage.
  • the conventional MFMIS type ferroelectric memory device has some drawbacks in that, when an electric charge is injected into the floating gate 32 through the ferroelectric layer 33 or the insulating layer 31, the injected charge affects the entire floating gate 32, and thus the memory characteristics may be degraded by leakage current .
  • the present invention has been made in an effort to solve the above-described problems.
  • the present invention provides an MFMIS type ferroelectric memory device with a simple structure and having excellent data retention characteristics, and a method of manufacturing the same.
  • the present invention provides an MFMIS type FET and a method of manufacturing the same.
  • a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate; a transistor formed on the substrate; and a ferroelectric capacitor formed on the transistor, wherein the ferroelectric capacitor comprises a lower electrode layer, an upper electrode layer, and a ferroelectric layer formed between the lower and upper electrode layers, in which the lower electrode layer is a data electrode and the upper electrode layer is a ground electrode.
  • MFMIS metal-ferroelectric-metal- insulator-semiconductor
  • a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate; a transistor formed on the substrcite; and a ferroelectric capacitor formed on the transistor, wherein the ferroelectric capacitor comprises a lower electrode layer, an upper electrode layer, and a ferroelectric layer formed between the lower and upper electrode layers, in which the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode.
  • MFMIS metal-ferroelectric-metal- insulator-semiconductor
  • the transistor may comprise: drain and source regions formed on the substrate; a channel region formed between the drain and source regions; and an insulating layer formed on the channel region.
  • a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a data electrode and the upper electrode layer is a ground electrode.
  • MFMIS metal-ferroelectric-metal- insulator-semiconductor
  • a metal -ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode.
  • MFMIS metal -ferroelectric-metal- insulator-semiconductor
  • a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type field-effect transistor (FET) comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a data electrode and the upper electrode layer is a ground electrode.
  • MFMIS metal-ferroelectric-metal- insulator-semiconductor
  • a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type field-effect transistor (FET) comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode.
  • MFMIS metal-ferroelectric-metal- insulator-semiconductor
  • a method of manufacturing a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a data electrode layer on the channel region; forming a ferroelectric layer on the data electrode layer; and forming a ground electrode layer on the ferroelectric layer.
  • MFMIS metal-ferroelectric-metal-insulator-semiconductor
  • a method of manufacturing a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a ground electrode layer on the channel region; forming a ferroelectric layer on the ground electrode layer; and forming a data electrode layer on the ferroelectric layer.
  • MFMIS metal-ferroelectric-metal-insulator-semiconductor
  • MFMIS metal-ferroelectric-metal-insulator-semiconductor
  • the substrate may comprise paper or an organic material .
  • the ferroelectric layer may comprise an inorganic ferroelectric material.
  • the ferroelectric layer may comprise an organic ferroelectric material .
  • the ferroelectric layer may comprise a mixture of an inorganic ferroelectric material and an organic material.
  • the ferroelectric layer may comprise a mixture of an inorganic ferroelectric material and an organic ferroelectric material.
  • the ferroelectric layer may comprise a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
  • the ferroelectric layer may comprise a mixture of a solid solution of an inorganic ferroelectric material and an organic ferroelectric material.
  • the ferroelectric layer may further comprise a suicide, a silicate or any other metal.
  • the lower electrode layer and the upper electrode layer may comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag), aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiOa) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
  • conductive metals including gold (Au) , silver (Ag), aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiOa)
  • conductive metal oxides conductive metal alloys
  • conductive metal compounds and, further,
  • the lower electrode layer and the upper electrode layer may be arranged to extend in a direction to cross each other.
  • FIG. 1 is a cross-sectional view showing a conventional metal-ferroelectric-semiconductor (MFS) type ferroelectric memory device
  • FIG. 2 is a cross-sectional view showing a conventional metal-ferroelectric-insulator-semiconductor (MFIS) type ferroelectric memory device
  • FIG. 3 is a cross-sectional view showing a conventional metal-ferroelectric-metal-semiconductor (MFMIS) type ferroelectric memory device
  • MFIS metal-ferroelectric-insulator-semiconductor
  • MFMIS metal-ferroelectric-metal-semiconductor
  • FIG. 4 is a cross-sectional view showing a metal- ferroelectric-metal-semiconductor (MFMIS) type ferroelectric memory device or an MFMIS type field-effect transistor (FET) in accordance with a preferred embodiment of the present invention.
  • MFMIS metal- ferroelectric-metal-semiconductor
  • a polarization voltage is set in a ferroelectric layer 33 by applying a predetermined voltage through a control gate 34. Accordingly, in the conventional structure, it is necessary to consider the capacitance values, i.e., the dielectric constant, the thicknesses and the areas of the ferroelectric layer 33 and an insulating layer 31. For this reason, a floating gate 32 is required and thus the memory characteristics may be degraded by leakage current due to the floating gate 32. In the present invention, the above problem is solved by selectively polarizing the ferroelectric layer 33 only.
  • FIG. 4 is a cross-sectional view showing an MFMIS type ferroelectric memory device or an MFMIS type field-effect transistor (FET) in accordance with a preferred embodiment of the present invention, in which substantially the same elements as those of FIG. 3 have the same reference numerals and th € ⁇ ir detailed description will be omitted.
  • FET field-effect transistor
  • source and drain regions 2 and 3 are formed in predetermined areas of a silicon substrate 1, and a ferroelectric capacitor is formed via an insulating layer 41 on a channel region 4 between the source and drain regions 2 and 3.
  • the ferroelectric capacitor includes a ferroelectric layer 43 provided between a lower electrode 42 and an upper electrode 44.
  • the lower electrode 42 is set as a data electrode, for example, and the upper electrode 44 is set as a ground electrode.
  • the lower electrode 42 and the upper electrode 44 are provided to form a polarization voltage in the ferroelectric layer 43. That is, the ferroelectric layer 43 is polarized in such a manner that a predetermined data voltage is applied to the lower electrode 42 and the upper electrode 44 is grounded.
  • the present invention has a structure in which the ferroelectric capacitor including the ferroelectric layer 43 is formed on a transistor (MIS) including the source region 2, the drain region 3, the channel region 4, and the insulating layer 41 formed on the channel region 4.
  • MIS transistor
  • the ferroelectric layer 43 is polarized using the lower electrode 42 and the upper electrode 44 in order to write data.
  • the lower transistor is set to either an ON or OFF state by the polarization value. Accordingly, the written data "0" or "1" can be read based on the ON/OFF state of the transistor.
  • the above structure functions as an excellent non-volatile memory. Accordingly, the present invention provides a nonvolatile memory device having a IT (one-transistor) structure.
  • source and drain regions 2 and 3 and a channel region 4 are formed on a substrate 1 by an ordinary method, and an insulating layer 41 is formed as a gate insulating layer on the top of the channel region 4.
  • the insulating layer 41 may be formed of any insulating material well known in the art such as a silicon dioxide (SiO 2 ) , for example .
  • the substrate 1 may be formed of general silicon or compound semiconductor.
  • the substrate 1 may be formed of paper, paper coated with parylene, or an organic material such as flexible plastic.
  • the available organic materials may include polyimide (PI) , polycarbonate (PC), polyethersulfone (PES), polyetheretherketone (PEEK), polybutyleneterephthalate (PBT) , polyethyleneterephthalate (PET) , polyvinylchloride (PVC) , polyethylene (PE) , ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4- methyl-1-pentene) (TPX) , polyarylate (PAR), polyacetal (POM), polyphenyleneoxide (PPO) , polysulfone (PSF) , polyphenylenesulfide (PPS) , polyvinylidenechloride (PVDC) , polyvinylacetate (PVAC) , polyvinylalcohol (P
  • the lower electrode 42 may be formed of at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiOa) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
  • conductive metals including gold (Au) , silver (Ag) , aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiOa)
  • conductive metal oxides conductive metal alloys
  • conductive metal compounds and, further,
  • a ferroelectric layer 43 is formed on the lower electrode 42 and an upper electrode 44 is formed on the ferroelectric layer 43 in a direction to cross the lower electrode 42.
  • the upper electrode 44 may be formed of at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt) , indium tin oxide (ITO), and strontiumtitanate (SrTiO 3 ), conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3, 4-ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
  • conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt) , indium
  • the ferroelectric layer 43 may be formed of a mixture of an inorganic ferroelectric material and an organic ferroelectric material or a mixture of an inorganic ferroelectric material or a solid solution thereof and an organic material or an organic ferroelectric material .
  • various materials showing ferroelectric characteristics are broadly classified into inorganic materials and organic materials.
  • the inorganic ferroelectric materials include ferroelectric oxides, ferroelectric fluorides such as BaMgF 4 (BMF) , and ferroelectric semiconductors.
  • the organic ferroelectric materials include polymer ferroelectric materials and the like.
  • the ferroelectric oxides include perovskite ferroelectric materials such as PbZr x Tii- x O 3 (PZT) , BaTiO 3 and PBTiO 3 , pseudo-ilmenite ferroelectric materials such as LiNbO 3 and LiTaO 3 , tungsten-bronze (TB) ferroelectric materials such as PbNb 3 Oe and Ba 2 NaNb 5 Oi 5 , ferroelectric materials having a bismuth layer structure such as SrBi 2 Ta 2 Og (SBT), (Bi,La) 4 Ti 3 Oi2 (BLT) and Bi 4 Ti 3 Oi 2 , pyrochlore ferroelectric materials such as La ?
  • ferroelectric materials such as RMnO 3 , Pb 5 Ge 3 On (PGO) and BiFeO 3 (BFO) including a rare earth element (R) such as Y, Er, Ho, Tm, Yb and Lu.
  • ferroelectric semiconductors include 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe.
  • polymer ferroelectric materials include polyvinylidene fluoride (PVDF), PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano-polymer, and polymer or copolymer thereof.
  • PVDF polyvinylidene fluoride
  • the inorganic ferroelectric materials including the ferroelectric oxides, the ferroelectric fluorides and the ferroelectric semiconductors have dielectric constants greater than those of the organic ferroelectric materials.
  • the generally proposed ferroelectric field-effect transistor (FET) or ferroelectric memory device employs the inorganic ferroelectric materials for forming the ferroelectric layer.
  • the inorganic ferroelectric materials are formed at higher temperatures, while their dielectric constants are high.
  • the organic materials including the organic ferroelectric materials are formed at lower temperatures, while their dielectric constants are relatively low.
  • the inorganic ferroelectric material and the organic material may be mixed with each other as follows: 1. Mixing an inorganic ferroelectric material with an organic material;
  • the above mixing methods are not limited to specific methods and any method that can appropriately mix the inorganic material with the organic material may be employed.
  • the organic materials mixed with the inorganic ferroelectric material include, a monomer, an oligomer, a polymer, and a copolymer.
  • an organic material having a high dielectric constant may be used.
  • the organic materials having a high dielectric constant include polyvinylpyrrolidone (PVP) , polycarbonate (PC) , polyvinyl chloride (PVC) , polystyrene (PS) , epoxy, polymethylmethacrylate (PMMA) , polyimide (PI) , polyethylene (PE) , polyvinyl alcohol (PVA) , polyhexamethylene adipamide (nylon 66), polyetherketoneketone (PEKK), and the like.
  • PVP polyvinylpyrrolidone
  • PC polycarbonate
  • PVC polyvinyl chloride
  • PS polystyrene
  • epoxy epoxy
  • PMMA polymethylmethacrylate
  • PI polyimide
  • PE polyethylene
  • PVA polyvinyl alcohol
  • PEKK polyhexamethylene adipamide
  • PEKK polyetherketoneketone
  • the organic materials include a nonpolar organic material, such as fluorinated para-xylene, fluoropolyarylether, fluorinated polyimide, polystyrene, poly ( ⁇ -methyl styrene) , poly ( ⁇ -vinylnaphthalene) , poly (vinyltoluene) , polyethylene, cis-polybutadiene, polypropylene, polyisoprene, poly (4-methyl-l-pentene) , poly (tetrafluoroethylene) , poly (chlorotrifluoroethylene) , poly (2-methyl-l, 3-butadiene) , poly (p-xylylene) , poly ( ⁇ - ⁇ - ⁇ ' - ⁇ ' -tetrafluoro-p-xylylene) , poly [1, 1- (2-methyl propane) bis (4-phenyl) carbonate] , poly (cyclohexyl methacrylate) , poly (chlorosty, poly
  • organic semi-conducting materials that can be used in this invention include soluble compounds and soluble derivatives of compounds of the following list: conjugated hydrocarbon polymers such as polyacene, polyphenylene, poly (phenylene vinylene) , polyfluorene including oligomers of those conjugated hydrocarbon polymers; condensed aromatic hydrocarbons such as anthracene, tetracene, chrysene, pentacene, pyrene, perylene, coronene; oligomeric para substituted phenylenes such as p-quaterphenyl (p-4P) , p- quinquephenyl (p-5P) , p-sexiphenyl (p-6P) ; conjugated heterocyclic polymers such as poly (3-substituted thiophene) , poly (3, 4-bisubstituted thiophene), polybenzothiophene, polyisothianapthene, poly (N-substit
  • Ib is possible to appropriately set the mixture ratio of the inorganic material and the organic material. If the mixture ratio of the inorganic ferroelectric material is increased, the formation temperature is increased while the dielectric constant of the mixture is increased, whereas if the mixture ratio of the inorganic ferroelectric material is decreased, the formation temperature is lowered while the dielectric constant of the mixture is reduced.
  • the present invention adopts a structure that selectively polarizes the ferroelectric layer 43 only, the available ferroelectric materials are not limited.
  • the present invention has the structure in which the ferroelectric capacitor is formed on the transistor, in which the data write operation is made independently with respect to the ferroelectric capacitor.
  • the preset invention provides the following technical effects: 1. Since a depolarization fieLd of the insulating layer with respect to a polarization field of the ferroelectric layer is removed in the present invention, excellent data retention characteristics are provided;
  • the present invention does not require specific materials as the ferroelectric material and the insulating material of the insulating layer 41, and thus the degree of design freedom is significantly increased;
  • the transistor can be turned ON/OFF by polarizing the ferroelectric layer 43, the structure in accordance with the present invention can be used as the field-effect transistor.
  • an MFMIS type ferroelectric memory device with a simple structure and having excellent data retention characteristics, and a method of manufacturing the same .

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Abstract

Disclosed herein are a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) field-effect transistor (FET), an MFMIS-ferroelectric memory device, and methods of manufacturing the same. The FET and the ferroelectric memory device in accordance with the present invention include: a substrate 1; a transistor formed on the substrate 1; and a ferroelectric capacitor formed on the transistor, the ferroelectric capacitor including a lower electrode layer 42, an upper electrode layer 44, and a ferroelectric layer 43 disposed between the lower and upper electrodes.

Description

[DESCRIPTION]
[invention Title]
MFMIS-FET , MFMIS-FERROELECTRIC MEMORY DEVICE , AND METHODS OF
MANUFACTURING THE SAME
[Technical Field]
The present invention relates to a metal- ferroelectric-metal-insulator-semiconductor (MFMIS) type field-effect transistor (FET) and an MFMIS type ferroelectric memory device with a simple structure and having excellent data retention characteristics, and methods of manufacturing the same.
[Background Art] At present, extensive research aimed at realizing a transistor or a memory device using a ferroelectric material has continued to progress. FIG. 1 is a cross-sectional view showinςj a typical structure of a metal-ferroelectric- semiconductor (MFS) type memory device using a ferroelectric material.
As shown in FIG. 1, source and drain regions 2 and 3 are formed in predetermined areas of a silicon substrate 1, and a ferroelectric layer 5 is formed on a channel region 4 between the source and drain regions 2 and 3. In this case, the ferroelectric layer 5 comprises an inorganic material having ferroelectric properties such as PbZrxTii_xθ3 (PZT) , SrBi2Ta2O9 (SBT), (Bi, La) 4Ti3Oi2 (BLT), and the like. Moreover, a source electrode 6, a drain electrode 7 and a gate electrode 8 formed of a metal material, respectively, are arranged on the top of the source and drain regions 2 and 3 and the ferroelectric layer 5.
In the ferroelectric memory device having the above- described structure, the ferroelectric layer 5 has polarization characteristics according to a voltage applied through the gate electrode 8, and a conductive channel is formed between the source region 2 and the drain region 3 by the polarization characteristics. As a result, a current flows between the source electrode 6 and the drain electrode 7. Especially, in the above-described structure, even in the case where the voltage applied through the gate electrode 8 is cut off, the polarization characteristics of the ferroelectric layer 5 are continuously maintained. Accordingly, the above-described structure has attracted much attention since it can form a non-volatile memory only with one transistor (IT) even though a capacitor is not provided.
However, the ferroelectric memory having the above- described structure has the following problems. That is, when the ferroelectric layer 5 is directly formed on the silicon substrate 1, a transition layer of low quality is formed on the boundary between the ferroelectric layer 5 and the silicon substrate 1 during the formation of the ferroelectric layer 5, and chemical elements such as Pb and Bi in the ferroelectric layer 5 are diffused into the silicon substrate 1, thus making it difficult to form a ferroelectric layer 5 of high quality. As a result, there occurs a problem that the polarization characteristics of the ferroelectric layer 5 are deteriorated, that is, the data retention time of the ferroelectric memory becomes very short.
In consideration of the above problems, as shown in FIG. 2, there has been recently proposed a so-called metal- ferroelectric-insulator-semiconductor (MFIS) structure, in which a buffer layer 20 formed mainly of an oxide is provided between the silicon substrate 1 and the ferroelectric layer 5.
However, the above MFIS type ferroelectric memory has some problems in that it requires an additional process of forming the buffer layer 20, the data retention effect is not greiat, and the data retention time cannot exceed 30 days even in case of an excellent product manufactured in a laboratory.
Moreover, there has been proposed a metal- ferroelectric-metal-insulator-semiconductor (MFMIS) structure as the ferroelectric memory device. FIG. 3 is a cross-sectional view showing a typical structure of the MFMIS type ferroelectric memory device, in which substantially the same elements as those of FIG. 2 have the same reference numerals. The MFMIS type ferroelectric memory device has a structure in which a source region 2, a drain region 3 and a channel region 4 are formed on a silicon substrate 1, and an insulating layer 31 as a gate oxide layer, for example, a floating gate 32, a ferroelectric layer 33 and a control gate 34 are sequentially stacked on the channel region 4.
The MFMIS type ferroelectric memory device has a characteristic feature in that the effect area of the ferroelectric layer 33 is changed using the floating gate 32 so as to saturate the polarization of the ferroelectric layer 33 at a relative low voltage.
However, the conventional MFMIS type ferroelectric memory device has some drawbacks in that, when an electric charge is injected into the floating gate 32 through the ferroelectric layer 33 or the insulating layer 31, the injected charge affects the entire floating gate 32, and thus the memory characteristics may be degraded by leakage current .
[Disclosure] [Technical Problem] Accordingly, the present invention has been made in an effort to solve the above-described problems. The present invention provides an MFMIS type ferroelectric memory device with a simple structure and having excellent data retention characteristics, and a method of manufacturing the same.
Moreover, the present invention provides an MFMIS type FET and a method of manufacturing the same.
[Technical Solution] In accordance with a first aspect of the present invention, there is provided a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate; a transistor formed on the substrate; and a ferroelectric capacitor formed on the transistor, wherein the ferroelectric capacitor comprises a lower electrode layer, an upper electrode layer, and a ferroelectric layer formed between the lower and upper electrode layers, in which the lower electrode layer is a data electrode and the upper electrode layer is a ground electrode.
In accordance with a second aspect of the present invention, there is provided a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate; a transistor formed on the substrcite; and a ferroelectric capacitor formed on the transistor, wherein the ferroelectric capacitor comprises a lower electrode layer, an upper electrode layer, and a ferroelectric layer formed between the lower and upper electrode layers, in which the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode.
The transistor may comprise: drain and source regions formed on the substrate; a channel region formed between the drain and source regions; and an insulating layer formed on the channel region.
In accordance with a third aspect of the present invention, there is provided a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a data electrode and the upper electrode layer is a ground electrode.
In accordance with a fourth aspect of the present invention, there is provided a metal -ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode. In accordance with a fifth aspect of the present invention, there is provided a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type field-effect transistor (FET) comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a data electrode and the upper electrode layer is a ground electrode.
In accordance with a sixth aspect of the present invention, there is provided a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type field-effect transistor (FET) comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode.
In accordance with a seventh aspect of the present invention, there is provided a method of manufacturing a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type ferroelectric memory device, the method comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a data electrode layer on the channel region; forming a ferroelectric layer on the data electrode layer; and forming a ground electrode layer on the ferroelectric layer.
In accordance with an eighth aspect of the present invention, there is provided a method of manufacturing a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type ferroelectric memory device, the method comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a ground electrode layer on the channel region; forming a ferroelectric layer on the ground electrode layer; and forming a data electrode layer on the ferroelectric layer.
In accordance with a ninth aspect of the present invention, there is provided a method of manufacturing a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type field-effect transistor (FET), the method comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a data electrode layer on the channel region; forming a ferroelectric layer on the data electrode layer; and forming a ground electrode layer on the ferroelectric layer.
In accordance with a tenth aspect of the present invention, there is provided a method of manufacturing a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type field-effect transistor (FET), the method comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a ground electrode layer on the channel region; forming a ferroelectric layer on the ground electrode layer; and forming a data electrode layer on the ferroelectric layer. The substrate may comprise paper or an organic material . The ferroelectric layer may comprise an inorganic ferroelectric material.
The ferroelectric layer may comprise an organic ferroelectric material . The ferroelectric layer may comprise a mixture of an inorganic ferroelectric material and an organic material.
The ferroelectric layer may comprise a mixture of an inorganic ferroelectric material and an organic ferroelectric material. The ferroelectric layer may comprise a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
The ferroelectric layer may comprise a mixture of a solid solution of an inorganic ferroelectric material and an organic ferroelectric material.
The ferroelectric layer may further comprise a suicide, a silicate or any other metal.
The lower electrode layer and the upper electrode layer may comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag), aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiOa) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
The lower electrode layer and the upper electrode layer may be arranged to extend in a direction to cross each other.
[Description of Drawings]
FIG. 1 is a cross-sectional view showing a conventional metal-ferroelectric-semiconductor (MFS) type ferroelectric memory device;
FIG. 2 is a cross-sectional view showing a conventional metal-ferroelectric-insulator-semiconductor (MFIS) type ferroelectric memory device; FIG. 3 is a cross-sectional view showing a conventional metal-ferroelectric-metal-semiconductor (MFMIS) type ferroelectric memory device; and
FIG. 4 is a cross-sectional view showing a metal- ferroelectric-metal-semiconductor (MFMIS) type ferroelectric memory device or an MFMIS type field-effect transistor (FET) in accordance with a preferred embodiment of the present invention.
[Mode for Invention] Hereinafter, preferred embodiments in accordance with the present invention will be described with reference to the accompanying drawings. The preferred embodiments are provided so that those skilled in the art can sufficiently understand the present invention, but can be modified in various forms and the scope of the present invention is not limited to the preferred embodiments.
First, the basic concept of the present invention will be described below.
In a conventional metal-ferroelectric-metal- semiconductor (MFMIS) structure as shown in FIG. 3, a polarization voltage is set in a ferroelectric layer 33 by applying a predetermined voltage through a control gate 34. Accordingly, in the conventional structure, it is necessary to consider the capacitance values, i.e., the dielectric constant, the thicknesses and the areas of the ferroelectric layer 33 and an insulating layer 31. For this reason, a floating gate 32 is required and thus the memory characteristics may be degraded by leakage current due to the floating gate 32. In the present invention, the above problem is solved by selectively polarizing the ferroelectric layer 33 only.
FIG. 4 is a cross-sectional view showing an MFMIS type ferroelectric memory device or an MFMIS type field-effect transistor (FET) in accordance with a preferred embodiment of the present invention, in which substantially the same elements as those of FIG. 3 have the same reference numerals and th€ϊir detailed description will be omitted.
In FIG. 4, source and drain regions 2 and 3 are formed in predetermined areas of a silicon substrate 1, and a ferroelectric capacitor is formed via an insulating layer 41 on a channel region 4 between the source and drain regions 2 and 3. The ferroelectric capacitor includes a ferroelectric layer 43 provided between a lower electrode 42 and an upper electrode 44. Here, the lower electrode 42 is set as a data electrode, for example, and the upper electrode 44 is set as a ground electrode. Moreover, it is possible to set the lower electrode 42 as the ground electrode and the upper electrode 44 as the data electrode. The lower electrode 42 and the upper electrode 44 are provided to form a polarization voltage in the ferroelectric layer 43. That is, the ferroelectric layer 43 is polarized in such a manner that a predetermined data voltage is applied to the lower electrode 42 and the upper electrode 44 is grounded.
Like this, it is unnecessary to consider the capacitance values of the ferroelectric layer 43 and the insulating layer 41. In the conventional structure as shown in FIG. 3, a plan for properly adjusting the area ratio of the insulating layer 31 and the ferroelectric layer 33 is considered in order to saturate the polarization of the ferroelectric layer 33, and a necessity for the adjustment operation has been a serious obstacle to the practical use of the ferroelectric memory having the MFMIS structure. The present invention has a structure in which the ferroelectric capacitor including the ferroelectric layer 43 is formed on a transistor (MIS) including the source region 2, the drain region 3, the channel region 4, and the insulating layer 41 formed on the channel region 4. In the structure of the present invention, the ferroelectric layer 43 is polarized using the lower electrode 42 and the upper electrode 44 in order to write data. When the ferroelectric layer 43 is polarized, the lower transistor is set to either an ON or OFF state by the polarization value. Accordingly, the written data "0" or "1" can be read based on the ON/OFF state of the transistor. Moreover, since the polarization state of the ferroelectric layer 43 is maintained continuously, the above structure functions as an excellent non-volatile memory. Accordingly, the present invention provides a nonvolatile memory device having a IT (one-transistor) structure.
Next, a method of manufacturing the MFMIS type ferroelectric memory device or the MFMIS type field-effect transistor (FET) with the above-described structure in accordance with the present invention will be described.
First, source and drain regions 2 and 3 and a channel region 4 are formed on a substrate 1 by an ordinary method, and an insulating layer 41 is formed as a gate insulating layer on the top of the channel region 4. Here, the insulating layer 41 may be formed of any insulating material well known in the art such as a silicon dioxide (SiO2) , for example .
Moreover, the substrate 1 may be formed of general silicon or compound semiconductor. The substrate 1 may be formed of paper, paper coated with parylene, or an organic material such as flexible plastic. Here, the available organic materials may include polyimide (PI) , polycarbonate (PC), polyethersulfone (PES), polyetheretherketone (PEEK), polybutyleneterephthalate (PBT) , polyethyleneterephthalate (PET) , polyvinylchloride (PVC) , polyethylene (PE) , ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4- methyl-1-pentene) (TPX) , polyarylate (PAR), polyacetal (POM), polyphenyleneoxide (PPO) , polysulfone (PSF) , polyphenylenesulfide (PPS) , polyvinylidenechloride (PVDC) , polyvinylacetate (PVAC) , polyvinylalcohol (PVA) , polyvinylacetal (PVAL), polystyrene (PS), AS resin, ABS resin, polymethylmethacrylate (PMMA) , fluorocarbon resin, phenol-formaldehyde (PF) resin, melamine-formaldehyde (MF) resin, urea-formaldehyde (UF) resin, unsaturated polyester (UP) resin, epoxy (EP) resin, diallylphthalate (DAP) resin, polyurethane (PUR), polyamide (PA), silicon (SI) resin or their mixtures and compounds.
Subsequently, a lower electrode 42 is formed on the top of the insulating layer 41. The lower electrode 42 may be formed of at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiOa) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
A ferroelectric layer 43 is formed on the lower electrode 42 and an upper electrode 44 is formed on the ferroelectric layer 43 in a direction to cross the lower electrode 42. Like the lower electrode 42, the upper electrode 44 may be formed of at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt) , indium tin oxide (ITO), and strontiumtitanate (SrTiO3), conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3, 4-ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials. Meanwhile, the ferroelectric layer 43 may be formed of a mixture of an inorganic ferroelectric material and an organic ferroelectric material or a mixture of an inorganic ferroelectric material or a solid solution thereof and an organic material or an organic ferroelectric material . At present, there are known various materials showing ferroelectric characteristics. Such materials are broadly classified into inorganic materials and organic materials. The inorganic ferroelectric materials include ferroelectric oxides, ferroelectric fluorides such as BaMgF4 (BMF) , and ferroelectric semiconductors. The organic ferroelectric materials include polymer ferroelectric materials and the like.
The ferroelectric oxides include perovskite ferroelectric materials such as PbZrxTii-xO3 (PZT) , BaTiO3 and PBTiO3, pseudo-ilmenite ferroelectric materials such as LiNbO3 and LiTaO3, tungsten-bronze (TB) ferroelectric materials such as PbNb3Oe and Ba2NaNb5Oi5, ferroelectric materials having a bismuth layer structure such as SrBi2Ta2Og (SBT), (Bi,La) 4Ti3Oi2 (BLT) and Bi4Ti3Oi2, pyrochlore ferroelectric materials such as La?Ti2θ7, and ferroelectric materials such as RMnO3, Pb5Ge3On (PGO) and BiFeO3 (BFO) including a rare earth element (R) such as Y, Er, Ho, Tm, Yb and Lu.
Moreover, the ferroelectric semiconductors include 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe.
Furthermore, the polymer ferroelectric materials include polyvinylidene fluoride (PVDF), PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano-polymer, and polymer or copolymer thereof.
In general, the inorganic ferroelectric materials including the ferroelectric oxides, the ferroelectric fluorides and the ferroelectric semiconductors have dielectric constants greater than those of the organic ferroelectric materials. Accordingly, the generally proposed ferroelectric field-effect transistor (FET) or ferroelectric memory device employs the inorganic ferroelectric materials for forming the ferroelectric layer. According to the study by the present inventor, the inorganic ferroelectric materials are formed at higher temperatures, while their dielectric constants are high. However, the organic materials including the organic ferroelectric materials are formed at lower temperatures, while their dielectric constants are relatively low. Accordingly, when mixing the inorganic ferroelectric materieil with the organic material or the organic ferroelectric material, it is possible to obtain a ferroelectric material having a dielectric constant above a predetermined value and formed at a much lower temperature. In this case, methods of forming mixed solutions of the inorganic ferroelectric material and the organic material or the organic ferroelectric material are as follows :
1. Mixing an inorganic powder with an organic powder and dissolving the mixed powders in a solvent to form a mixed solution;
2. Dissolving an organic powder in an inorganic solution to form a mixed solution;
3. Dissolving an inorganic powder in an organic solution to form a mixed solution; and
4. Mixing an organic solution with an inorganic solution to form a mixed solution.
Moreover, the inorganic ferroelectric material and the organic material may be mixed with each other as follows: 1. Mixing an inorganic ferroelectric material with an organic material;
2. Mixing an inorganic ferroelectric material with an organic ferroelectric material;
3. Mixing a solid solution of an inorganic ferroelectric material with an organic material; 4. Mixing a solid solution of an inorganic ferroelectric material with an organic ferroelectric material; and
5. Mixing the aforementioned mixture with a suicide, a silicate or another metal.
Of course, the above mixing methods are not limited to specific methods and any method that can appropriately mix the inorganic material with the organic material may be employed. The organic materials mixed with the inorganic ferroelectric material include, a monomer, an oligomer, a polymer, and a copolymer. Preferably, an organic material having a high dielectric constant may be used.
The organic materials having a high dielectric constant include polyvinylpyrrolidone (PVP) , polycarbonate (PC) , polyvinyl chloride (PVC) , polystyrene (PS) , epoxy, polymethylmethacrylate (PMMA) , polyimide (PI) , polyethylene (PE) , polyvinyl alcohol (PVA) , polyhexamethylene adipamide (nylon 66), polyetherketoneketone (PEKK), and the like. Moreover, the organic materials include a nonpolar organic material, such as fluorinated para-xylene, fluoropolyarylether, fluorinated polyimide, polystyrene, poly (α-methyl styrene) , poly (α-vinylnaphthalene) , poly (vinyltoluene) , polyethylene, cis-polybutadiene, polypropylene, polyisoprene, poly (4-methyl-l-pentene) , poly (tetrafluoroethylene) , poly (chlorotrifluoroethylene) , poly (2-methyl-l, 3-butadiene) , poly (p-xylylene) , poly (α-α-α' - α' -tetrafluoro-p-xylylene) , poly [1, 1- (2-methyl propane) bis (4-phenyl) carbonate] , poly (cyclohexyl methacrylate) , poly (chlorostyrene) , poly (2, β-dimethyl-1, 4- phenylene ether), polyisobutylene, poly (vinyl cyclohexane) , poly(arylene ether), and polyphenylene, or copolymers having a low dielectric constant, such as poly (ethylene/tetrafluoroethylene) , poly (ethylene/chlorotrifluoroethylene) , fluorinated ethylene/propylene copolymer, polystyrene-co-α-methyl styrene, ethylene/ethyl acrylate copolymer, poly (styrene/10%butadiene) , poly (styrene/15%butadiene) , poly (styrene/2, 4-dimethylstyrene) , Cytop, Teflon AF, and polypropylene-co-1-butene.
Other organic semi-conducting materials that can be used in this invention include soluble compounds and soluble derivatives of compounds of the following list: conjugated hydrocarbon polymers such as polyacene, polyphenylene, poly (phenylene vinylene) , polyfluorene including oligomers of those conjugated hydrocarbon polymers; condensed aromatic hydrocarbons such as anthracene, tetracene, chrysene, pentacene, pyrene, perylene, coronene; oligomeric para substituted phenylenes such as p-quaterphenyl (p-4P) , p- quinquephenyl (p-5P) , p-sexiphenyl (p-6P) ; conjugated heterocyclic polymers such as poly (3-substituted thiophene) , poly (3, 4-bisubstituted thiophene), polybenzothiophene, polyisothianapthene, poly (N-substituted pyrrole), poly (3- substituted pyrrole), poly (3, 4-bisubstituted pyrrole), polyfuran, polypyridine, poly-1, 3, 4-oxadiazoles, polyisothianaphthene, poly (N-substituted aniline), poly (2- substituted aniline), poly (3-substituted aniline), poly (2, 3- bisubstituted aniline) , polyazulene, polypyrene; pyrazoline compounds; polyselenophene; polybenzofuran; polyindole; polypyridazine; benzidine compounds; stilbene compounds; triazines; substituted metallo- or metal-free porphines, phthalocyanines, fluorophthalocyanines, naphthalocyanines, or fluoronaphthalocyanines; Ceo and C70 fullerenes; N,N'- dialkyl, substituted dialkyl, diaryl or substituted diaryl- 1, 4, 5, 8-naphthalenetetracarboxylic diimide; N, N' -dialkyl, substituted dialkyl, diaryl or substituted diaryl 3,4,9,10- perylenetetracarboxylicdiimide; bathophenanthroline; diphenoquinones; 1, 3, 4-oxadiazoles; 11,11,12,12- tetracyanonaptho-2, β-quinodimethane; α, α' -bis (dithieno [3,2- b2' ,3'-d] thiophene) ; 2,8-dialkyl, substituted dialkyl, diaryl or substituted diaryl anthradithiophene; and 2,2'- bibenzo [ 1 , 2-b : 4 , 5-b ' ] dithiophene .
Ib is possible to appropriately set the mixture ratio of the inorganic material and the organic material. If the mixture ratio of the inorganic ferroelectric material is increased, the formation temperature is increased while the dielectric constant of the mixture is increased, whereas if the mixture ratio of the inorganic ferroelectric material is decreased, the formation temperature is lowered while the dielectric constant of the mixture is reduced.
Since the present invention adopts a structure that selectively polarizes the ferroelectric layer 43 only, the available ferroelectric materials are not limited.
As described above, the present invention has the structure in which the ferroelectric capacitor is formed on the transistor, in which the data write operation is made independently with respect to the ferroelectric capacitor.
Accordingly, the preset invention provides the following technical effects: 1. Since a depolarization fieLd of the insulating layer with respect to a polarization field of the ferroelectric layer is removed in the present invention, excellent data retention characteristics are provided;
2. Since the data read and write operation is carried out in the ferroelectric capacitor of the selected memory cell only, the data disturbance phenomenon is prevented;
3. Since only the ferroelectric layer 43 is selectively polarized, the present invention does not require specific materials as the ferroelectric material and the insulating material of the insulating layer 41, and thus the degree of design freedom is significantly increased;
4. Since the transistor is turned ON/OFF by the polarization value of the ferroelectric layer 43 and the polarization value of the ferroelectric layer 43 is maintained by the next rewrite, it is possible to realize the non-volatile memory device having a IT structure; and
5. Since the transistor can be turned ON/OFF by polarizing the ferroelectric layer 43, the structure in accordance with the present invention can be used as the field-effect transistor.
The invention has been described in detail with reference to preferred embodiments thereof. However, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
[industrial Applicability]
As described above, according to the present invention, it is possible to provide an MFMIS type ferroelectric memory device with a simple structure and having excellent data retention characteristics, and a method of manufacturing the same .
Moreover, according to the present invention, it is possible to realize an MFMIS type field-effect transistor.


Claims

[CLAIMS]
[Claim l]
A metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate; a transistor formed on the substrate; and a ferroelectric capacitor formed on the transistor, wherein the ferroelectric capacitor comprises a lower electrode layer, an upper electrode layer, and a ferroelectric layer formed between the lower and upper electrode layers, in which the lower electrode layer is a data electrode and the upper electrode layer is a ground electrode .
[Claim 2]
The MFMIS type ferroelectric memory device of claim 1, wherein the transistor comprises: drain and source regions formed on the substrate; a channel region formed between the drain and source regions; and an insulating layer formed on the channel region.
[Claim 3]
A metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate; a transistor formed on the substrate; and a ferroelectric capacitor formed on the transistor, wherein the ferroelectric capacitor comprises a lower electrode layer, an upper electrode layer, and a ferroelectric layer formed between the lower and upper electrode layers, in which the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode.
[Claim 4]
The MFMIS type ferroelectric memory device of claim 3, wherein the transistor comprises: drain and source regions formed on the substrate; a channel region formed between the drain and source regions; and an insulating layer formed on the channel region.
[Claim 5] A metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a data electrode and the upper electrode layer is a ground electrode.
[Claim 6]
The MFMIS type ferroelectric memory device of claim 5, wherein the substrate comprises paper or an organic material
[Claim 7] The MFMIS type ferroelectric memory device of claim 5, wherein the ferroelectric layer comprises an inorganic ferroelectric material.
[Claim 8] The MFMIS type ferroelectric memory device of claim 5, wherein the ferroelectric layer comprises an organic ferroelectric material.
[Claim 9] The MFMIS type ferroelectric memory device of claim 5, wherein the ferroelectric layer comprises a mixture of an inorganic ferroelectric material and an organic material.
[Claim 10] The MFMIS type ferroelectric memory device of claim 5, wherein the ferroelectric layer comprises a mixture of an inorganic ferroelectric material and an organic ferroelectric material.
[Claim 11]
The MFMIS type ferroelectric memory device of claim 5, wherein the ferroelectric layer comprises a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
[Claim 12]
The MFMIS type ferroelectric memory device of claim 5, wherein the ferroelectric layer comprises a mixture of a solid solution of an inorganic ferroelectric material and an organic ferroelectric material.
[Claim 13]
The MFMIS type ferroelectric memory device of claim 5, wherein the ferroelectric layer further comprises a suicide, a silicate or any other metal.
[Claim 14]
The MFMIS type ferroelectric memory device of claim 5, wherein the lower electrode layer and the upper electrode layer comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag), aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO3), conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
[Claim 15]
The MFMIS type ferroelectric memory device of claim 5, wherein the lower electrode layer and the upper electrode layer are arranged to extend in a direction to cross each other.
[Claim 16]
A metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type ferroelectric memory device comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode.
[Claim 17]
The MFMIS type ferroelectric memory device of claim 16, wherein the substrate comprises paper or an organic material.
[Claim 18]
The MFMIS type ferroelectric memory device of claim 16, wherein the ferroelectric layer comprises an inorganic ferroelectric material.
[Claim 19]
The MFMIS type ferroelectric memory device of claim 16, wherein the ferroelectric layer comprises an organic ferroelectric material.
[Claim 20]
The MFMIS type ferroelectric memory device of claim 16, wherein the ferroelectric layer comprises a mixture of an inorganic ferroelectric material and an organic material.
[Claim 21]
The MFMIS type ferroelectric memory device of claim 16, wherein the ferroelectric layer comprises a mixture of an inorganic ferroelectric material and an organic ferroelectric material.
[Claim 22]
The MFMIS type ferroelectric memory device of claim 16, wherein the ferroelectric layer comprises a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
[Claim 23] The MFMIS type ferroelectric memory device of claim 16, wherein the ferroelectric layer comprises a mixture of a solid solution of an inorganic ferroelectric material and an organic ferroelectric material.
[Claim 24] The MFMIS type ferroelectric memory device of claim 16, wherein the ferroelectric layer further comprises a suicide, a silicate or any other metal.
[Claim 25]
The MFMIS type ferroelectric memory device of claim 16, wherein the lower electrode layer and the upper electrode layer comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt) , indium tin oxide (ITO) , and strontiumtitanate (SrTiCb) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3, 4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS), conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
[Claim 26] The MFMIS type ferroelectric memory device of claim 16, wherein the insulating layer is formed of silicon dioxide (SiO2) .
[Claim 27] The MFMIS type ferroelectric memory device of claim 16, wherein the lower electrode layer and the upper electrode layer are arranged to extend in a direction to cross each other.
[Claim 28]
A metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type field-effect transistor (FET) comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a data electrode and the upper electrode layer is a ground electrode.
[Claim 29]
A metal-ferroelectric-metal-insulator-semiconductor (MFMIS) type field-effect transistor (FET) comprising: a substrate on which source and drain regions and a channel region are formed, the channel region being formed between the source and drain regions; an insulating layer formed on the channel region; a lower electrode layer formed on the insulating layer; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode.
[Claim 30]
A method of manufacturing a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device, the method comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a data electrode layer on the channel region; forming a ferroelectric layer on the data electrode layer; and forming a ground electrode layer on the ferroelectric layer .
[Claim 31]
The method of claim 30, wherein the substrate comprises paper or an organic material.
[Claim 32]
The method of claim 30, wherein the ferroelectric layer comprises at least one selected from the group consisting of an inorganic material, an organic material, and a mixture thereof.
[Claim 33]
The method of claim 32, wherein the ferroelectric layer further comprises a suicide, a silicate or any other metal .
[Claim 34]
The method of claim 30, wherein the lower electrode layer and the upper electrode layer comprise at least one selected from the group consisting of conductive metals including gold (Au), silver (Ag), aluminum (Al), platinum
(Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO3), conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3, 4-ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
[Claim 35] The method of claim 30, wherein the lower electrode layer and the upper electrode layer are arranged to extend in a direction to cross each other.
[Claim 36] A method of manufacturing a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type ferroelectric memory device, the method comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a ground electrode layer on the channel region; forming a ferroelectric layer on the ground electrode layer; and forming a data electrode layer on the ferroelectric layer.
[Claim 37] The method of claim 36, wherein the substrate comprises paper or an organic material .
[Claim 38]
The method of claim 36, wherein the ferroelectric layer comprises at least one selected from the group consisting of an inorganic material, an organic material, and a mixture thereof.
[Claim 39] The method of claim 38, wherein the ferroelectric layer further comprises a suicide, a silicate or any other metal .
[Claim 40] The method of claim 36, wherein the lower electrode layer and the upper electrode layer comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt) , indium tin oxide (ITO) , and strontiumtitanate (SrTiOa) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3, 4-ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS), conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
[Claim 41]
The method of claim 36, wherein the lower electrode layer and the upper electrode layer are arranged to extend in a direction to cross each other.
[Claim 42]
A method of manufacturing a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type field-effect transistor (FET), the method comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a data electrode layer on the channel region; forming a ferroelectric layer on the data electrode layer; and forming a ground electrode layer on the ferroelectric layer.
[Claim 43]
A method of manufacturing a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) type field-effect transistor (FET) , the method comprising: forming source and drain region on a substrate; forming a channel region between the source and drain regions; forming an insulating layer on the channel region; forming a ground electrode layer on the channel region; forming a ferroelectric layer on the ground electrode layer; and forming a data electrode layer on the ferroelectric layer.
PCT/KR2007/002887 2007-04-12 2007-06-14 Mfmis-fet, mfmis-ferroelectric memory device, and methods of manufacturing the same WO2008126961A1 (en)

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