WO2008082044A1 - Fet, ferroelectric memory device, and methods of manufacturing the same - Google Patents

Fet, ferroelectric memory device, and methods of manufacturing the same Download PDF

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Publication number
WO2008082044A1
WO2008082044A1 PCT/KR2007/002882 KR2007002882W WO2008082044A1 WO 2008082044 A1 WO2008082044 A1 WO 2008082044A1 KR 2007002882 W KR2007002882 W KR 2007002882W WO 2008082044 A1 WO2008082044 A1 WO 2008082044A1
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Prior art keywords
ferroelectric
layer
polymer
pvdf
memory device
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PCT/KR2007/002882
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French (fr)
Inventor
Byung-Eun Park
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University Of Seoul Foundation Of Industry-Academic Cooperation
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Priority claimed from KR1020070057539A external-priority patent/KR100877428B1/en
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Publication of WO2008082044A1 publication Critical patent/WO2008082044A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer

Definitions

  • the present invention relates to a metal- ferroelectric-metal-semiconductor (MFMS) field-effect transistor (FET) , a ferroelectric memory device having a simple structure and excellent data retention characteristics, and methods of manufacturing the same.
  • MFMS metal- ferroelectric-metal-semiconductor
  • FET field-effect transistor
  • FIG. 1 is a cross-sectional view showing a typical structure of a metal-ferroelectric- semiconductor (MFS) type memory device using a ferroelectric material.
  • FMS metal-ferroelectric- semiconductor
  • the ferroelectric layer 5 comprises an inorganic material having ferroelectric properties such as PbZr x Tii_ x O 3 (PZT) , SrBi 2 Ta 2 O 9 (SBT), (Bi, La) 4Ti 3 Oi 2 (BLT), and the like.
  • a source electrode 6, a drain electrode 7 and a gate electrode 8 formed of a metal material, respectively, are arranged on the top of the source and drain regions 2 and 3 and the ferroelectric layer 5.
  • the ferroelectric layer 5 has polarization characteristics according to a voltage applied through the gate electrode 8, and a conductive channel is formed between the source region 2 and the drain region 3 by the polarization characteristics. As a result, a current flows between the source electrode 6 and the drain electrode 7. Especially, in the above-described structure, even in the case where the voltage applied through the gate electrode 8 is cut off, the polarization characteristics of the ferroelectric layer 5 are continuously maintained. Accordingly, the above-described structure has attracted much attention since it can form a non-volatile memory only with one transistor (IT) even though a capacitor is not provided.
  • IT transistor
  • the ferroelectric memory having the above- described structure has the following problems. That is, when the ferroelectric layer 5 is directly formed on the silicon substrate 1, a transition layer of low quality is formed on the boundary between the ferroelectric layer 5 and the silicon substrate 1 during the formation of the ferroelectric layer 5, and chemical elements such as Pb and Bi in the ferroelectric layer 5 are diffused into the silicon substrate 1, thus making it difficult to form a ferroelectric layer 5 of high quality. As a result, there occurs a problem that the polarization characteristics of the ferroelectric layer 5 are deteriorated, that is, the data retention time of the ferroelectric memory becomes very short .
  • MFIS metal- ferroelectric-insulator-semiconductor
  • the MFIS type ferroelectric memory has some problems in that it requires an additional process of forming the buffer layer 20, and the polarization characteristics of the ferroelectric layer 5 are deteriorated due to a depolarization field caused by the buffer layer 20 provided between the ferroelectric layer 5 and the substrate 1, thus deteriorating the data retention characteristics .
  • FIG. 3 is a diagram showing an equivalent circuit in a state where a gate voltage applied to the gate electrode 8 is cut off in the MFIS structure.
  • a capacitor Cl corresponds to the ferroelectric layer 5 and a capacitor C2 corresponds to the buffer layer 20.
  • an inner potential is set to 0.
  • the ferroelectric material has a constant polarization value Q due to a spontaneous polarization even in the case where the external voltage is cut off. That is, in the equivalent circuit of FIG. 3, the capacitor Cl corresponding to the ferroelectric layer 5 has a polarization value Q.
  • an inverse polarization field is generated in the capacitor C2 to make the potential of the closed loop become 0 in general by offsetting the polarization value Q of the capacitor Cl. Since the direction of the inverse polarization field is opposite to that of the polarization field by the capacitor Cl, the polarization value Q of the capacitor Cl may be continuously deteriorated.
  • the polarization characteristics of the ferroelectric layer 5 are deteriorated due to the depolarization field caused by the buffer layer 20 and thereby the data retention characteristics are degraded. As a result, the data retention time cannot exceed 30 days even in case of an excellent product manufactured in a laboratory.
  • the present invention has been made in an effort to solve the above-described problems.
  • the present invention provides a metal-ferroelectric-metal-semiconductor (MFMS) field-effect transistor (FET) and a ferroelectric memory device having a simple structure and excellent data retention characteristics.
  • MFMS metal-ferroelectric-metal-semiconductor
  • FET field-effect transistor
  • the present invention provides methods of manufacturing the MFMS-FET and the ferroelectric memory device .
  • a ferroelectric memory device including a substrate, a gate electrode, a drain electrode, a source electrode, a channel forming layer, and a ferroelectric layer
  • the ferroelectric memory device comprising: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
  • a ferroelectric memory device in accordance with the present invention comprises: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
  • a field-effect transistor comprising: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
  • a field-effect transistor in accordance with the present invention comprises: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material .
  • the lower electrode layer may be a data electrode.
  • the upper electrode layer may be a ground electrode.
  • the lower and upper electrode layers may comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO 3 ) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
  • conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO 3 )
  • the lower electrode layer and the upper electrode layer may be arranged to extend in a direction where they intersect each other.
  • the lower electrode layer may be a ground electrode and the upper electrode layer may be a data electrode.
  • the inorganic ferroelectric material may comprise at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture thereof.
  • the inorganic ferroelectric material may be PZT.
  • the mixture may further comprise a suicide, a silicate or any other metal.
  • the organic material may be a polymer ferroelectric material .
  • the polymer ferroelectric material may comprise at least one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano- polymer, and polymer or copolymer thereof.
  • PVDF polyvinylidene fluoride
  • the polymer ferroelectric material may be PVDF-TrFE.
  • the ferroelectric layer may be formed by heating and baking a mixed solution of an inorganic ferroelectric solution and an organic solution.
  • a method of manufacturing a field-effect transistor comprising: forming source and drain regions on a substrate; forming a channel region between the source and drain regions; forming a lower electrode on the top of the channel region; forming a mixed solution of an inorganic ferroelectric material and an organic material; forming a ferroelectric layer by coating the mixed solution on the lower electrode and then baking and etching the resulting lower electrode; and forming an upper electrode on the ferroelectric layer.
  • a method of manufacturing a field-effect transistor comprising: forming source and drain regions on a substrate; forming a channel region between the source and drain regions; forming a lower electrode on the top of the channel region; forming a mixed solution of an inorganic ferroelectric material and an organic material; forming a ferroelectric layer by coating the mixed solution on the lower electrode and then baking and etching the resulting lower electrode; and forming an upper electrode on the ferroelectric layer.
  • the inorganic ferroelectric material may comprise at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture thereof.
  • the inorganic ferroelectric material may be PZT.
  • the mixed solution may further comprise a silicide, a silicate or any other metal.
  • the organic material may be a polymer ferroelectric material .
  • the polymer ferroelectric material may comprise at least one selected from the group consisting of polyvinylidene fluoride (PVDF), PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano- polymer, and polymer or copolymer thereof.
  • PVDF polyvinylidene fluoride
  • the polymer ferroelectric material may be PVDF-TrFE.
  • the mixed solution may comprises a PZT solution and a PVDF-TrFE solution.
  • the PZT solution may be prepared by mixing a PZO solution and a PTO solution.
  • the PVDF-TrFE solution may be prepared by dissolving PVDF-TrFE powder in at least one solvent selected from the group consisting of C 4 H 5 O (THF), C 4 H 8 O (MEK), C 3 H 6 O (acetone), C 3 H 7 NO (DMF), and C 2 H 6 OS (DMSO).
  • solvent selected from the group consisting of C 4 H 5 O (THF), C 4 H 8 O (MEK), C 3 H 6 O (acetone), C 3 H 7 NO (DMF), and C 2 H 6 OS (DMSO).
  • the ferroelectric layer may be formed by a spin coating, ink-jet printing or screen printing method.
  • An etching process of the ferroelectric layer may be performed by a buffered oxide etching (BOE) method.
  • the etching process of the ferroelectric layer may be performed by a two-step etching method using BOE and gold etchant .
  • the etching process of the ferroelectric layer may be performed by a reactive ion etching (RIE) method.
  • RIE reactive ion etching
  • the baking temperature may be below 200 ° C.
  • FIG. 1 is a cross-sectional view showing a structure of a conventional metal-ferroelectric-semiconductor (MFS) type memory device;
  • MFS metal-ferroelectric-semiconductor
  • FIG. 2 is a cross-sectional view showing a structure of a conventional metal-ferroelectric-insulator- semiconductor (MFIS) type memory device;
  • MFIS metal-ferroelectric-insulator- semiconductor
  • FIG. 3 is a diagram illustrating problems of the conventional structure shown in FIG. 2;
  • FIG. 4 is a cross-sectional view showing a structure of a metal-ferroelectric-metal-semiconductor (MFMS) field- effect transistor (FET) or an MFMS-ferroelectric memory device in accordance with a preferred embodiment of the present invention
  • FIGS. 5 to 9 are graphs showing capacitance-voltage characteristics of ferroelectric materials applied to the present invention.
  • FIG. 4 is a cross-sectional view showing a structure of a metal-ferroelectric-metal-semiconductor (MFMS) field- effect transistor (FET) or an MFMS-ferroelectric memory device in accordance with a preferred embodiment of the present invention, in which the same elements as those shown in FIGS. 1 and 2 have the same reference numerals.
  • MFMS metal-ferroelectric-metal-semiconductor
  • FET field- effect transistor
  • the ferroelectric memory device in accordance with the present invention has a metal-ferroelectric-metal- semiconductor (MFMS) structure, differently from a conventional metal-ferroelectric-semiconductor (MFS) structure and a metal-ferroelectric-insulator-semiconductor (MFIS) structure.
  • MFMS metal-ferroelectric-metal- semiconductor
  • source and drain regions 2 and 3 are formed in predetermined areas of a silicon substrate 1, and a lower electrode layer is formed on a channel region 4 between the source and drain regions 2 and 3 and used as a data electrode, for example.
  • the data electrode 30 is provided to generate a polarization voltage in a ferroelectric layer 31 to be described later.
  • the data electrode 30 may be formed of at least one selected from the group consisting of conductive metals including gold (Au), silver (Ag), aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTi.0 3 ) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS), conductive organic mixtures, conductive organic compounds, and conductive orcjanic multilayer materials.
  • conductive metals including gold (Au), silver (Ag), aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTi.0 3 )
  • conductive metal oxides conductive metal alloys
  • conductive metal compounds and, further, conductive organic
  • the ferroelectric layer 31 is formed on the data electrode 30, and an upper electrode layer is formed on the ferroelectric layer 31 and used as a ground electrode 32, for example.
  • the ground electrode 32 may be formed of at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt) , indium tin oxide (ITO), and strontiumtitanate (SrTiO 3 ), conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3, 4-ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
  • a conductive polymer such as polyaniline and poly (3, 4-ethylenedioxythiophene) /poly (styrenes
  • the ferroelectric layer 31 may be formed of a mixture of an inorganic ferroelectric material or a solid solution thereof and an organic material or an organic ferroelectric material.
  • the inorganic ferroelectric materials include ferroelectric oxides, ferroelectric fluorides such as BaMgF 4 (BMF) , and ferroelectric semiconductors.
  • the organic ferroelectric materials include polymer ferroelectric materials and the like.
  • the ferroelectric oxides include perovskite ferroelectric materials such as PbZr x Tii- x O 3 (PZT) , BaTiO 3 and PBTiO 3 , pseudo-ilmenite ferroelectric materials such as LiNbO 3 and LiTaO 3 , tungsten-bronze (TB) ferroelectric materials such as PbNb 3 Oe and Ba 2 NaNb S Oi 5 , ferroelectric materials having a bismuth layer structure such as SrBi 2 Ta 2 Og (SBT), (Bi,La) 4Ti 3 Oi 2 (BLT) and Bi 4 Ti 3 Oi 2 , pyrochlore ferroelectric materials such as La 2 Ti 2 O 7 , and ferroelectric materials such as RMnO 3 , Pb 5 Ge 3 On (PGO) and BiFeO 3 (BFO) including a rare earth element (R) such as Y, Er, Ho, Tm, Yb and Lu.
  • the ferroelectric semiconductors include 2-6
  • polymer ferroelectric materials include polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano-polymer, and polymer or copolymer thereof.
  • PVDF polyvinylidene fluoride
  • the inorganic ferroelectric materials including the ferroelectric oxides, the ferroelectric fluorides and the ferroelectric semiconductors have dielectric constants greater than those of the organic ferroelectric materials.
  • the generally proposed ferroelectric field-effect transistor (FET) or ferroelectric memory device employs the inorganic ferroelectric materials for forming the ferroelectric layer.
  • the inorganic ferroelectric materials are formed at higher temperatures, while their dielectric constants are high.
  • the organic materials including the organic ferroelectric materials are formed at lower temperatures, while their dielectric constants are relatively low.
  • the inorganic ferroelectric material and the organic material may be mixed with each other as follows:
  • the organic materials mixed with the inorganic ferroelectric material include, a monomer, an oligomer, a polymer, and a copolymer.
  • an organic material having a high dielectric constant may be used.
  • the organic materials having a high dielectric constant include polyvinylpyrrolidone (PVP) , polycarbonate (PC) , polyvinyl chloride (PVC) , polystyrene (PS) , epoxy, polymethylmethacrylate (PMMA) , polyimide (PI) , polyethylene (PE) , polyvinyl alcohol (PVA) , polyhexamethylene adipamide (nylon 66), polyetherketoneketone (PEKK), and the like.
  • PVP polyvinylpyrrolidone
  • PC polycarbonate
  • PVC polyvinyl chloride
  • PS polystyrene
  • PI polyimide
  • PE polyethylene
  • PVA polyvinyl alcohol
  • PEKK polyhexamethylene adip
  • the organic materials include nonpolar organic materials, such as fluorinated para-xylene, fluoropolyarylether, fluorinated polyimide, polystyrene, poly ( ⁇ -methyl styrene) , poly ( ⁇ -vinylnaphthalene) , poly (vinyltoluene) , polyethylene, cis-polybutadiene, polypropylene, polyisoprene, poly (4-methyl-l-pentene) , poly (tetrafluoroethylene) , poly (chlorotrifluoroethylene) , poly (2-methyl-l, 3-butadiene) , poly (p-xylylene) , poly( ⁇ - ⁇ - ⁇ '- ⁇ ' -tetrafluoro-p-xylylene) , poly [1,1- (2-methyl propane) bis (4-phenyl) carbonate] , poly (cyclohexyl methacrylate) , poly (chlorostyrene,
  • organic semi-conducting materials that can be used in this invention include soluble compounds and soluble derivatives of compounds of the following list: conjugated hydrocarbon polymers such as polyacene, polyphenylene, poly (phenylene vinylene) , polyfluorene including oligomers of those conjugated hydrocarbon polymers; condensed aromatic hydrocarbons such as anthracene, tetracene, chrysene, pentacene, pyrene, perylene, coronene; oligomeric para substituted phenylenes such as p-quaterphenyl (p-4P) , p- quinquephenyl (p-5P) , p-sexiphenyl (p-6P) ; conjugated heterocyclic polymers such as poly (3-substituted thiophene) , poly (3, 4-bisubstituted thiophene), polybenzothiophene, polyisothianapthene, poly (N-substit
  • the mixture ratio of the inorganic material and the organic material it is possible to appropriately set the mixture ratio of the inorganic material and the organic material. If the mixture ratio of the inorganic ferroelectric material is increased, the formation temperature is increased while the dielectric constant of the mixture is increased, whereas if the mixture ratio of the inorganic ferroelectric material is decreased, the formation temperature is lowered while the dielectric constant of the mixture is reduced.
  • the ferroelectric layer is formed using a mixed solution of an inorganic material and an organic material, it is possible to easily form the ferroelectric layer by an ink-jet printing, spin coating or screen printing method;
  • the formation temperature of the ferroelectric layer is lowered to below about 200 ° C, it is possible to form the ferroelectric layer having excellent data retention characteristics on the silicon substrate;
  • FIGS. 5 to 9 are graphs showing polarization characteristics of ferroelectric layers formed of an inorganic ferroelectric material and an organic ferroelectric material such as PbZr x Tii_ x O 3 (PZT) and PVDF- TrFE mixed in predetermined ratios.
  • PZT PbZr x Tii_ x O 3
  • the ferroelectric layer was formed in such a manner that a PZT solution and a PVDF-TrFE solution were mixed in a predetermined ratio to form a mixed solution, the mixed solution was coated on a silicon wafer by a spin coating method, and the resulting silicon wafer was heated in the temperature range of 150 to 200 ° C on a hot plate for a predetermined period of time.
  • the PZT solution was prepared by mixing a PZO solution and a PTO solution, in which the PZO solution was formed by mixing a zirconium propoxide solution with a mixed solution of a 2-methoxyethanol solution and a lead acetate trihydrate solution and the PTO solution was formed by mixing a titanium isopropoxide solution with the mixed solution of the 2-methoxyethanol solution and the lead acetate trihydrate solution.
  • the PVDF-TrFE solution was prepared by dissolving PVDF-TrFE powder in a solvent such as C 4 H 5 O (THF) , C 4 H 8 O (MEK), C 3 H 6 O (acetone), C 3 H 7 NO (DMF), and C 2 H 6 OS (DMSO).
  • a solvent such as C 4 H 5 O (THF) , C 4 H 8 O (MEK), C 3 H 6 O (acetone), C 3 H 7 NO (DMF), and C 2 H 6 OS (DMSO).
  • FIG. 5 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:1
  • FIG. 6 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 2:1
  • FIG. 7 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 3:1
  • FIG. 8 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:2
  • FIGS. 5A, 6A and 7A the thickness of the ferroelectric layer was 50 ran; in FIGS. 5B, 6B, 7B, 8 and 9, the thickness of the ferroelectric layer was 75 ran; and in FIG. 5C, the thickness of the ferroelectric layer was 100 nm. Moreover, in FIGS. 5A, 6A and 7A, the thickness of the ferroelectric layer was 50 ran; in FIGS. 5B, 6B, 7B, 8 and 9, the thickness of the ferroelectric layer was 75 ran; and in FIG. 5C, the thickness of the ferroelectric layer was 100 nm. Moreover, in FIGS.
  • the characteristic curves represented as A show the polarization characteristics in which the formation temperature of the ferroelectric layer was 190 ° C
  • the characteristic curves represented as B show the polarization characteristics in which the formation temperature of the ferroelectric layer was 170 ° C
  • the characteristic curves represented as C show the polarization characteristics in which the formation temperature of the ferroelectric layer was 150 ° C.
  • the polarization is generated in the ferroelectric layer 31 by applying a predetermined voltage through the data electrode 30 in a state where the ground electrode 32 is connected to the ground.
  • a channel is formed or not in the channel region 4 between the source region 2 and the drain region 3 based on polarization characteristics.
  • the current flow between the source region 2 and the drain region 3 is generated or cut off through the channel formed as described above, thus functioning as a transistor.
  • a predetermined voltage is applied to a drain electrode 7 and, at the same time, it is determined whether the data stored in a corresponding memory cell is "1" or ⁇ 0" based on whether or not the transistor is in a conductive state while grounding a source electrode 6. Accordingly, with the above-described one-transistor (IT) structure, it is possible to form one memory cell.
  • the ferroelectric layer 31 is not directly in contact with the silicon substrate 1 but connected thereto through the data electrode 30. Accordingly, it is possible to solve the problem that a transition layer of low quality is formed on the boundary between the ferroelectric layer 5 and the silicon substrate 1 during the formation of the ferroelectric layer 5.

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Abstract

Disclosed herein are a metal-ferroelectric-metal-semiconductor (MFMS) field-effect transistor (FET), an MFMS-ferroelectric memory device, and methods of manufacturing the same. The FET and the ferroelectric memory device in accordance with the present invention include: a substrate 1 including source and drain regions 2 and 3, and a channel region 4 formed therebetween; a lower electrode layer 30 formed on the top of the channel region 4 of the substrate 1; a ferroelectric layer 31 formed on the lower electrode layer 30; and an upper electrode layer 32 formed on the ferroelectric layer 31. The ferroelectric layer 31 is composed of a mixture of an inorganic ferroelectric material or a solid solution thereof and an organic material or an organic ferroelectric material.

Description

[DESCRIPTION]
[invention Title]
FET, FERROELECTRIC MEMORY DEVICE, AND METHODS OF MANUFACTURING THE SAME
[Technical Field]
The present invention relates to a metal- ferroelectric-metal-semiconductor (MFMS) field-effect transistor (FET) , a ferroelectric memory device having a simple structure and excellent data retention characteristics, and methods of manufacturing the same.
[Background Art]
At present, extensive research aimed at realizing a transistor or a memory device using a ferroelectric material has continued to progress. FIG. 1 is a cross-sectional view showing a typical structure of a metal-ferroelectric- semiconductor (MFS) type memory device using a ferroelectric material. As shown in FIG. 1, source and drain regions 2 and 3 are formed in predetermined areas of a silicon substrate 1, and a ferroelectric layer 5 is formed on a channel region 4 between the source and drain regions 2 and 3. In this case, the ferroelectric layer 5 comprises an inorganic material having ferroelectric properties such as PbZrxTii_xO3 (PZT) , SrBi2Ta2O9 (SBT), (Bi, La) 4Ti3Oi2 (BLT), and the like. Moreover, a source electrode 6, a drain electrode 7 and a gate electrode 8 formed of a metal material, respectively, are arranged on the top of the source and drain regions 2 and 3 and the ferroelectric layer 5.
In the ferroelectric memory having the above-described structure, the ferroelectric layer 5 has polarization characteristics according to a voltage applied through the gate electrode 8, and a conductive channel is formed between the source region 2 and the drain region 3 by the polarization characteristics. As a result, a current flows between the source electrode 6 and the drain electrode 7. Especially, in the above-described structure, even in the case where the voltage applied through the gate electrode 8 is cut off, the polarization characteristics of the ferroelectric layer 5 are continuously maintained. Accordingly, the above-described structure has attracted much attention since it can form a non-volatile memory only with one transistor (IT) even though a capacitor is not provided.
However, the ferroelectric memory having the above- described structure has the following problems. That is, when the ferroelectric layer 5 is directly formed on the silicon substrate 1, a transition layer of low quality is formed on the boundary between the ferroelectric layer 5 and the silicon substrate 1 during the formation of the ferroelectric layer 5, and chemical elements such as Pb and Bi in the ferroelectric layer 5 are diffused into the silicon substrate 1, thus making it difficult to form a ferroelectric layer 5 of high quality. As a result, there occurs a problem that the polarization characteristics of the ferroelectric layer 5 are deteriorated, that is, the data retention time of the ferroelectric memory becomes very short . In consideration of the above problems, as shown in FIG. 2, there has been recently proposed a so-called metal- ferroelectric-insulator-semiconductor (MFIS) structure, in which a buffer layer 20 formed mainly of an oxide is provided between the silicon substrate 1 and the ferroelectric layer 5.
However, the MFIS type ferroelectric memory has some problems in that it requires an additional process of forming the buffer layer 20, and the polarization characteristics of the ferroelectric layer 5 are deteriorated due to a depolarization field caused by the buffer layer 20 provided between the ferroelectric layer 5 and the substrate 1, thus deteriorating the data retention characteristics .
That is, FIG. 3 is a diagram showing an equivalent circuit in a state where a gate voltage applied to the gate electrode 8 is cut off in the MFIS structure. In FIG. 3, a capacitor Cl corresponds to the ferroelectric layer 5 and a capacitor C2 corresponds to the buffer layer 20. In case of a dielectric layer formed of a dielectric material, if an externally applied voltage is cut off, an inner potential is set to 0. However, the ferroelectric material has a constant polarization value Q due to a spontaneous polarization even in the case where the external voltage is cut off. That is, in the equivalent circuit of FIG. 3, the capacitor Cl corresponding to the ferroelectric layer 5 has a polarization value Q.
Accordingly, in a closed loop .including the capacitors Cl and C2 connected in series, an inverse polarization field is generated in the capacitor C2 to make the potential of the closed loop become 0 in general by offsetting the polarization value Q of the capacitor Cl. Since the direction of the inverse polarization field is opposite to that of the polarization field by the capacitor Cl, the polarization value Q of the capacitor Cl may be continuously deteriorated.
As described above, in the MFIS type ferroelectric memory shown in FEG. 2, the polarization characteristics of the ferroelectric layer 5 are deteriorated due to the depolarization field caused by the buffer layer 20 and thereby the data retention characteristics are degraded. As a result, the data retention time cannot exceed 30 days even in case of an excellent product manufactured in a laboratory.
[Disclosure] [Technical Problem]
Accordingly, the present invention has been made in an effort to solve the above-described problems. The present invention provides a metal-ferroelectric-metal-semiconductor (MFMS) field-effect transistor (FET) and a ferroelectric memory device having a simple structure and excellent data retention characteristics.
Moreover, the present invention provides methods of manufacturing the MFMS-FET and the ferroelectric memory device .
[Technical Solution]
In accordance with a first aspesct of the present invention, there is provided a ferroelectric memory device including a substrate, a gate electrode, a drain electrode, a source electrode, a channel forming layer, and a ferroelectric layer, the ferroelectric memory device comprising: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material. Moreover, a ferroelectric memory device in accordance with the present invention comprises: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material. In accordance with a second aspect of the present invention, there is provided a field-effect transistor comprising: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material. Furthermore, a field-effect transistor in accordance with the present invention comprises: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material . The lower electrode layer may be a data electrode.
The upper electrode layer may be a ground electrode. The lower and upper electrode layers may comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO3) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
The lower electrode layer and the upper electrode layer may be arranged to extend in a direction where they intersect each other. The lower electrode layer may be a ground electrode and the upper electrode layer may be a data electrode.
The inorganic ferroelectric material may comprise at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture thereof.
The inorganic ferroelectric material may be PZT.
The mixture may further comprise a suicide, a silicate or any other metal. The organic material may be a polymer ferroelectric material .
The polymer ferroelectric material may comprise at least one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano- polymer, and polymer or copolymer thereof.
The polymer ferroelectric material may be PVDF-TrFE.
The ferroelectric layer may be formed by heating and baking a mixed solution of an inorganic ferroelectric solution and an organic solution.
In accordance with a third aspect of the present invention, there is provided a method of manufacturing a field-effect transistor, the method comprising: forming source and drain regions on a substrate; forming a channel region between the source and drain regions; forming a lower electrode on the top of the channel region; forming a mixed solution of an inorganic ferroelectric material and an organic material; forming a ferroelectric layer by coating the mixed solution on the lower electrode and then baking and etching the resulting lower electrode; and forming an upper electrode on the ferroelectric layer.
In accordance with a fourth aspect of the present invention, there is provided a method of manufacturing a field-effect transistor, the method comprising: forming source and drain regions on a substrate; forming a channel region between the source and drain regions; forming a lower electrode on the top of the channel region; forming a mixed solution of an inorganic ferroelectric material and an organic material; forming a ferroelectric layer by coating the mixed solution on the lower electrode and then baking and etching the resulting lower electrode; and forming an upper electrode on the ferroelectric layer.
The inorganic ferroelectric material may comprise at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture thereof.
The inorganic ferroelectric material may be PZT. The mixed solution may further comprise a silicide, a silicate or any other metal. The organic material may be a polymer ferroelectric material .
The polymer ferroelectric material may comprise at least one selected from the group consisting of polyvinylidene fluoride (PVDF), PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano- polymer, and polymer or copolymer thereof.
The polymer ferroelectric material may be PVDF-TrFE. The mixed solution may comprises a PZT solution and a PVDF-TrFE solution. The PZT solution may be prepared by mixing a PZO solution and a PTO solution.
The PVDF-TrFE solution may be prepared by dissolving PVDF-TrFE powder in at least one solvent selected from the group consisting of C4H5O (THF), C4H8O (MEK), C3H6O (acetone), C3H7NO (DMF), and C2H6OS (DMSO).
The ferroelectric layer may be formed by a spin coating, ink-jet printing or screen printing method.
An etching process of the ferroelectric layer may be performed by a buffered oxide etching (BOE) method. The etching process of the ferroelectric layer may be performed by a two-step etching method using BOE and gold etchant .
The etching process of the ferroelectric layer may be performed by a reactive ion etching (RIE) method. The baking temperature may be below 200°C. [Description of Drawings]
FIG. 1 is a cross-sectional view showing a structure of a conventional metal-ferroelectric-semiconductor (MFS) type memory device;
FIG. 2 is a cross-sectional view showing a structure of a conventional metal-ferroelectric-insulator- semiconductor (MFIS) type memory device;
FIG. 3 is a diagram illustrating problems of the conventional structure shown in FIG. 2;
FIG. 4 is a cross-sectional view showing a structure of a metal-ferroelectric-metal-semiconductor (MFMS) field- effect transistor (FET) or an MFMS-ferroelectric memory device in accordance with a preferred embodiment of the present invention; and
FIGS. 5 to 9 are graphs showing capacitance-voltage characteristics of ferroelectric materials applied to the present invention.
[Mode for Invention]
Hereinafter, preferred embodiments in accordance with the present invention will be described with reference to the accompanying drawings. The preferred embodiments are provided so that those skilled in the art can sufficiently understand the present invention, but can be modified in
ll various forms and the scope of the present invention is not limited to the preferred embodiments .
FIG. 4 is a cross-sectional view showing a structure of a metal-ferroelectric-metal-semiconductor (MFMS) field- effect transistor (FET) or an MFMS-ferroelectric memory device in accordance with a preferred embodiment of the present invention, in which the same elements as those shown in FIGS. 1 and 2 have the same reference numerals.
The ferroelectric memory device in accordance with the present invention has a metal-ferroelectric-metal- semiconductor (MFMS) structure, differently from a conventional metal-ferroelectric-semiconductor (MFS) structure and a metal-ferroelectric-insulator-semiconductor (MFIS) structure. As shown in FIG. 4, source and drain regions 2 and 3 are formed in predetermined areas of a silicon substrate 1, and a lower electrode layer is formed on a channel region 4 between the source and drain regions 2 and 3 and used as a data electrode, for example. The data electrode 30 is provided to generate a polarization voltage in a ferroelectric layer 31 to be described later. The data electrode 30 may be formed of at least one selected from the group consisting of conductive metals including gold (Au), silver (Ag), aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTi.03) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS), conductive organic mixtures, conductive organic compounds, and conductive orcjanic multilayer materials.
The ferroelectric layer 31 is formed on the data electrode 30, and an upper electrode layer is formed on the ferroelectric layer 31 and used as a ground electrode 32, for example. Like the data electrode 30, the ground electrode 32 may be formed of at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt) , indium tin oxide (ITO), and strontiumtitanate (SrTiO3), conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3, 4-ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials. Especially, in a case where a plurality of memory cells is provided on the substrate 1, the data electrode 30 and the ground electrode 32 extend to intersect each other so as to select the memory cell arranged at the intersection using the data electrode 30 and the ground electrode 32.
Meanwhile, the ferroelectric layer 31 may be formed of a mixture of an inorganic ferroelectric material or a solid solution thereof and an organic material or an organic ferroelectric material.
There are known various materials showing ferroelectric characteristics. Such materials are broadly classified into inorganic materials and organic materials. The inorganic ferroelectric materials include ferroelectric oxides, ferroelectric fluorides such as BaMgF4 (BMF) , and ferroelectric semiconductors. The organic ferroelectric materials include polymer ferroelectric materials and the like.
The ferroelectric oxides include perovskite ferroelectric materials such as PbZrxTii-xO3 (PZT) , BaTiO3 and PBTiO3, pseudo-ilmenite ferroelectric materials such as LiNbO3 and LiTaO3, tungsten-bronze (TB) ferroelectric materials such as PbNb3Oe and Ba2NaNbSOi5, ferroelectric materials having a bismuth layer structure such as SrBi2Ta2Og (SBT), (Bi,La) 4Ti3Oi2 (BLT) and Bi4Ti3Oi2, pyrochlore ferroelectric materials such as La2Ti2O7, and ferroelectric materials such as RMnO3, Pb5Ge3On (PGO) and BiFeO3 (BFO) including a rare earth element (R) such as Y, Er, Ho, Tm, Yb and Lu. Moreover, the ferroelectric semiconductors include 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe.
Furthermore, the polymer ferroelectric materials include polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano-polymer, and polymer or copolymer thereof.
In general, the inorganic ferroelectric materials including the ferroelectric oxides, the ferroelectric fluorides and the ferroelectric semiconductors have dielectric constants greater than those of the organic ferroelectric materials. Accordingly, the generally proposed ferroelectric field-effect transistor (FET) or ferroelectric memory device employs the inorganic ferroelectric materials for forming the ferroelectric layer. According to the study by the present inventor, the inorganic ferroelectric materials are formed at higher temperatures, while their dielectric constants are high. However, the organic materials including the organic ferroelectric materials are formed at lower temperatures, while their dielectric constants are relatively low. Accordingly, when mixing the inorganic ferroelectric material with the organic material or the organic ferroelectric material, it is possible to obtain a ferroelectric material having a dielectric constant above a predetermined value and formed at a much lower temperature. In this case, methods of forming mixed solutions of the inorganic ferroelectric material and the organic material or the organic ferroelectric material are as follows : 1. Mixing an inorganic powder with an organic powder and dissolving the mixed powders in a solvent to form a mixed solution;
2. Dissolving an organic powder in an inorganic solution to form a mixed solution; 3. Dissolving an inorganic powder in an organic solution to form a mixed solution; and
4. Mixing an organic solution with an inorganic solution to form a mixed solution.
Moreover, the inorganic ferroelectric material and the organic material may be mixed with each other as follows:
1. Mixing an inorganic ferroelectric material with an organic material;
2. Mixing an inorganic ferroelectric material with an organic ferroelectric material; 3. Mixing a solid solution of an inorganic ferroelectric material with an organic material; 4. Mixing a solid solution of an inorganic ferroelectric material with an organic ferroelectric material; and 5. Mixing the aforementioned mixture with a suicide, a silicate or any other metal.
Of course, the above mixing methods are not limited to specific methods and any method that can appropriately mix the inorganic material with the organic material may be employed.
The organic materials mixed with the inorganic ferroelectric material include, a monomer, an oligomer, a polymer, and a copolymer. Preferably, an organic material having a high dielectric constant may be used. The organic materials having a high dielectric constant include polyvinylpyrrolidone (PVP) , polycarbonate (PC) , polyvinyl chloride (PVC) , polystyrene (PS) , epoxy, polymethylmethacrylate (PMMA) , polyimide (PI) , polyethylene (PE) , polyvinyl alcohol (PVA) , polyhexamethylene adipamide (nylon 66), polyetherketoneketone (PEKK), and the like.
Moreover, the organic materials include nonpolar organic materials, such as fluorinated para-xylene, fluoropolyarylether, fluorinated polyimide, polystyrene, poly (α-methyl styrene) , poly (α-vinylnaphthalene) , poly (vinyltoluene) , polyethylene, cis-polybutadiene, polypropylene, polyisoprene, poly (4-methyl-l-pentene) , poly (tetrafluoroethylene) , poly (chlorotrifluoroethylene) , poly (2-methyl-l, 3-butadiene) , poly (p-xylylene) , poly(α-α-α'- α ' -tetrafluoro-p-xylylene) , poly [1,1- (2-methyl propane) bis (4-phenyl) carbonate] , poly (cyclohexyl methacrylate) , poly (chlorostyrene) , poly (2, 6-dimethyl-l, 4- phenylene ether), polyisobutylene, poly (vinyl cyclohexane) , poly(arylene ether), and polyphenylene, or copolymers having a low dielectric constant, such as poly (ethylene/tetrafluoroethylene) , poly (ethylene/chlorotrifluoroethylene) , fluorinated ethylene/propylene copolymer, polystyrene-co-α-raethyl styrene, ethylene/ethyl acrylate copolymer, poly (styrene/10%butadiene) , poly (styrene/15%butadiene) , poly (styrene/2, 4-dimethylstyrene) , Cytop, Teflon AF, and polypropylene-co- L-butene .
Other organic semi-conducting materials that can be used in this invention include soluble compounds and soluble derivatives of compounds of the following list: conjugated hydrocarbon polymers such as polyacene, polyphenylene, poly (phenylene vinylene) , polyfluorene including oligomers of those conjugated hydrocarbon polymers; condensed aromatic hydrocarbons such as anthracene, tetracene, chrysene, pentacene, pyrene, perylene, coronene; oligomeric para substituted phenylenes such as p-quaterphenyl (p-4P) , p- quinquephenyl (p-5P) , p-sexiphenyl (p-6P) ; conjugated heterocyclic polymers such as poly (3-substituted thiophene) , poly (3, 4-bisubstituted thiophene), polybenzothiophene, polyisothianapthene, poly (N-substituted pyrrole), poly (3- substituted pyrrole), poly (3, 4-bisubstituted pyrrole), polyfuran, polypyridine, poly-1, 3, 4-oxadiazoles, polyisothianaphthene, poly (N-substituted aniline), poly (2- substituted aniline), poly (3-substituted aniline), poly (2, 3- bisubstituted aniline) , polyazulene, polypyrene; pyrazoline compounds; polyselenophene; polybenzofuran; polyindole; polypyridazine; benzidine compounds; stilbene compounds; triazines; substituted metallo- or metal-free porphines, phthalocyanines, fluorophthalocyanines, naphthalocyanines, or fluoronaphthalocyanines; Cεo and C70 fullerenes; N,N'- dialkyl, substituted dialkyl, diaryl or substituted diaryl- 1, 4, 5, 8-naphthalenetetracarboxylic diimide; N, N ' -dialkyl, substituted dialkyl, diaryl or substituted diaryl 3,4,9,10- perylenetetracarboxylicdiimide; bathophenanthroline; diphenoquinones; 1, 3, 4-oxadiazoles; 11,11,12,12- tetracyanonaptho-2, β-quinodimethane; α, α' -bis (dithieno [3, 2- b2 ' , 3 ' -d] thiophene) ; 2,8-dialkyl, substituted dialkyl, diaryl or substituted diaryl anthradithiophene; and 2,2'- bibenzo [ 1 , 2-b : 4 , 5-b ' ] dithiophene .
It is possible to appropriately set the mixture ratio of the inorganic material and the organic material. If the mixture ratio of the inorganic ferroelectric material is increased, the formation temperature is increased while the dielectric constant of the mixture is increased, whereas if the mixture ratio of the inorganic ferroelectric material is decreased, the formation temperature is lowered while the dielectric constant of the mixture is reduced.
The ferroelectric materials employed in the present invention have the following characteristics :
1. Since the ferroelectric layer is formed using a mixed solution of an inorganic material and an organic material, it is possible to easily form the ferroelectric layer by an ink-jet printing, spin coating or screen printing method;
2. Since the formation temperature of the ferroelectric layer is lowered to below about 200°C, it is possible to form the ferroelectric layer having excellent data retention characteristics on the silicon substrate; and
3. Since the formation temperature of the ferroelectric layer is lowered, it is possible to form the field-effect transistor or ferroelectric memory device on various kinds of substrates such as an organic material or paper instead of the existing silicon substrate. Meanwhile, FIGS. 5 to 9 are graphs showing polarization characteristics of ferroelectric layers formed of an inorganic ferroelectric material and an organic ferroelectric material such as PbZrxTii_xO3 (PZT) and PVDF- TrFE mixed in predetermined ratios.
Here, the ferroelectric layer was formed in such a manner that a PZT solution and a PVDF-TrFE solution were mixed in a predetermined ratio to form a mixed solution, the mixed solution was coated on a silicon wafer by a spin coating method, and the resulting silicon wafer was heated in the temperature range of 150 to 200 °C on a hot plate for a predetermined period of time. Moreover, the PZT solution was prepared by mixing a PZO solution and a PTO solution, in which the PZO solution was formed by mixing a zirconium propoxide solution with a mixed solution of a 2-methoxyethanol solution and a lead acetate trihydrate solution and the PTO solution was formed by mixing a titanium isopropoxide solution with the mixed solution of the 2-methoxyethanol solution and the lead acetate trihydrate solution.
The PVDF-TrFE solution was prepared by dissolving PVDF-TrFE powder in a solvent such as C4H5O (THF) , C4H8O (MEK), C3H6O (acetone), C3H7NO (DMF), and C2H6OS (DMSO).
An etching process of the ferroelectric layer was performed by a buffered oxide etching (BOE) , two-step etching using BOE and gold etchant, or reactive ion etching (RIE) method. FIG. 5 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:1, FIG. 6 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 2:1, FIG. 7 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 3:1, FIG. 8 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:2, and FIG. 9 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:3. In FIGS. 5A, 6A and 7A, the thickness of the ferroelectric layer was 50 ran; in FIGS. 5B, 6B, 7B, 8 and 9, the thickness of the ferroelectric layer was 75 ran; and in FIG. 5C, the thickness of the ferroelectric layer was 100 nm. Moreover, in FIGS. 5 to 9, the characteristic curves represented as A show the polarization characteristics in which the formation temperature of the ferroelectric layer was 190 °C, the characteristic curves represented as B show the polarization characteristics in which the formation temperature of the ferroelectric layer was 170 °C, and the characteristic curves represented as C show the polarization characteristics in which the formation temperature of the ferroelectric layer was 150°C.
Referring to FIGS. 5 to 9, in the case where the mixed ratio of the PZT and PVDF-TrFE was 1:1 or in the case where the mixed ratio of the PVDF-TrFE was greater than that of the PZT, generally good polarization characteristics were shown in the temperature range of 150 to 190°C, and the higher the mixed ratio of the PZT was, the better the polarization characteristics were shown at higher temperatures . Moreover, the higher the thickness of the ferroelectric layer, the lower the polarization value, i.e., the capacitance value, whereas the greater the size of the memory window. Especially, it was remarkable that, even in the case where the mixed ratio of the PZT and PVDF-TrFE was changed or in the case where the formation temperature was set to a temperature below about 200°C, excellent hysteresis characteristics were shown. As described above, since the formation temperature of the ferroelectric layer formed of the conventional inorganic ferroelectric material is higher than that of the ferroelectric layer formed in accordance with the present invention, various problems occur when forming the ferroelectric layer on the silicon substrate. Contrarily, when the mixture of the inorganic ferroelectric material and the organic material is used, it is possible to form the ferroelectric layer at a low temperature of below 200°C and excellent hysteresis characteristics are shown in a voltage range of -5 to 5 V.
In the structure of FIG. 4, the polarization is generated in the ferroelectric layer 31 by applying a predetermined voltage through the data electrode 30 in a state where the ground electrode 32 is connected to the ground. When the polarization is generated in the ferroelectric layer 31, a channel is formed or not in the channel region 4 between the source region 2 and the drain region 3 based on polarization characteristics. As a result, the current flow between the source region 2 and the drain region 3 is generated or cut off through the channel formed as described above, thus functioning as a transistor.
In a case where a memory cell or a memory cell array is formed using the above-described structure, a predetermined voltage is applied to a drain electrode 7 and, at the same time, it is determined whether the data stored in a corresponding memory cell is "1" or λλ0" based on whether or not the transistor is in a conductive state while grounding a source electrode 6. Accordingly, with the above-described one-transistor (IT) structure, it is possible to form one memory cell.
In the above-described structure, the ferroelectric layer 31 is not directly in contact with the silicon substrate 1 but connected thereto through the data electrode 30. Accordingly, it is possible to solve the problem that a transition layer of low quality is formed on the boundary between the ferroelectric layer 5 and the silicon substrate 1 during the formation of the ferroelectric layer 5.
Moreover, since a buffer layer is not provided between the ferroelectric layer 31 and the substrate 1 in the above structure, it is possible to solve the problem that data retention characteristics are degraded due to the deterioration of the polarization characteristics caused by a depolarization field, for example. Furthermore, since the mixture of the inorganic ferroelectric material and the organic material is used as the material for forming the ferroelectric material 31 in the above embodiment, it is possible to from the ferroelectric layer at a low temperature of below 200°C. The invention has been described in detail with reference to preferred embodiments thereof. However, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
For example, although the description has been given with respect to the case where the lower electrode layer 30 is used as the data electrode and the upper electrode layer 32 is used as the ground electrode, it is possible to use the lower electrode layer 30 as the ground electrode and the upper electrode layer 32 as the data electrode.
[industrial Applicability]
As described above, according to the present invention, it is possible to realize a ferroelectric memory device having a simple structure and excellent data retention characteristics and capable of forming a non-volatile memory cell with a IT structure.

Claims

[CLAIMS]
[Claim l]
A ferroelectric memory device including a substrate, a gate electrode, a drain electrode, a source electrode, a channel forming layer, and a ferroelectric layer, the ferroelectric memory device comprising: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material .
[Claim 2] The ferroelectric memory device of claim 1, wherein the lower electrode layer is a data electrode.
[Claim 3]
The ferroelectric memory device of claim 1, wherein the upper electrode layer is a ground electrode. [Claim 4]
The ferroelectric memory device of claim 1, wherein the lower and upper electrode layers comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiCb) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3, 4-ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
[Claim 5]
The ferroelectric memory device of claim 1, wherein the lower electrode layer and the upper electrode layer are arranged to extend in a direction where they intersect each other.
[Claim 6]
The ferroelectric memory device of claim 1, wherein the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode. [Claim 7]
The ferroelectric memory device of claim 1, wherein the inorganic ferroelectric material comprises at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture thereof,.
[Claim 8]
The ferroelectric memory device of claim 1, wherein the inorganic ferroelectric material is PZT.
[Claim 9]
The ferroelectric memory device of claim 1, wherein the mixture further comprises a suicide, a silicate or any other metal.
[Claim lθ]
The ferroelectric memory device of claim 1, wherein the organic material is a polymer ferroelectric material.
[Claim ll]
The ferroelectric memory device of claim 10, wherein the polymer ferroelectric material comprises at least one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano-polymer, and polymer or copolymer thereof.
[Claim 12] The ferroelectric memory device of claim 10, wherein the polymer ferroelectric material is PVDF-TrFE.
[Claim 13]
The ferroelectric memory device of claim 1, wherein the ferroelectric layer is formed by heating and baking a mixed solution of an inorganic ferroelectric solution and an organic solution.
[Claim 14] A ferroelectric memory device comprising: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material .
[Claim 15]
A field-effect transistor comprising: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
[Claim 16]
The field-effect transistor of claim 15, wherein the lower electrode layer is a data electrode.
[Claim 17]
The field-effect transistor of claim 15, wherein the upper electrode layer is a ground electrode.
[Claim 18] The field-effect transistor of claim 15, wherein the lower and upper electrode layers comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO3), conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3, 4-ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
[Claim 19]
The field-effect transistor of claim 15, wherein the lower electrode layer and the upper electrode layer are arranged to extend in a direction where they intersect each other.
[Claim 20] The field-effect transistor of claim 15, wherein the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode.
[Claim 2l] The field-effect transistor of claim 15, wherein the inorganic ferroelectric material comprises at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture thereof.,
[Claim 22]
The field-effect transistor of claim 15, wherein the inorganic ferroelectric material is PZT.
[Claim 23]
The field-effect transistor of claim 15, wherein the mixture further comprises a suicide, a silicate or any other metal .
[Claim 24]
The field-effect transistor of claim 15, wherein the organic material is a polymer ferroelectric material.
[Claim 25] The field-effect transistor of claim 24, wherein the polymer ferroelectric material comprises at least one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano-polymer, and polymer or copolymer thereof. [Claim 26]
The field-effect transistor of claim 24, wherein the polymer ferroelectric material is PVDF-TrFE.
[Claim 27]
The field-effect transistor of claim 15, wherein the ferroelectric layer is formed by heating and baking a mixed solution of an inorganic ferroelectric solution and an organic solution.
[Claim 28]
A field-effect transistor comprising: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material. [Claim 29]
A method of manufacturing a ferroelectric memory device, the method comprising: forming source and drain regions on a substrate; forming a channel region between the source and drain regions; forming a lower electrode on the top of the channel region; forming a mixed solution of an inorganic ferroelectric material and an organic material; forming a ferroelectric layer by coating the mixed solution on the lower electrode and then baking and etching the resulting lower electrode; and forming an upper electrode on the ferroelectric layer.
[Claim 30]
The method of claim 29, wherein the inorganic ferroelectric material comprises at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture thereof.
[Claim 31]
The method of claim 29, wherein the inorganic ferroelectric material is PZT. [Claim 32]
The method of claim 29, wherein the mixed solution further comprises a suicide, a silicate or any other metal.
[Claim 33]
The method of claim 29, wherein the organic material is a polymer ferroelectric material.
[Claim 34]
The method of claim 33, wherein the polymer ferroelectric material comprises at least one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd- numbered nylon, cyano-polymer, and polymer or copolymer thereof.
[Claim 35]
The method of claim 33, wherein the polymer ferroelectric material is PVDF-TrFE.
[Claim 36]
The method of claim 29, wherein the mixed solution comprises a PZT solution and a PVDF-TrFE solution. [Claim 37]
The method of claim 36, wherein the PZT solution is prepared by mixing a PZO solution and a PTO solution.
[Claim 38]
The method of claim 36, wherein the PVDF-TrFE solution is prepared by dissolving PVDF-TrFE powder in at least one solvent selected from the group consisting of C4H5O (THF) , C4H8O (MEK) , C3H6O ( acetone ) , C3H7NO ( DMF) , and C2H6OS ( DMSO) .
[Claim 39]
The method of claim 29, wherein the ferroelectric layer is formed by a spin coating method.
[Claim 40]
The method of claim 29, wherein the ferroelectric layer is formed by an ink-jet printing method.
[Claim 41] The method of claim 29, wherein the ferroelectric layer is formed by a screen printing method.
[Claim 42]
The method of claim 29, wherein an etching process of the ferroelectric layer is performed by a buffered oxide etching (BOE) method.
[Claim 43]
The method of claim 29, wherein the etching process of the ferroelectric layer is performed by a two-step etching method using BOE and gold etchant.
[Claim 44]
The method of claim 29, wherein the etching process of the ferroelectric layer is performed by a reactive ion etching (RIE) method.
[Claim 45]
The method of claim 29, wherein the baking temperature is below 200°C.
[Claim 46]
A method of manufacturing a field-effect transistor, the method comprising: forming source and drain regions on a substrate; forming a channel region between the source and drain regions; forming a lower electrode on the top of the channel region; forming a mixed solution of an inorganic ferroelectric material and an organic material; forming a ferroelectric layer by coating the mixed solution on the lower electrode and then baking and etching the resulting lower electrode; and forming an upper electrode on the ferroelectric layer.
PCT/KR2007/002882 2006-12-29 2007-06-14 Fet, ferroelectric memory device, and methods of manufacturing the same WO2008082044A1 (en)

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KR20060138737 2006-12-29
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US5942776A (en) * 1997-03-07 1999-08-24 Sharp Laboratories Of America, Inc. Shallow junction ferroelectric memory cell and method of making the same
US6236076B1 (en) * 1999-04-29 2001-05-22 Symetrix Corporation Ferroelectric field effect transistors for nonvolatile memory applications having functional gradient material

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