KR100876135B1 - Memory device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a memory device and a method for manufacturing the same, which have a simple structure that does not use a switching element such as a transistor and enable nonvolatile storage of data. The memory device according to the present invention includes a substrate 70, a plurality of lower electrodes 71 formed in parallel on the substrate 70, a ferroelectric layer 72 formed on the lower electrode 71, and The ferroelectric layer 72 includes a plurality of upper electrodes 73 formed in a direction perpendicular to the lower electrode 71 while being parallel to each other. The ferroelectric layer 72 is formed of an inorganic ferroelectric material and an organic material. It is characterized by consisting of a mixture.

Description

Memory device and method of manufacturing the same

1 is an equivalent circuit diagram of a memory device having a 1C structure according to the present invention.

2 to 6 is a characteristic diagram showing the capacity characteristics according to the voltage of the ferroelectric material applied to the present invention.

Fig. 7 is a diagram showing the configuration of the memory device according to the first embodiment of the present invention.

FIG. 8 is a view showing a modification of the embodiment shown in FIG. 7. FIG.

9 is a structural diagram showing the structure of a memory device according to the second embodiment of the present invention;

10 and 11 are structural diagrams showing a modification of the embodiment shown in FIG. 9.

*** Brief description of the main parts of the drawing ***

70: substrate, 71: lower electrode,

72: ferroelectric layer, 73: upper electrode.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device capable of electrically recording and reading information. In particular, the present invention relates to a memory device having a simple structure that does not use a switching element such as a transistor and that enables nonvolatile storage of data. It relates to a manufacturing method.

Currently, various kinds of memory devices using semiconductors are used. These memory devices include ROMs such as EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable PROM), Flash ROM (Flash ROM), SRAM (Static Random Access Memory), DRAM (Dynamic RAM), and FRAM (Ferroelectric RAM). Various things are used including RAM, etc.

All semiconductor memory devices currently used are basically provided with a switching element such as a transistor and a storage element such as a capacitor. These memory devices perform writing, erasing and reading of data through an operation of storing and reading data values in a storage element through a switching element.

Therefore, in the conventional semiconductor memory device, as the switching elements and the capacitors are formed on the wafer, many manufacturing processes are required, and there is a disadvantage that it is difficult to realize a certain degree of integration.

Accordingly, an object of the present invention is to provide a memory device and a method of manufacturing the same, which have been created in view of the above circumstances and are capable of nonvolatile storage and reading of data in a simple structure without a separate switching device or a storage device. There is this.

A memory device according to a first aspect of the present invention for realizing the above object is provided on a substrate, a lower electrode made of a conductive material, a ferroelectric layer provided on the lower electrode, and a ferroelectric layer provided on the substrate. And an upper electrode made of a conductive material, wherein the ferroelectric layer is made of a mixture of an inorganic ferroelectric material and an organic material.

In addition, the memory device according to the second aspect of the present invention includes a substrate, a lower electrode formed on the substrate and a conductive material, a ferroelectric layer provided on the lower electrode, and a conductive material provided on the ferroelectric layer. Comprising an upper electrode made of a, characterized in that the ferroelectric layer is composed of a mixture of an organic solution and a solid solution of an inorganic ferroelectric material.

In addition, a memory device according to a third aspect of the present invention includes a substrate, a plurality of lower electrodes formed on the substrate in parallel with each other, a ferroelectric layer formed on the lower electrode, and the lower portion in parallel with each other on the ferroelectric layer. It comprises a plurality of upper electrodes formed in a direction orthogonal to the electrode, characterized in that the ferroelectric layer is composed of a mixture of inorganic ferroelectric material and organic material.

In addition, the memory device according to the fourth aspect of the present invention includes a substrate, a plurality of lower electrodes formed on the substrate in parallel with each other, a ferroelectric layer formed on the lower electrode, and the lower portion in parallel with each other on the ferroelectric layer. It comprises a plurality of upper electrodes formed in a direction orthogonal to the electrode, characterized in that the ferroelectric layer is composed of a mixture of an organic solution and a solid solution of an inorganic ferroelectric material.

In addition, the substrate is characterized in that composed of one of the Si wafer, Ge wafer, paper, paper coated with parylene, organic material.

In addition, the organic material is polyimide (PI), polycarbonate (PC), polyether sulfone (PES), polyether ether ketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), polychlorinated Vinyl (PVC), Polyethylene (PE), Ethylene Copolymer, Polypropylene (PP), Propylene Copolymer, Poly (4-methyl-1-pentene) (TPX), Polyarylate (PAR), Polyacetal (POM) , Polyphenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), polyvinyl acetal, polystyrene (PS), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorine resin, phenol resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP), epoxy resin ( EP), diallyl phthalate resin (DAP), polyurethane (PUR), polyamide (PA), silicone resin (SI) or mixtures and compounds thereof Characterized in that it comprises a.

The inorganic ferroelectric material may include at least one of an oxide ferroelectric, a fluoride ferroelectric, a ferroelectric semiconductor, and a mixture of these inorganic materials.

In addition, the inorganic ferroelectric material is characterized in that the PZT.

In addition, the mixture is characterized in that the silicate, silicate or other metal is further mixed.

In addition, the organic material is characterized in that the polymer ferroelectric.

In addition, the polymeric ferroelectric includes at least one or more of polyvinylidene fluoride (PVDF), a polymer, a copolymer, or a terpolymer comprising the PVDF, an odd number of nylon, a cyano polymer, and polymers or copolymers thereof. Characterized in that.

In addition, the polymer ferroelectric is characterized in that the PVDF-TrFE.

In addition, the ferroelectric layer is characterized in that it is produced by heating and baking a mixed solution of the inorganic ferroelectric material and the organic solution.

In addition, a memory device according to a fifth aspect of the present invention includes a first memory cell formed on a substrate and a second memory cell formed on the first memory cell, wherein the first and second memory cells And a lower electrode made of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode made of a conductive material and provided on the ferroelectric layer. The ferroelectric layer is a mixture of an inorganic ferroelectric material and an organic material. It is characterized in that the configuration.

In addition, a memory device according to a sixth aspect of the present invention includes a first memory cell formed on a substrate and a second memory cell formed on the first memory cell, wherein the first and second memory cells And a lower electrode made of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode made of a conductive material and provided on the ferroelectric layer, wherein the ferroelectric layer comprises a solid solution of an inorganic ferroelectric material and an organic material. It is characterized by consisting of a mixture.

In addition, a memory device according to a seventh aspect of the present invention includes a first memory cell formed on a substrate and a second memory cell formed on the first memory cell, wherein the first and second memory cells A plurality of lower electrodes formed on the substrate in parallel to each other, a ferroelectric layer formed on the lower electrode, and a plurality of upper electrodes formed on the ferroelectric layer in a direction orthogonal to the lower electrodes. The ferroelectric layer is characterized by consisting of a mixture of inorganic ferroelectric material and organic material.

In addition, a memory device according to an eighth aspect of the present invention includes a first memory cell formed on a substrate and a second memory cell formed on the first memory cell, wherein the first and second memory cells A plurality of lower electrodes formed on the substrate in parallel to each other, a ferroelectric layer formed on the lower electrode, and a plurality of upper electrodes formed on the ferroelectric layer in a direction orthogonal to the lower electrodes. The ferroelectric layer is characterized in that the mixture of the solid solution of the inorganic ferroelectric material and the organic material.

In addition, a memory device according to a ninth aspect of the present invention includes a first memory cell formed on a substrate and a second memory cell formed on the first memory cell, wherein the first and second memory cells And a lower electrode made of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode made of a conductive material and provided on the ferroelectric layer. The ferroelectric layer is a mixture of an inorganic ferroelectric material and an organic material. In addition, the ferroelectric layers of the first memory cell and the second memory cell are made of different materials.

In addition, a memory device according to a tenth aspect of the present invention includes a first memory cell formed on a substrate and a second memory cell formed on the first memory cell, wherein the first and second memory cells A plurality of lower electrodes formed on the substrate in parallel to each other, a ferroelectric layer formed on the lower electrode, and a plurality of upper electrodes formed on the ferroelectric layer in a direction orthogonal to the lower electrodes. The ferroelectric layer is composed of a mixture of inorganic ferroelectric materials and organic materials, and the ferroelectric layers of the first memory cell and the second memory cell are composed of different materials.

In addition, an insulating layer is formed between the first memory cell and the second memory cell.

In addition, the upper electrode of the first memory cell and the lower electrode of the second memory cell are characterized in that the ground electrode.

The ground electrode of the first memory cell and the second memory cell may be integrally formed.

The upper electrode of the first memory cell and the lower electrode of the second memory cell may be data electrodes.

In addition, a method of manufacturing a memory device according to an eleventh aspect of the present invention includes a lower electrode forming step of forming a lower electrode on a substrate, and a mixture of an inorganic ferroelectric material and an organic material on the entire surface of the substrate on which the lower electrode is formed. A ferroelectric layer forming step of forming a ferroelectric layer, and an upper electrode forming step of forming an upper electrode on the ferroelectric layer is characterized in that it comprises a.

In addition, the organic material is characterized in that the ferroelectric organic material.

The ferroelectric layer may be formed by applying a mixed solution of an inorganic ferroelectric material and an organic solution on a substrate to form a ferroelectric film, and heating and baking the ferroelectric film.

In addition, the mixed solution is characterized in that the mixed solution of the PZT solution and PVDF-TrFE solution.

In addition, the PZT solution is characterized in that it is produced by mixing the PZO solution and PTO solution.

In addition, the PVDF-TrFE solution is PVDF-TrFE powder THF (C ₄ H ₅ O), MEK (C ₄ H ₈ O), acetone (C ₃ H ₆ O), DMF (C ₃ H ₇ NO), DMSO It is characterized by producing by dissolving in at least one of (C ₂ H ₆ OS).

In addition, the ferroelectric film is formed by a spin coating method.

In addition, the ferroelectric film is formed by an inkjet method.

In addition, the ferroelectric film is formed by screen printing.

In addition, the ferroelectric layer is characterized in that it further comprises the step of etching to remove the remaining portion other than the cross region of the lower electrode and the upper electrode.

In addition, the etching of the ferroelectric layer is characterized in that it is carried out through the BOE.

In addition, the etching of the ferroelectric layer is characterized in that it is carried out through a two-step etching using BOE and gold etchant.

The ferroelectric layer is etched through the RIE method.

Moreover, the said baking temperature is 200 degrees or less, It is characterized by the above-mentioned.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

First, the basic concept of the present invention will be described.

Generally, a memory device is for storing digital data. Thus, if any structure can store data " 0 " or " 1 ", and such stored data can be read and used when necessary, such a structure can be usefully used as a memory device.

Currently, generally known ferroelectric materials have a constant polarization value according to an externally applied voltage, and the polarization value is maintained for a predetermined time even when the external power source is cut off. According to the present inventors, when the above polarization characteristic is used, a memory device having a 1C (one-capacitor) structure can be implemented as shown in FIG. 1. Of course, a ferroelectric material is used as the ferroelectric layer 13 between the lower electrode 11 and the upper electrode 12 in the structure of FIG.

At present, an attempt has been made to implement a 1T (one-transistor) structure memory device using ferroelectric materials. However, in the case of forming a transistor in a silicon substrate or the like, first, a drain and source region and a channel region are formed on the substrate, a gate layer is formed on the channel region, and then an electrode is formed on the drain and source region and the gate layer. Therefore, a number of manufacturing processes are required. However, the formation of the capacitor can be implemented through a simple manufacturing process since the dielectric layer is formed on the lower electrode and then the upper electrode is formed thereon. In addition, since the capacitor structure has a much smaller occupied space than the transistor structure, a large number of devices can be formed in the same space.

In addition, unlike the conventional memory structure, the structure of FIG. 1 eliminates the need to form drain, source, and channel regions for the transistor configuration, thereby eliminating the need for a substrate such as silicon. In the structure of FIG. 1, since the memory device is implemented only by forming the conductive thin films and the ferroelectric thin films for the upper and lower electrodes, a substrate of a special material is not required to implement the memory device. Therefore, the manufacturing price of the memory device can be drastically lowered, and the memory device can be implemented on a material having flexibility such as general resin or paper, so that the memory device can be folded or rolled up. do.

However, appropriate ferroelectric materials are required to apply the above concepts.

Currently, various materials are known as ferroelectric properties. These substances are largely divided into inorganic and organic substances. Examples of the inorganic ferroelectric include oxide ferroelectrics, fluoride ferroelectrics such as BMF (BaMgF ₄ ), ferroelectric semiconductors, and the like, and polymer ferroelectrics as organic ferroelectrics.

As the oxide ferroelectric, for example, Pseudo-ilmenite ferroelectric such as Perovskite ferroelectric such as PZT (PbZr _x Ti _1-x O ₃ ), BaTiO ₃ , PbTiO ₃ , LiNbO ₃ , LiTaO _3, and the like , Tungsten-bronze (TB) ferroelectrics such as PbNb ₃ O ₆ , Ba ₂ NaNb ₅ O ₁₅ , SBT (SrBi ₂ Ta ₂ O ₉ ), BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ), Bi ₄ Ti ₃ Ferroelectrics of bismuth layer structure such as O ₁₂ and Pyrochlore ferroelectrics such as La ₂ Ti ₂ O ₇ and solid solutions of these ferroelectrics, as well as Y, Er, Ho, Tm, Yb, Lu, etc. RMnO ₃ , PGO (Pb ₅ Ge ₃ O ₁₁ ), and BFO (BiFeO ₃ ) containing a rare earth element (R).

Examples of the ferroelectric semiconductors include Group 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe, and CdFeSe.

As the polymer ferroelectric, for example, polyvinylidene fluoride (PVDF), a polymer, a copolymer, or a terpolymer containing the PVDF is included. In addition, an odd number of nylons, cyano polymers, polymers thereof and air Coalescing and the like.

In general, inorganic ferroelectrics such as oxide ferroelectrics, fluoride ferroelectrics, and ferroelectric semiconductors have a higher dielectric constant than organic ferroelectrics. Therefore, in the case of ferroelectric field effect transistors and ferroelectric memories, which are currently generally proposed, an inorganic ferroelectric is employed as a material of the ferroelectric layer.

However, in the case of the inorganic ferroelectric described above, a high temperature treatment of, for example, 500 degrees or more is required when forming it on a substrate. In the case where high temperature treatment is required to form the ferroelectric layer or the ferroelectric thin film, there is a limitation in using a flexible material such as general resin or paper. That is, the material that can be used as the substrate of the memory device is limited.

In the present invention, a mixture of an inorganic ferroelectric material and an organic or organic ferroelectric material is used as a material of the ferroelectric layer in FIG. 1.

According to the inventors' research, the inorganic ferroelectric material has a high dielectric constant while its formation temperature is high. In addition, the organic material including the organic ferroelectric material has a low dielectric constant while its formation temperature is very low. Therefore, when the inorganic ferroelectric material and the organic or organic ferroelectric material are mixed, the ferroelectric material having a very high dielectric constant and having a very low formation temperature can be obtained.

Herein, the following method may be used as a method of mixing an inorganic ferroelectric material and an organic or organic ferroelectric material.

1. After mixing inorganic powder and organic powder, dissolve it in solvent to produce mixed solution.

2. Dissolve organic powder in mineral solution to produce mixed solution.

3. Dissolve the inorganic powder in the organic solution to produce a mixed solution.

4. Mix the organic solution with the inorganic solution to form a mixed solution.

In addition, in the method of mixing the inorganic ferroelectric material and the organic material, it is possible to adopt the following method.

1. Mix ferroelectric minerals and organics.

2. Mix ferroelectric minerals with ferroelectric organics.

3. Mix solid solution of organic fertilizer with organic material.

4. Mix solid solution of ferroelectric mineral with ferroelectric organic material.

5. Mixing silicide, silicate or other metals into the mixture according to the first to fourth manners.

Of course, the mixing method and method of the said inorganic substance and organic substance are not limited to a specific thing, Any arbitrary method which can mix an inorganic substance and an organic substance suitably can be employ | adopted here.

In addition, as the organic material mixed with the ferroelectric inorganic material, a general monomer, oligomer, polymer, copolymer, preferably an organic material having a high dielectric constant may be used.

These materials include, for example, polyvinyl pyrrolidone (PVP), polycarbonate (PC), polyvinyl chloride (PVC), polystyrene (PS), epoxy (epoxy), polymethyl methacrylate (PMMA), polyimide (PE), poly (ethylene) (PE), and PVA ( polyvinyl alcohol), nylon 66 (polyhezamethylene adipamide), and PEKK (polytherketoneketone).

In addition, as the organic material, fluorinated para-xylene, fluoropolyarylether, fluorinated polyimide, polystyrene, poly (α-methyl styrene) (poly (α) -methyl styrene), poly (α-vinylnaphthalene), poly (vinyltoluene), polyethylene, cis-polybutadiene, poly Polypropylene, polyisoprene, poly (4-methyl-1-pentene), poly (tetrafluoroethylene), poly (Chlorotrifluoroethylene) (poly (chlorotrifluoroethylene), poly (2-methyl-1,3-butadiene) (poly (2-methyl-1,3-butadiene)), poly (p-xylylene) (poly (p-xylylene)), poly (α-α-α'-α'-tetrafluoro-p-xylylene) (poly (α-α-α'-α'-tetrafluoro-p-xylylene)), Poly [1,1- (2-methyl propane) bis (4-phenyl) carbonate] (poly [1,1 -(2-methyl propane) bis (4-phenyl) carbonate]), poly (cyclohexyl methacrylate), poly (chlorostyrene), poly (2,6) Dimethyl-1,4-phenylene ether) (poly (2,6-dimethyl-1,4-phenylene ether)), polyisobutylene, poly (vinyl cyclohexane) , Nonpolar organic materials such as poly (arylene ether) and polyphenylene, poly (ethylene / tetrafluoroethylene), poly (ethylene / chloro Poly (ethylene / chlorotrifluoroethylene), fluorinated ethylene / propylene copolymer, polystyrene-co-α-methyl styrene, ethylene / ethyl Ethylene / ethyl acrylate copolymer, poly (styrene / 10% butadiene) (poly (styrene / 10% butadiene), poly (styrene / 15% butadiene) (po ly (styrene / 15% butadiene), poly (styrene / 2,4-dimethylstyrene) (poly (styrene / 2,4-dimethylstyrene), Cytop, Teflon AF, polypropylene-co-1-butene (polypropylene-co- Low dielectric constant copolymers such as 1-butene) and the like can be used.

And other conjugated hydrocarbon polymers such as polyacene, polyphenylene, poly (phenylene vinylene), polyfluorene, and oligomers of such conjugated hydrocarbons. ; Condensed aromatic hydrocarbons such as anthracene, tetratracene, chrysene, pentacene, pyrene, perylene and coronene; oligomeric para substitutions such as p-quaterphenyl (p-4P), p-quinquephenyl (p-5P), p-sexiphenyl (p-6P) Oligomeric para substituted phenylenes; Poly (3-substituted thiophene), poly (3,4-bisubstituted thiophene), polybenzothiophene, poly Isothianaphthene, poly (N-substituted pyrrole), poly (3-substituted pyrrole), poly (3,4-disubstituted pyrrole) ) (poly (3,4-bisubstituted pyrrole)), polyfuran, polypyridine, poly-1,3,4-oxadiazoles, polyiso Polyisothianaphthene, poly (N-substituted aniline), poly (2-substituted aniline), poly (2-substituted aniline), poly (3-substituted aniline) (poly Conjugated heterocyclic polymers such as (3-substituted aniline), poly (2,3-bisubstituted aniline), polyazulene, polypyrene; Pyrazoline compounds; Polyselenophene; Polybenzofuran; Polyindole; Polypyridazine; Benzidine compounds; Stilbene compounds; Triazines; Substituted metallo- or metal-free porphines, phthalocyanines, fluorophthalocyanines, naphthalocyanines or fluoronaphthalocyanines; C ₆₀ and C ₇₀ fullerenes; N, N'-dialkyl, substituted dialkyl, diaryl or substituted diaryl-1,4,5,8-naphthalenetetracarboxylic diimide (N, N'-dialkyl, substituted dialkyl, diaryl or substituted diaryl-1,4,5,8-naphthalenetetracarboxylic diimide) and fluorinated derivatives; N, N'-dialkyl, substituted dialkyl, diaryl or substituted diaryl 3,4,9,10-perylenetetracarboxylic diimide (N, N'-dialkyl, substituted dialkyl, diaryl or substituted diaryl 3,4,9,10-perylenetetracarboxylic diimide); Bathophenanthroline; Diphenoquinones; 1,3,4-oxadiazoles (1,3,4-oxadiazoles); 11,11,12,12-tetracyanonaphtho-2,6-quinodimethane (11,11,12,12-tetracyanonaptho-2,6-quinodimethane); α, α'-bis (dithieno [3,2-b2 ', 3'-d] thiophene) (α, α'-bis (dithieno [3,2-b2', 3'-d] thiophene) ); 2,8-dialkyl, substituted dialkyl, diaryl or substituted diaryl anthrathiothiophenes (2,8-dialkyl, substituted dialkyl, diaryl or substituted diaryl anthradithiophene); Organic groups such as 2,2'-bibenzo [1,2-b: 4,5-b '] dithiophene (2,2'-bibenzo [1,2-b: 4,5-b'] dithiophene) Semi-conducting materials or their compounds, oligomers and compound derivatives can be used.

In the above manner, the mixing ratio of the inorganic material and the organic material can be appropriately set as necessary. If the mixing ratio of the ferroelectric inorganic material is increased, the dielectric constant of the mixture is increased while the formation temperature is high, and if the mixing ratio of the ferroelectric inorganic material is low, the dielectric constant of the mixture is low while the formation temperature is low.

The ferroelectric material according to the present invention has the following characteristics.

1. Since the ferroelectric layer is formed using a mixed solution of an inorganic material and an organic material, the ferroelectric layer can be easily formed using inkjet, spin coating, or screen printing.

2. Since the formation temperature of the ferroelectric layer is lowered, the ferroelectric memory can be formed on various kinds of substrates such as organic material or paper instead of the existing silicon substrate.

Meanwhile, FIGS. 2 to 6 illustrate ferroelectric layers formed by mixing inorganic ferroelectric materials and organic ferroelectric materials, such as PZT (PbZr _x Ti _1-x O ₃ ) and PVDF-TrFE, at a predetermined ratio. It is a graph which measured the polarization characteristic after that.

Here, the ferroelectric layer is mixed with the PZT solution and PVDF-TrFE solution in a constant ratio to generate a mixed solution, the mixed solution is applied on the silicon wafer by spin coating method, and then the silicon wafer is fixed on the hot plate for a predetermined time. It was formed by heating to about 150 ~ 200 degrees.

In addition, the PZT solution, for example, by mixing a zirconium propoxide solution with a mixed solution of 2-methoxyethanol solution and lead acetate trihydrate solution to produce a PZO solution Then, a titanium isopropoxide solution was mixed with a mixed solution of 2-methoxyethanol solution and lead acetate trihydrate solution to generate a PTO solution, and then a PZO solution and a PTO solution were mixed.

In addition, the PVDF-TrFE solution may contain PVDF-TrFE powders such as THF (C ₄ H ₅ O), MEK (C ₄ H ₈ O), Acetone (C ₃ H ₆ O), DMF (C ₃ H ₇ NO) It was produced by dissolving in a solvent such as (C ₂ H ₆ OS).

2 to 6, the mixing ratio of PZT and PVDF-TrFE is 1: 1, the mixing ratio of PZT and PVDF-TrFE is 2: 1, and the mixing ratio of PZT and PVDF-TrFE is 3: 1. FIG. 5 shows polarization characteristics when the mixing ratio of PZT and PVDF-TrFE is 1: 2 and FIG. 6 is 1: 3.

2A, 3A and 4A show the film thickness of the ferroelectric layer 50 nm, FIGS. 2B, 3B, 4B, 5 and 6 show the film thickness of the ferroelectric layer 75 nm, and FIG. 2C shows the ferroelectric layer. The case where the film thickness is 100 nm is shown.

2 to 6, the characteristic graph denoted by A is 190 degrees for forming the ferroelectric layer, and the B is for forming the ferroelectric layer at 170 degrees and the C is 150 for forming the ferroelectric layer. The case is shown.

2 to 6, when the mixing ratio of PZT and PVDF-TrFE is 1: 1 or the mixing ratio of PVDF-TrFE to PZT is larger, generally good polarization characteristics are shown at a forming temperature of 150 to 190 degrees. The higher the mixing ratio of PZT, the better the polarization characteristics at higher formation temperatures.

In addition, as the thickness of the ferroelectric layer is increased, the polarization value, that is, the capacitance value is lowered, while the size of the memory window is increased.

In particular, it is noteworthy that even when the mixing ratio of PZT and PVDF-TrFE is changed or the formation temperature is set to a temperature of 200 degrees or less, very good hysteresis characteristics are exhibited.

FIG. 7 is a structural diagram illustrating a structure of a memory device according to a first embodiment of the present invention in which the memory device shown in FIG. 1 is implemented.

In FIG. 7, a plurality of lower electrodes 71 and upper electrodes 73 are arranged to intersect on the substrate 70, and a ferroelectric layer having polarization characteristics at the intersections of the lower electrodes 71 and the upper electrodes 73. 72 is provided.

Here, the substrate 70 may be formed of an organic material such as a conventional Si, Ge wafer, paper, a paper coated with a coding material such as parylene, or a plastic having flexibility. In addition, the organic materials usable here include polyimide (PI), polycarbonate (PC), polyether sulfone (PES), polyether ether ketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), Polyvinyl chloride (PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4-methyl-1-pentene) (TPX), polyarylate (PAR), polyacetal ( POM), polyphenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), polyvinyl acetal , Polystyrene (PS), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorine resin, phenol resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP), epoxy Resin (EP), diallyl phthalate resin (DAP), polyurethane (PUR), polyamide (PA), silicone resin (SI) or mixtures and combinations thereof The can be used.

Of course, the substrate 70 is not limited to a specific one, and any material may be used.

As the lower electrode 71 and the upper electrode 73, for example, gold, silver, aluminum, platinum, indium tin compound (ITO), strontium titanate compound (SrTiO ₃ ), other conductive metal oxides and alloys thereof And all conductive metals and metals, including compounds or mixtures of compounds such as polyaniline, poly (3,4-ethylenedioxythiophene) / polystyrenesulfonate (PEDOT: PSS), compounds or multilayers, etc., based on conductive polymers. Oxides and conductive organics are used.

As the ferroelectric layer 72, a material in which an organic ferroelectric material is mixed with an inorganic ferroelectric or a solid body thereof, or a material in which silicide, silicate or another metal is mixed with these mixtures is used.

Although not specifically shown in the drawings, the lower and upper electrodes 71 and 73 read a polarization value of the driving device for driving each electrode and the ferroelectric layer 72 as in the conventional memory device. The sense amplifier will be electrically coupled.

In the case of manufacturing the above-described memory device, the lower electrode 71 is formed on the substrate 70 using a conventional method.

Then, the ferroelectric material solution according to the present invention is entirely applied onto the structure through spin coating, inkjet printing, or screen printing, and then, for example, it is baked at a temperature of 200 degrees or less to form a ferroelectric film.

Subsequently, for example, buffered oxide etching (BOE), two-step etching using BOE and gold etchant, or reactive ion etching (RIE) are performed to cross the area between the lower electrode 71 and the upper electrode 73. The ferroelectric layer 72 is formed by removing other portions of the ferroelectric film.

Then, the upper electrode 73 is formed on the structure through a conventional method.

8 shows a modified example of the embodiment shown in FIG. 7, in which FIG. 8A shows a plan view and FIG. 8B shows a cross sectional view thereof. In the embodiment shown in FIG. 7, the ferroelectric layer 72 is formed at the intersection of the lower electrode 71 and the upper electrode 73 constituting the capacitor. In the present embodiment, the lower electrode 81 is disposed in the transverse direction. The ferroelectric layer 82 is applied on the entire surface area of the Ns, and a plurality of upper electrodes 83 are formed on the ferroelectric layer 82 in the longitudinal direction orthogonal to the lower electrode 81.

In the present embodiment, after the lower electrode 81 is formed on the substrate 80, the ferroelectric layer 82 is formed on the entire surface, so that the process of forming the ferroelectric layer 82 is greatly simplified. In addition, in this embodiment, since only the portion where the lower electrode 81 and the upper electrode 83 cross each other functions as one capacitor, the operation is substantially the same as the embodiment shown in FIG.

In addition, in the embodiment of FIG. 8, the material of the substrate 80, the lower and upper electrodes 81 and 83, and the ferroelectric layer 82 are substantially the same as the embodiment of FIG. 7, and thus a detailed description thereof will be omitted.

The memory device according to the embodiment has a 1C structure. Therefore, the structure is simpler than that of a memory structure having a transistor and a capacitor or a memory having a 1T structure, and a large capacity memory device can be formed in the same area.

In addition, the memory device according to the above embodiment does not form a transistor requiring a complicated process for implementing the memory device, thereby greatly simplifying the manufacturing process of the memory device.

9 is a structural diagram illustrating a structure of a memory device according to a second embodiment of the present invention. In FIG. 9, a plurality of first memory cells 110 are formed on the substrate 100, and an insulating layer 120, such as polyimide (PI), is formed while covering the first memory cells 110 as a whole. do. A plurality of second memory cells 130 is formed on the insulating layer 120.

7 and 8, the substrate 100 may be formed of Si, Ge wafers, organic materials such as paper coated with a coding material such as parylene, or plastic having flexibility.

The first and second memory cells 110 and 130 have the same structure as those of FIGS. 7 and 8. That is, the first and second memory cells 110 and 130 are arranged to cross the lower electrodes 111 and 131 and the upper electrodes 113 and 133, and ferroelectric layers 112 and 132 are formed between the electrodes. do. In the equivalent circuit diagram shown in FIG. 1, when the electrode 11 coupled to the ground side is a ground electrode and the electrode 13 coupled to the data output side is a data electrode, the lower electrode ( 111 and 131 are ground electrodes, and upper electrodes 113 and 133 correspond to data electrodes. Hereinafter, the upper and lower electrodes are called data electrodes and ground electrodes according to their functions.

Meanwhile, the ferroelectric layers 112 and 132 formed between the ground electrodes 111 and 131 and the data electrodes 113 and 133 may have the ground electrodes 111 and 131 and the data electrodes 113 and 133 as shown in FIG. 7. Is limited to only the intersection region of the < RTI ID = 0.0 >), or as shown in FIG. 8, covering the ground electrodes 111, 131 as a whole.

In addition, the first memory cell 110 allows the ferroelectric layer 112 to be formed only at the crossing regions of the positive electrodes 111 and 131, and the second memory cell 130 applies the ground electrode 131 as a whole. 132 is formed, or vice versa, the first memory cell 110 is formed such that the ferroelectric layer 112 is applied to the ground electrode 111 as a whole, so that the second memory cell 130 is formed of both electrodes 131 and 133. It is also possible to form the ferroelectric layer 132 only at the intersection region.

In particular, the ferroelectric layers 112 and 132 are composed of a mixture of inorganic ferroelectric materials and organic materials as described above. Of course, even in this case, the material of the ferroelectric layer 112 and the ferroelectric layer 132 may be appropriately used in some cases without having to be the same. For example, the ferroelectric layer 112 may be composed of a mixture of inorganic ferroelectric materials and organic materials, and the ferroelectric layer 132 may be composed of a mixture of inorganic ferroelectric materials and organic ferroelectric materials.

That is, the ferroelectric layers 112 and 132 may be formed using any kind of ferroelectric mixture material provided in the present invention.

Incidentally, in the present embodiment, the configuration of the memory cells in two layers has been described, but the stacking of the memory cells can be made in a plurality of layers or more in the same manner.

In the above-described embodiment, since the memory cells 110 and 130 are stacked by the insulating layer 120, a large amount of memory cells can be configured in the same area.

In the above-described embodiment, since the data electrode 113 of the first memory cell 110 and the ground electrode 131 of the second memory cell 130 are coupled through the insulating layer 120, the data electrode ( 113 and the ground electrode 131 form a capacitor. Accordingly, such a capacitor may cause an error in data writing and reading of the first or second memory cells 110 and 130.

FIG. 10 is a structural diagram illustrating a structure of a memory device according to a modified embodiment of the example illustrated in FIG. 9. In addition, in FIG. 10, the same reference numeral is attached | subjected to the substantially same part as FIG. 9 mentioned above, and the detailed description is abbreviate | omitted.

In FIG. 9, in the first and second memory cells 110 and 130, ground electrodes 111 and 131 are formed as lower electrodes, and data electrodes 113 and 133 are formed as upper electrodes. However, in this embodiment, the ground electrode 111 of the first memory cell 110 is formed as the upper electrode and the data electrode 113 as the lower electrode.

In this manner, the ground electrodes 111 and 131 may be disposed adjacent to each other through the insulating layer 120 in the first memory cell 110 and the second memory cell 130. Therefore, it is possible to prevent the accumulation of inappropriate charge between the first memory cell 110 and the second memory cell 130.

In addition, in the present embodiment, when another memory cell is formed again on the second memory cell 130 through the insulating layer, the memory cell is formed by using the lower electrode as the data electrode and the upper electrode as the ground electrode. It is desirable to arrange the data electrodes adjacently between the cells.

Meanwhile, FIG. 11 shows another modified embodiment of the embodiment shown in FIG. 9. In addition, in FIG. 11, the same code | symbol is attached | subjected to the same part as FIG. 9 and FIG. 10 mentioned above, and the detailed description is abbreviate | omitted.

In the above-described embodiment of FIG. 10, the ground electrode 111 of the first memory cell 110 and the ground electrode 131 of the second memory cell 130 are disposed adjacent to each other through the insulating layer 120. In this embodiment, the insulating layer 120 is removed and the ground electrodes 111 and 131 of the first and second memory cells 110 and 130 are formed as one single layer.

Meanwhile, in the embodiment of FIG. 11, when another memory cell is stacked on the second memory cell 130, an insulating layer is formed on the entire upper side of the second memory cell 130, and then the memory cells are formed in the same manner. Done.

According to the above-described embodiment, in forming a memory device on a substrate, a plurality of memory cells can be formed on the substrate through a method of sequentially stacking other memory cells on one memory cell.

Therefore, a larger number of memory cells can be formed in the same area than in the related art.

The embodiment according to the present invention has been described above. However, the above embodiment shows one preferred example for implementing the present invention, the illustration of such an embodiment is not intended to limit the scope of the invention. The present invention can be carried out in various modifications without departing from the spirit thereof.

As described above, according to the present invention, the memory device and the method of manufacturing the same have a simple structure that does not include a switching element, which can achieve high integration and low cost, and use substrates made of various materials such as paper and organic materials. Can be implemented.

Claims (43)

Substrate, A lower electrode formed on the substrate and made of a conductive material; A ferroelectric layer provided on the lower electrode, It is provided on the ferroelectric layer and provided with an upper electrode made of a conductive material, The ferroelectric layer is composed of a mixture of inorganic ferroelectric materials and organic matter, And the inorganic ferroelectric material comprises at least one of an oxide ferroelectric, a fluoride ferroelectric, a ferroelectric semiconductor, and a mixture of these inorganic materials. The method of claim 1, And the lower and upper electrodes are made of a conductive organic material. The method of claim 1, The substrate is a memory device, characterized in that consisting of one of the Si wafer, Ge wafer, paper, parylene coated paper, organic material. The method of claim 3, The organic material is polyimide (PI), polycarbonate (PC), polyether sulfone (PES), polyether ether ketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), polyvinyl chloride ( PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4-methyl-1-pentene) (TPX), polyarylate (PAR), polyacetal (POM), poly Phenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), polyvinyl acetal, polystyrene (PS ), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorine resin, phenol resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP), epoxy resin (EP) At least one of a diallyl phthalate resin (DAP), a polyurethane (PUR), a polyamide (PA), a silicone resin (SI) or mixtures thereof and a compound thereof. And a memory device. delete The method of claim 1, And the inorganic ferroelectric material is PZT. The method of claim 1, And further comprising a mixture of silicide, silicate or other metal in the mixture. The method of claim 1, And the organic material is a polymer ferroelectric. The method of claim 8, Wherein the polymeric ferroelectric comprises at least one or more of polyvinylidene fluoride (PVDF), a polymer, a copolymer, or a terpolymer, an odd nylon, a cyano polymer and their polymers or copolymers containing the PVDF Characterized in that the memory device. The method of claim 8, And the polymer ferroelectric is PVDF-TrFE. The method of claim 1, And the ferroelectric layer is formed by heating and calcining a mixed solution of an inorganic ferroelectric material and an organic solution. delete delete Substrate, A plurality of lower electrodes formed on the substrate in parallel to each other; A ferroelectric layer formed on the lower electrode, Comprising a plurality of upper electrodes formed in a direction perpendicular to the lower electrode in parallel with each other on the ferroelectric layer, The ferroelectric layer is composed of a mixture of inorganic ferroelectric materials and organic matter, And the inorganic ferroelectric material comprises at least one of an oxide ferroelectric, a fluoride ferroelectric, a ferroelectric semiconductor, and a mixture of these inorganic materials. The method of claim 14, And the ferroelectric layer is formed at an intersection of the lower electrode and the upper electrode. The method of claim 14, And the lower and upper electrodes are made of a conductive organic material. The method of claim 14, The substrate is a memory device, characterized in that consisting of one of the Si wafer, Ge wafer, paper, parylene coated paper, organic material. delete delete Forming a lower electrode on the substrate; A ferroelectric layer forming step of forming a ferroelectric layer composed of a mixture of an inorganic ferroelectric material and an organic material on the entire surface of the substrate on which the lower electrode is formed; An upper electrode forming step of forming an upper electrode on the ferroelectric layer, And the ferroelectric layer is formed by applying a mixed solution of an inorganic ferroelectric material and an organic solution on a substrate to form a ferroelectric film, and heating and firing the ferroelectric film. The method of claim 20, The method of manufacturing a memory device, wherein the organic material is a ferroelectric organic material. delete The method of claim 20, And the mixed solution is a mixed solution of a PZT solution and a PVDF-TrFE solution. The method of claim 23, wherein And the PZT solution is produced by mixing a PZO solution and a PTO solution. The method of claim 23, wherein The PVDF-TrFE solution contained PVDF-TrFE powder in THF (C ₄ H ₅ O), MEK (C ₄ H ₈ O), Acetone (C ₃ H ₆ O), DMF (C ₃ H ₇ NO), DMSO (C ₂ H ₆ OS) dissolved in at least one of the production method of the memory device. delete delete delete The method of claim 20, And etching to remove the remaining portions of the ferroelectric layer except for the intersection of the lower electrode and the upper electrode. The method of claim 29, And etching the ferroelectric layer through a BOE. The method of claim 29, Etching of the ferroelectric layer is performed through a two-step etching using BOE and a gold etchant. The method of claim 29, And the etching of the ferroelectric layer is carried out through a RIE method. The method of claim 20, And said firing temperature is 200 degrees or less. A first memory cell formed on the substrate, A second memory cell formed above the first memory cell, The first and second memory cells include a lower electrode made of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode made of a conductive material and provided on the ferroelectric layer. The ferroelectric layer is a memory device, characterized in that consisting of a mixture of inorganic ferroelectric material and organic material. The method of claim 34, wherein And an insulating layer is formed between the first memory cell and the second memory cell. The method of claim 34, wherein And an upper electrode of the first memory cell and a lower electrode of the second memory cell are ground electrodes. The method of claim 34, wherein And a ground electrode of the first memory cell and the second memory cell integrally formed. The method of claim 34, wherein And an upper electrode of the first memory cell and a lower electrode of the second memory cell are data electrodes. A first memory cell formed on the substrate, A second memory cell formed above the first memory cell, The first and second memory cells include a lower electrode made of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode made of a conductive material and provided on the ferroelectric layer. And the ferroelectric layer is composed of a mixture of an organic solution and a solid solution of an inorganic ferroelectric material. A first memory cell formed on the substrate, A second memory cell formed above the first memory cell, The first and second memory cells may include a plurality of lower electrodes formed on the substrate in parallel to each other, a ferroelectric layer formed on the lower electrode, and in a direction perpendicular to and parallel to the lower electrode on the ferroelectric layer. It is configured to include a plurality of upper electrodes, The ferroelectric layer is a memory device, characterized in that consisting of a mixture of inorganic ferroelectric material and organic material. A first memory cell formed on the substrate, A second memory cell formed above the first memory cell, The first and second memory cells are formed on a plurality of lower electrodes formed on the substrate in parallel to each other, a ferroelectric layer formed on the lower electrode, and formed in a direction orthogonal to the lower electrodes on the ferroelectric layer. It is configured to include a plurality of upper electrodes, And the ferroelectric layer is composed of a mixture of an organic solution and a solid solution of an inorganic ferroelectric material. A first memory cell formed on the substrate, A second memory cell formed above the first memory cell, The first and second memory cells include a lower electrode made of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode made of a conductive material and provided on the ferroelectric layer. The ferroelectric layer is composed of a mixture of an inorganic ferroelectric material and an organic material, wherein the ferroelectric layer of the first memory cell and the second memory cell is composed of different materials. A first memory cell formed on the substrate, A second memory cell formed above the first memory cell, The first and second memory cells are formed on a plurality of lower electrodes formed on the substrate in parallel to each other, a ferroelectric layer formed on the lower electrode, and formed in a direction orthogonal to the lower electrodes on the ferroelectric layer. It is configured to include a plurality of upper electrodes, The ferroelectric layer is composed of a mixture of inorganic ferroelectric materials and organic materials, and the ferroelectric layer of the first memory cell and the second memory cell is composed of different materials.

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