TWI534906B - 具有隔離區之電晶體 - Google Patents

具有隔離區之電晶體 Download PDF

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TWI534906B
TWI534906B TW100146291A TW100146291A TWI534906B TW I534906 B TWI534906 B TW I534906B TW 100146291 A TW100146291 A TW 100146291A TW 100146291 A TW100146291 A TW 100146291A TW I534906 B TWI534906 B TW I534906B
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component
transistor
region
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米喜拉鄔梅西
邱杜利斯拉班提
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全斯法姆公司
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Description

具有隔離區之電晶體
茲描述半導體電子元件、部件以及各種使用該等元件與部件之電路應用。
迄今為止,大部分使用於電力電子應用的電晶體通常以矽(Si)半導體材料製造而成。常見的用於電力應用的電晶體元件包含:Si CoolMOS、Si Power MOSFETs以及Si絕緣閘雙載子電晶體(IGBTs)。即使價格便宜,Si電力元件仍然具有一些缺點,包含:相對低的切換速度與高位準的電雜訊。最近,考慮使用碳化矽(SiC)電力元件用於電力應用,因碳化矽具有優越的性能。現在III-N半導體元件(例如氮化鎵(GaN)元件)已成為具吸引力的候選材料,藉此能承載大電流、支援高電壓並且提供極低的導通電阻與極快的切換時間。即使已展示眾多的III-N電晶體與二極體,但為求能大量製造且更廣泛採用該等元件,仍須提升該等III-N電晶體與二極體之可靠度。
第1圖顯示先前技術之電晶體,該電晶體具有源極電極14、汲極電極15、閘極電極13以及存取區(access region)23與24。在此處所稱之電晶體「存取區」,係指在電晶體中,介於源極電極與閘極電極之間以及介於閘極電極與汲極電極之間的兩區域,分別例如在第1圖中所示之區域23與24。區域23-在閘極之源極邊上的存取區,通常被稱為源極存取區;區域24-在閘極之汲極邊上的存取區,通常被稱為汲極存取區。在第1圖中所稱之電晶體「閘極區」31,係指電晶體中之某一部份,即介於第1圖中之存取區23與24之間之區域。
在使用切換電晶體的典型電力切換應用中,該等電晶體一直處於以下兩種狀態之一。在一般被稱為「導通狀態」的第一種狀態下,閘極電極的電壓相對於源極電極的電壓而言,較電晶體的閾值電壓高,且有實質電流流通過電晶體。在此狀態下,源極與汲極間的電壓差一般而言偏低,通常不超過幾伏特,例如約0.1~5伏特。在一般被稱為「關閉狀態」的第二狀態,閘極電極的電壓相對於源極電極的電壓而言,較電晶體的閾值電壓低,且無實質電流流通過電晶體。元件是導通或是關閉取決於電流是否能夠流通過元件(關閉=無電流)。電流流動取決於閘極電壓。當元件導通(閘極電壓呈高電壓)時,僅需在汲極具有小電壓(0.1~5 V)即可維持電流流動。然而,當元件關閉(閘極電壓呈低電壓)時,無論在汲極施加多高的電壓(即便高達元件的電壓上限,即能使元件損毀的電壓),仍無實質電流流動。
處在上述關閉狀態時,介於源極與汲極間的電壓值可為在約0 V至電路所供應之高電壓值範圍之間的任一值,其中電路所供應之高電壓值在一些例子中可高達100 V、300 V、600 V、1200 V、1700 V或者更高。當電晶體處在關閉狀態時,即被視為「阻斷」介於源極與汲極之間的電壓。在此所稱之「將電壓阻斷」係指當電壓施加橫越在電晶體上時,能防止實質電流流通過電晶體的能力,例如在一般的傳導下,上述實質電流係指比操作電流0.001倍大的電流。換句話說,在一般的傳導下,當電晶體將施加橫越於電晶體本身的電壓阻斷時,流通過該電晶體的總電流將不會超過操作電流的0.001倍。
此處所稱之「高電壓元件」(例如高電壓電晶體)為經最佳化而用於高電壓切換應用之電子元件。亦即,當將電晶體關閉時,將能阻斷高電壓,例如:約為300 V或更高的電壓、約為600 V或更高的電壓、約為1200 V或更高的電壓,或約為1700 V或更高的電壓,且當將電晶體導通時,在用於會使用電晶體的應用上,該電晶體具有夠低的導通電阻(RON),意即,當實質電流流通過元件時,電晶體承受的傳導損失亦夠低。高電壓元件可至少具有阻斷電壓的能力,即阻斷相當於高電壓電源的電壓或相當於用於電路使用之最高電壓的能力。高電壓元件可至少具有阻斷300 V、600 V、1200 V、1700 V之電壓的能力,或其他在應用上所需適合的阻斷電壓(blocking voltage)。換句話說,高電壓元件能阻斷介於0 V與至少高至Vmax之間的任何電壓值,其中Vmax為電路或電源能供應之最高電壓。在一些實施方式上,高電壓元件能阻斷介於0 V與至少高至2*Vmax之間的任何電壓值。
在一個態樣中,茲描述具有短路生存時間的電晶體元件。該電晶體元件包含:源極、閘極、汲極,以及半導體材料,該半導體材料包含:閘極區,該閘極區位於源極與汲極之間。電晶體元件更包含:複數個在半導體材料內的通道存取區、在半導體材料內的通道,以及在閘極區中的隔離區,該通道存取區分別介於源極與閘極之間以及介於汲極與閘極之間;該在半導體材料內的通道在閘極區與在通道存取區中具有有效寬度;該隔離區用於降低閘極區內通道之有效寬度,而不實質降低存取區內通道之有效寬度。
在另一個態樣中,茲描述包含源極、閘極、汲極,以及半導體材料的電晶體元件,其中半導體材料包含:閘極區,該閘極區位於源極與汲極之間。電晶體元件更包含:複數個在半導體材料內的通道存取區、在半導體材料內的通道,以及隔離區,該通道存取區分別介於源極與閘極之間以及介於汲極與閘極之間;在元件操作期間,該隔離區所處在的或接近的半導體材料區域具有高電場或處在低電位,該隔離區用於提升從半導體材料中收集電洞的效率。
在另一個態樣中,茲描述電晶體元件,該電晶體元件包含具有源極寬度的源極,該電晶體元件具有最大電流與導通電阻。每單位電晶體元件的源極寬度之最大電流小於500毫安培/毫米(milliamps/millimeter),且導通電阻乘以源極寬度小於30歐姆-毫米。
對在此描述的所有元件而言,可應用下列元件中的一個或更多個。該元件可包含:複數個在閘極區中的隔離區。隔離區可為經蝕刻而穿過通道的區域。該元件可包含:場平板,該場平板可沿著隔離區的邊緣或可位於通道存取區上方,該通道存取區介於閘極與汲極之間。該場平板可為傾斜場平板。該場平板可與閘極、源極、汲極、接地端或DC電壓中之一者相連接。隔離區可位於場平板下方或附近。隔離區可包含摻質,該等摻質經佈植進入半導體材料內較通道更深之深度,且可從鎂(Mg)、鋁(Al)與鐵(Fe)所組成之群組中選擇摻質。該元件可為III-N電晶體。該元件可為場效電晶體。該隔離區可具有收集電洞之能力,該等電洞係經產生於半導體材料內。閘極或源極可與隔離區的表面接觸。隔離區可增加電晶體的短路生存時間。該元件可為高電壓元件。隔離區可位於源極下方或接近源極。隔離區可位於閘極下方或接近閘極。隔離區可介於源極與閘極之間。該元件可更包含與隔離區表面接觸的金屬電極。該元件可具有阻斷至少600 V的能力。導通電阻乘以源極寬度可少於15歐姆-毫米。最大電流可小於50 A。導通電阻可小於1歐姆。最大電流與導通電阻的乘積可小於約5安培-歐姆。
電晶體元件可使用隔離區以限制可通過該元件的最大電流而無實質增加該元件的導通電阻。或者,可將隔離結構或隔離區域配置成用以收集經產生於電晶體元件的電洞。該等隔離區可同時實現上述此兩項功效。
參考第2~5圖,茲描述電晶體元件,該電晶體元件在元件閘極區的通道電荷密度以及/或通道傳導性相較於在元件存取區內的通道電荷密度以及/或通道傳導性來得低,且因此能在維持低導通電阻的同時,仍具有經減少的短路電流Imax。電晶體1包含隔離區20、21,以及22,該等隔離區介於源極14與汲極15之間。在維持可接受的低導通電阻之同時,可藉由減少或最小化可流通過元件之最大通道電流(短路電流)Imax的方式,將該等隔離區配置成用以增加或最大化電晶體1的短路生存時間。或者,可將隔離結構或隔離區域配置成用以收集經產生於電晶體1內的電洞。該等隔離區可同時實現上述此兩項功效。電晶體側向元件(lateral device)、III-N元件、場效電晶體、增強型元件(閾值電壓>0 V)、空乏型元件(閾值電壓<0 V)、高電壓元件,或上述元件之任意組合。III-N元件可為III-polar極化(III-face極化面)元件、N-polar極化(N-face極化面)元件,或半極化元件。Ga-face極化面、III-face極化面,或III-polar極化之III-N元件可包含III-N材料,該等III-N材料與離生長基板最遠之族III-face極化面或[0001]極化面一起生長,或可包含源極、閘極,或汲極電極,該等電極位於III-N材料之族III-face極化面或[0001]極化面上。nitrogen-face極化面、N-face極化面,或N-polar極化III-N元件可包含III-N材料,該等III-N材料與離生長基板最遠之N-face極化面或[0001bar]極化面一起生長,或可包含源極、閘極,或汲極電極,該等電極位於III-N材料之N-face極化面或[0001bar]極化面上。
當例如電晶體等半導體元件操作於關閉狀態時,尤其在高電壓之應用下使用元件時,可在材料層內形成大電場。此等大電場可導致電洞產生於具有此等大電場的區域,例如藉由碰撞游離的方式。該等具有正電荷的電洞在元件結構內朝向低電位區域(即低電壓區域)遷移。此等帶正電荷電洞的存在,可導致元件閾值電壓偏移、減少可靠度,以及其他不良影響。因此,若能將此等電洞的影響降至最小或消除會較佳。
再者,在一些使用高電壓電晶體之電路或系統應用上,於電路或系統故障期間,可將電晶體以高電壓操作於導通狀態(即傳導電流)持續一段短暫的時間,其中該高電壓係介於源極與汲極之間。在此短暫的時間中,流通過電晶體之電流係為電晶體可傳導之最大電流。最大電流值通常被稱為「短路電流」且以符號Imax表示。例如,在馬達驅動電路中,有時馬達會停止轉動並伴隨大電流(即短路電流)與大電壓,該電流同時間通過馬達驅動電路內之高電壓電晶體,該大電壓橫跨此等電晶體之源極端與汲極端。具有限響應時間(通常約為10微秒)的控制電路,該控制電路可傳送電壓信號至電晶體的閘極以將元件關閉並且藉此防止額外電流流動。因此,控制電路能在此種大電流、高電壓的操作模式下操作持續整個響應時間。
在上述大電流、高電壓的操作模式下,高電壓電晶體以及/或其他電路部件可能損壞或呈現無法使用。可持續在該大電流、高電壓操作模式操作而不損害電晶體的此段時間,被稱為「短路存活時間」,以符號以及給定方程式=[T*m*C]/[Imax*V]來表示「短路存活時間」,其中T表示產生損壞之前電晶體的最大溫度提升;m表示電晶體的熱質量(即電晶體通道附近區域材料的質量,例如電晶體通道附近約5微米範圍內的材料質量);C表示在電晶體通道附近區域材料的平均熱容;Imax表示電晶體能傳導的最大電流(即短路電流);以及V表示在該大電流、高電壓模式操作期間橫跨於電晶體的平均電壓。
正如上述所見關於的方程式可知,將增加的一種方法為:將短路電流Imax減少而不實質影響之方程式中的任何其他參數。例如此方法可藉由將電晶體設計具有較低的通道電荷密度以及/或較低的通道傳導性而得以實現。然而,以此方法以及其他許多方法將Imax減少,會使電晶體的導通電阻Ron增加,因此在正常的操作下會增加功率損耗。正因如此,較佳的情況則是:將短路電流Imax減少而不實質影響之方程式中的任何其他參數,而僅略微增加導通電阻。
最傳統的III-N高電子移動率電晶體(HEMTs)以及相關的電晶體元件通常會導通,意即,具有負閾值電壓,亦即,該等電晶體可在閘極電壓為零時傳導電流。此等具有負閾值電壓的元件被稱為空乏型(D-mode)元件。若在一些電力電子應用上具有常閉型(normally-off)元件會較佳,該常閉型元件即具有正閾值電壓且無法在閘極電壓為零時傳導電流的元件,為避免損害元件或其他電路部件,該常閉型元件係藉由防止元件突然導通以避免損害。常閉型元件通常被稱為增強型(E-mode)元件。
參考在此使用的第2~5圖,電晶體的「閘極區」指的是電晶體中介於兩存取區域23與24之間的部份31。第2~5圖中的電晶體包含:隔離區20、21以及22(如第2圖的平面視圖所顯示),該等隔離區的至少有部分位於元件的閘極區31內。
隔離區20~22為實質通道電流無法流通過之區域,意即該等隔離區提供在元件通道內介於源極14與汲極15之間的斷路區域(break)。該等隔離區可為將半導體材料蝕刻穿過通道之蝕刻區域,或例如以鋁(Al)、鎂(Mg),或鐵(Fe)離子佈植之離子佈植區域。如第3、4以及5圖之橫截面視圖所顯示,該元件包含:基材10、半導體材料結構32、傳導通道19(例如在半導體材料結構32中的二維電子氣體(electron gas)(2DEG))、絕緣材料層33(包含位在元件之閘極下方的閘極絕緣體部份17)、源極14、汲極15、閘極接點16、18、25,與26(顯示在第2圖的平面視圖),以及場平板27、28、29以及30(顯示在第2圖的平面視圖)。
如第3圖所示,電極29在閘極區域31內的部分為閘極接點16,且電極29在汲極存取區24內的部分為場平板28。閘極接點16、18、25以及26皆可彼此電氣連接,例如在外部電路或內在元件的外部周邊以電氣連接(未顯示)。半導體材料結構32可包含多重半導體層,例如在第3~5圖中所示之通道層11與阻絕層12。在一些實施方式上,半導體材料結構包含III-N材料或由III-N材料所形成,且該元件為III-N元件,例如III-N電晶體或FET。例如,通道層11可為GaN,且阻絕層12可為AlxGa1-xN。如在此使用的各種術語如:III-Nitride或III-N材料、層、元件、結構等等,上述術語所指的是根據化學劑量化學式AlxInyGazN(其中x+y+z約等於1)所合成的半導體材料所組成的材料、元件,或結構。在III-Nitride或III-N元件中,可將傳導通道之部分或全部包含在III-N材料層內。
第2~5圖所示之傾斜場平板27~30與閘極接點16、18、25以及26一樣皆由相同的傳導材料所形成。該等傳導材料例如為:鎳(Ni)、鉑(Pt)、多晶矽(poly-silicon)、鋁(Al)、鈦(Ti)、金(Au),或所述之組合。可將場平板使用於半導體元件(例如電晶體)中,其中藉由減少電場峰值與增加元件崩潰電壓的方式將在該元件高電場區域的電場塑形,藉此能允許以更高的電壓操作元件。場平板並不一定需要以與閘極相同的材料形成,且場平板並不一定需要與閘極相連接;在一些情況下,場平板可與源極、汲極、電性接地端,或DC電壓源相連接。絕緣材料層33(顯示於第3~5圖)至少局部定義出閘極的幾何形狀與場平板結構。第3圖所示之實現方式中,例如,絕緣材料層33包含閘極之汲極側的邊緣上的傾斜邊34,且場平板28位在傾斜邊34頂部並且與傾斜邊34接觸。因此正如在第3圖中所示,場平板28係為「傾斜場平板」。傾斜邊34包含至少實質部份,該部分對半導體材料結構32之主平面呈非垂直角度。亦可使用場平板結構來代替傾斜場平板。
再次參考第2~5圖,隔離區20、21以及22有效地減少閘極區31的通道寬度而不實質減少在存取區23與24內之通道的有效寬度。例如,元件包含三個各具有寬度Wiso(見第2圖)的隔離區20、21以及22,使得所有隔離區的總寬度Wtot等於3*Wiso。隔離區20、21以及22將閘極區31的通道寬度從Wsource值(源極接點的整個範圍)減少到(Wsource-Wtot)值,其中該閘極區31介於源極14與汲極15之間。藉此將與閘極區通道寬度成正比的最大電流Imax減少一常數(Wsource-Wtot)/Wsource,而存取電阻值(即在存取區的通道電阻值)維持近乎相同。因此,與內部通道導通電阻值以及存取電阻值之加總相等的元件總導通電阻值可能實質上不會增加。
在一些實現方式中,使用隔離區20、21以及22以限制Imax。可藉由將離子佈植進入半導體材料結構32的方式來形成該等隔離區20、21以及22。對III-N元件而言,可用來佈植的離子包含卻不受限於下列元素:鋁、鎂或鐵。或者,可藉由將半導體材料蝕刻到至少比元件通道還深的深度的方式來形成該等隔離區,並藉此將一部分的元件通道實體移除。與其他不包含隔離區的相同元件相比較,因為可能必須確保將電流以常數(Wsource-Wtot)/Wsource減少,該等隔離區可延伸至少從最靠近源極14之閘極區31的一側,一直到最靠近汲極15之閘極區31的另一側。
如第2圖中所示,對於具有場平板或具有與閘極的汲極側相連接的多重場平板27、28、29以及30的元件而言,隔離區可選擇性地進一步往汲極方向延伸而超出在第2圖中所示之場平板的汲極側的邊緣。Wtot可介於約1%與99%的Wsource之間,例如介於約10%與90%、約20%與80%,或是約10%與20%的Wsource之間。儘管閘極並不需要直接位於隔離區20、21以及22之上,閘極仍可覆蓋隔離區20、21以及22之一部分或所有部分,隔離區20、21以及22在元件的閘極區內。如此將元件製造過程簡化的方式可具有優勢。閘極金屬可與隔離區電性接觸,或可與隔離區電性隔離。在元件操作期間,當隔離區為經蝕刻區域時,沿著隔離區邊緣的電場可增加或增強。因此為了避免減少電晶體之崩潰電壓,必須包含沿著經蝕刻之隔離區20、21以及22的一些或所有邊緣配置之場平板。例如,與以沿著閘極的汲極側的邊緣之方式使用的場平板結構相同或相似的場平板結構亦可以沿著經蝕刻之隔離區的一些或所有邊緣之方式使用。
第6圖圖示說明具有隔離區40的元件,其中藉由將半導體材料至少蝕刻到比元件通道還深的深度形成該隔離區,藉此將元件通道的一部分實體移除。第6圖中所示的橫截面與第4圖中的橫截面相似,除了在第6圖中包含閘極的電極29,該電極29係以適形方式(conformally)沿著部分III-N層12與III-N層11沉積而成,其中III-N層12與III-N層11藉蝕刻而暴露出來。或者,可將絕緣體置於電極29與III-N層12與III-N層11之間(未顯示)。當將絕緣體包含介於電極29與III-N層12與III-N層11之間時,可蝕刻出穿過絕緣體的開孔使得電極29在開孔區域與III-N層12與III-N層11中之一或二者直接接觸。
在當元件內電場夠高的期間內,亦可使用隔離區20、21以及22以收集形成於元件材料層32內的電洞,例如在當元件處於關閉狀態且阻斷高電壓的期間內。使用隔離區作為電洞收集器可將電洞從元件通道周圍傳輸出去,藉此減輕電洞對元件性能與可靠度造成的不良影響。可將隔離區置於低電位(電壓)區域,使得電洞被吸向隔離區。一旦電洞接近或射向隔離區,電洞會被吸引而遠離通道的周圍或元件的其他主動區。例如,在一些實現方式中,電洞與電子可在接近隔離區20、21以及22或在隔離區20、21以及22內再結合。在其他實現方式中,金屬電極(未顯示)與隔離區的表面連接,且將夠低或負的電壓施加於該電極以如電流般將電洞攜出而穿過電極。在其他的實現方式中,閘極金屬與隔離區表面電性接觸。因當電晶體1處於關閉狀態時,閘極16通常處於低或負電壓,閘極電壓可足以吸引電洞使電洞遠離元件通道周圍或其他主動區。
對於將隔離區作為電洞收集器而言,在許多情況下,對閘極金屬16必須與在隔離區20、21以及22內之至少一部分的底層半導體材料電性接觸。許多電晶體包含閘極介電質17,該等介電質17為介於閘極金屬16與底層半導體材料12的絕緣體。當使用閘極介電質時,為了能使閘極金屬16或其他電極與底層隔離區接觸,需要在介電質中存在斷路區域,該斷路區域涵蓋隔離區20、21以及22的至少一部分。
將隔離區20、21以及22作為電洞收集器使用可具有下列性能。半導體材料可在該等隔離區上蝕刻,在一些情況下可至少蝕刻穿過元件通道。在此情況下,金屬電極或閘極金屬的一部份會與半導體藉蝕刻而暴露出之表面的至少一部份電性接觸。或者,該等隔離區可為在半導體材料內的離子佈植區域,該離子佈植區域可延伸穿過通道區域,藉此在元件通道內形成斷路區域。離子佈植區域可具有傳導實質電洞的能力卻無傳導實質電流之能力。例如該離子佈植區域可為p型或名義上為p型之區域。可將隔離區置於高電場區域,或在高電場區域的周圍。因為電洞可產生於高電場區域,將隔離區置於產生電洞的區域附近可提升電洞的收集效率。在元件操作期間,通常具有高電場的區域實例包含介於閘極電極與汲極電極之間的區域,尤其是以下區域:靠近閘極電極的汲極側的邊緣,或靠近場平板之處或位於場平板下方。
亦可將隔離區置放於低電壓或低電位的區域,或置放於低電壓或低電位的區域的周圍。因為電洞被往低電壓或低電位的區域的方向吸引,將隔離區置於靠近會吸引電洞的區域可提升電洞的吸收效率。在元件操作期間,通常具有低電壓或低電位的區域實例包含以下區域:靠近源極電極之處或位於源極電極下方之處、靠近閘極電極之處或位於閘極電極下方之處,或介於源極電極與閘極電極之間。或者,可將隔離區置於高電場的區域(即在元件操作期間具有高電場的區域)。因為電洞可產生於高電場區域,將隔離區置於產生電洞的區域附近可提升電洞的收集效率。可置放電洞收集器的位置實例包含卻不受限於下列位置:在第2圖中所示之源極電極14的下方或附近、閘極電極16、18、25以及26的下方或附近、介於源極電極14與閘極電極16、18、25以及26之間、介於閘極電極16、18、25以及26與汲極電極15之間,或場平板的下方或附近。Wtot可介於約1%與99%的Wsource之間,例如介於約10%與20%的Wsource之間,其中Wtot再次如第2圖中所示,表示將所有隔離區寬度結合之總寬度。當隔離區20、21以及22為蝕刻區域時,在元件操作期間,可增加或增強沿著經蝕刻之隔離區邊緣的電場。因此,為了避免減少電晶體的崩潰電壓,必須包含沿著經蝕刻之隔離區的一些或所有邊緣配置之場平板。例如,與以沿著閘極的汲極側的邊緣之方式使用的場平板結構相同或相似的場平板結構亦可以沿著經蝕刻之隔離區的一些或所有邊緣之方式使用。
具有隔離區(用於限制最大電流)的III-N高電子移動率電晶體(HEMT)可具有每單位源極寬度下之最大電流位準Imax,其中該每單位寬度電流小於500毫安/毫米,例如在當導通電阻RON與源極寬度的乘積小於30歐姆-毫米(例如小於約15、5、3、2或1歐姆-毫米)時,每單位電流約小於350、150或50毫安/毫米。被設計成用來阻斷較大電壓的元件通常使用較大的導通電阻。因此,被設計成能阻斷1200 V的元件可具有約30歐姆-毫米或較少的導通電阻,而被設計成能阻斷600 V的元件遂可具有約15歐姆-毫米或較少的導通電阻。在一些實現方式中,包含隔離區的電晶體之最大電流位準係小於50 A,例如小於25、10或5 A。在另一些實現方式中,包含隔離區的電晶體之導通電阻係小於1歐姆,例如小於0.5、0.2或0.1歐姆。在其他的實現方式中,最大電流位準與導通電阻的乘積可小於約5安培-歐姆。
以上已描述若干實現方式。然而,理應瞭解各種可在不偏離在此所述之技術以及元件的範疇與精神下進行改良。因此,其他實現方式係在以下申請專利範圍請求發明的範疇之內。
3...剖線
4...剖線
5...剖線
10...基材
11...通道層
12...阻絕層
14...源極電極
15...汲極電極
16...閘極接點
17...閘極絕緣部
18...閘極接點
19...傳導通道
20...隔離區
21...隔離區
22...隔離區
23...源極存取區
24...汲極存取區
25...閘極接點
26...閘極接點
27...場平板
28...場平板
29...場平板
30...場平板
31...閘極區
32...半導體材料結構
33...絕緣材料層
34...傾斜邊
40...隔離區
第1圖為先前技術的元件的平面視圖;
第2圖為根據此說明書的元件的平面視圖;
第3圖為將第2圖中的元件穿過剖線3-3的橫截面圖;
第4圖為將第2圖中的元件穿過剖線4-4的橫截面圖;
第5圖為將第2圖中的元件穿過剖線5-5的橫截面圖;及
第6圖為根據此說明書的元件的橫截面圖。
各種圖示中相同的參考符號所指為相同的元件。
3...剖線
4...剖線
5...剖線
14...源極電極
15...汲極電極
16...閘極接點
18...閘極接點
20...隔離區
21...隔離區
22...隔離區
23...源極存取區
24...汲極存取區
25...閘極接點
26...閘極接點
27...場平板
28...場平板
29...場平板
30...場平板
31...閘極區

Claims (33)

  1. 一種具有一短路存活時間的電晶體元件,該電晶體元件包含:一源極、一閘極,與一汲極;一半導體材料,該半導體材料包含一介於該源極與該汲極之間的閘極區;複數個在該半導體材料內的通道存取區,該等通道存取區分別介於該源極與該閘極之間,以及介於該汲極與該閘極之間;一在該半導體材料內的通道,該通道具有在該閘極區內以及在該等通道存取區內的一有效寬度;以及一在該閘極區內的隔離區,該隔離區用於減少在該閘極區內之該通道的該有效寬度,而不實質減少在該等存取區內之該通道的該有效寬度;沿著該隔離區的一邊緣的一場平板。
  2. 如請求項第1項所述的電晶體元件,其中該閘極區內有複數個隔離區。
  3. 如請求項第1項所述的電晶體元件,其中該隔離區為一經蝕刻穿過該通道之區域。
  4. 如請求項第1項所述的電晶體元件,其中該隔離區包含摻質,將該等摻質佈植進該半導體材料達一深度,該深度比該通道的該深度還要深。
  5. 如請求項第4項所述的電晶體元件,其中該等摻質係由下列元素所組成之一群組中選出::鎂(Mg)、鋁(Al),以及鐵(Fe)。
  6. 如請求項第1項所述的電晶體元件,該電晶體元件更包含:一場平板,該場平板位於該通道存取區的上方,該通道存取區介於該閘極與該汲極之間。
  7. 如請求項第6項所述的電晶體元件,其中該場平板為一傾斜場平板。
  8. 如請求項第6項所述的電晶體元件,其中該場平板與下列中之一者相連接,包含:該閘極、該源極、該汲極、一接地端或一DC電壓。
  9. 如請求項第1項所述的電晶體元件,其中該元件為一III-N電晶體。
  10. 如請求項第1項所述的電晶體元件,其中該元件為一場 效電晶體。
  11. 如請求項第1項所述的電晶體元件,其中該隔離區具有收集電洞之能力,該等電洞產生於該半導體材料內。
  12. 如請求項第1項所述的電晶體元件,其中該閘極與該隔離區的一表面接觸。
  13. 如請求項第1項所述的電晶體元件,其中該隔離區增加該電晶體的該短路生存時間。
  14. 如請求項第1項所述的電晶體元件,其中該元件為一高電壓元件。
  15. 一種電晶體元件,該電晶體元件包含:一源極、一閘極,與一汲極;一半導體材料,該半導體材料包含一介於該源極與該汲極之間的閘極區;複數個在該半導體材料內的通道存取區,該等通道存取區分別介於該源極與該閘極之間,以及介於該汲極與該閘極之間;一在該半導體材料內的通道;以及一隔離區,在元件操作期間,該隔離區處在的或接近的 該半導體材料的一區域具有一高電場或處在一低電位,該隔離區用於提升從該半導體材料中收集電洞的效率;其中該源極與該隔離區的一表面接觸。
  16. 如請求項第15項所述的電晶體元件,其中該隔離區位在該源極的下方或接近該源極。
  17. 如請求項第15項所述的電晶體元件,其中該隔離區位在該閘極的下方或接近該閘極。
  18. 如請求項第15項所述的電晶體元件,其中該隔離區位於該源極與該閘極之間。
  19. 如請求項第15項所述的電晶體元件,其中該隔離區位於該閘極與該汲極之間。
  20. 如請求項第15項所述的電晶體元件,該電晶體元件更包含一場平板,該場平板位於該通道存取區的上方,該通道存取區介於該閘極與該汲極之間。
  21. 如請求項第20項所述的電晶體元件,其中該隔離區位於該場平板的下方或接近該場平板。
  22. 如請求項第15項所述的電晶體元件,其中該閘極與該隔離區的一表面接觸。
  23. 如請求項第15項所述的電晶體元件,該電晶體元件更包含一金屬電極,該金屬電極與該隔離區的一表面接觸。
  24. 如請求項第15項所述的電晶體元件,其中該元件為一高電壓元件。
  25. 如請求項第15項所述的電晶體元件,其中該元件為一III-N電晶體。
  26. 如請求項第15項所述的電晶體元件,其中該隔離區具有收集電洞之能力,該等電洞產生於該半導體材料內。
  27. 一種電晶體元件,該電晶體元件包含一源極、一閘極、及一汲極,該源極具有一源極寬度,其中一閘極區介於該源極與該汲極之間,一隔離區在該閘極區內,且一場平板沿著該隔離區的一邊緣,該電晶體元件具有一最大電流與一導通電阻,其中每單位該源極寬度之該最大電流小於500毫安/毫米,且該導通電阻乘以該源極寬度小於30歐姆-毫米。
  28. 如請求項第27項所述的電晶體元件,其中該元件具有阻斷至少600V之能力。
  29. 如請求項第28項所述的電晶體元件,其中該導通電阻乘以該源極寬度小於15歐姆-毫米。
  30. 如請求項第27項所述的電晶體元件,其中該最大電流小於50A。
  31. 如請求項第27項所述的電晶體元件,其中該導通電阻小於1歐姆。
  32. 如請求項第27項所述的電晶體元件,其中該最大電流與該導通電阻的乘積小於約5安培-歐姆。
  33. 如請求項第27項所述的電晶體元件,其中該元件為一III-N電晶體。
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WO2012082519A1 (en) 2012-06-21
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US20150333147A1 (en) 2015-11-19
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