CN103262244B - 具有隔离区的晶体管 - Google Patents

具有隔离区的晶体管 Download PDF

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CN103262244B
CN103262244B CN201180059979.4A CN201180059979A CN103262244B CN 103262244 B CN103262244 B CN 103262244B CN 201180059979 A CN201180059979 A CN 201180059979A CN 103262244 B CN103262244 B CN 103262244B
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乌梅什·米什拉
斯拉班缇·乔杜里
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Transphorm Inc
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Abstract

提供一种晶体管器件，包括：源极、栅极、漏极；包括在源极和漏极之间的栅极区的半导体材料；在栅极的任一侧的半导体材料中的多个沟道接入区；半导体材料中的在栅极区和沟道接入区中具有有效宽度的沟道；以及栅极区中的隔离区。隔离区用于在基本上不降低沟道在接入区中的有效宽度的情况下降低沟道在栅极区中的有效宽度。作为替代，隔离区可被构造成收集晶体管器件中产生的空穴。隔离区可同时实现上述两种功能。

Description

具有隔离区的晶体管
技术领域
提供了半导体电子器件和组件，以及采用该半导体电子器件和组件的多种电路应用。
背景技术
迄今为止，功率电子应用中使用的大多数晶体管通常都用硅（Si）半导体材料来制造。用于功率应用的常用晶体管器件包括SiCoolMOS、SiPowerMOSFET以及Si绝缘栅双极晶体管（IGBT）。虽然Si功率器件较为廉价，但是它们存在许多缺点，包括相对低的切换速度以及高电气噪声。近来，已经考虑采用碳化硅（SiC）功率器件，因为它们具有优越的性质。现在将新兴起的诸如氮化镓（GaN）器件的III-N半导体器件作为具有吸引力的候选，从而能承载大电流、耐受高电压且提供非常低的导通电阻（on-resistance）以及快速的切换时间。虽然已经论证了多种III-N晶体管和二极管，但是仍然需要进一步提升可靠性以便能大规模制造并更普遍的采用这些器件。
图1示出现有技术的晶体管，其具有源电极14、漏电极15、栅电极13以及接入区23和24。如在此所用的，晶体管的“接入区”分别是指图1中的晶体管的源和栅电极之间以及栅和漏电极之间的两个区域，即区域23和24。区域23（栅极的源极侧上的接入区）通常被称为源极接入区，且区域24（栅极的漏极侧上的接入区）通常被称为漏极接入区。在此，晶体管的“栅极区”31是指图1中的两个接入区23和24之间的晶体管的部分。
在其中使用开关晶体管的典型功率切换应用中，晶体管总是处于两种状态下的一种状态。在第一状态下，其通常被称为“导通态”，相对于源电极的栅电极处的电压高于晶体管阈值电压，且实质电流（substantialcurrent）流过晶体管。在该状态下，源极和漏极之间的电压差通常较低，一般不大于几个伏特，例如约0.1-5伏。在第二状态下，其通常被称为“截止态”，相对于源电极的栅电极处的电压低于晶体管阈值电压，且没有实质电流流过晶体管。器件导通或截止与否取决于电流是否能流过器件（截止=没有电流）。电流由栅极上的电压决定。当器件导通（栅极电压高）时，在漏极处仅需要较小的电压（0.1-5V）来保持电流流动。然而，当器件截止（栅极电压低）时，无论施加到漏极的电压多大（直至器件的高压极限，在该点处器件会被击穿），都没有实质的电流流动。
在截止状态下，源极和漏极之间的电压可以是从约0V至电路高电压源的电压值的范围内的任意值，电路高电压源的电压值在一些情况下可高达100V、300V、600V、1200V、1700V或更高。当晶体管处于截止状态时，称为在源极和漏极之间“阻塞电压”。在此，术语“阻塞电压”是指在正常传导过程中，在电压施加在晶体管两端时，晶体管防止诸如大于操作电流的0.001倍的电流的实质电流流过晶体管的能力。换言之，虽然晶体管能阻塞施加在其上的电压，但是穿过晶体管的总电流在正常传导过程中将不能大于操作电流的0.001倍。
如在此所用的，诸如高压晶体管的“高压器件”是优化用于高压开关应用的电子器件。即当晶体管截止时，能阻塞高电压，例如约300V或更高、约600V或更高、约1200V或更高或约1700V或更高，并且，当晶体管导通时，它具有用于它在其中使用的应用的足够低的导通电阻（RON），即它在实质电流穿过器件时表现出足够低的传导损失。高压器件可至少能阻塞等于高电压电源或使用它的电路的最大电压的电压。高压器件能阻塞300V、600V、1200V、1700V，或为应用所需的其他合适的阻塞电压。换言之，高压器件可阻塞0V以及至少Vmax之间的任何电压，其中，Vmax是可由电路或电源供应的最大电压。在某些实施方案中，高压器件可阻塞0V以及至少2*Vmax之间的任何电压。
发明内容
在一个方面，提供一种具有短路存活时间的晶体管器件。晶体管器件包括源极、栅极、漏极以及包括栅极区的半导体材料，栅极区位于源极和漏极之间。晶体管器件还包括分别位于源极和栅极之间以及漏极和栅极之间的半导体材料中的多个沟道接入区，在栅极区和沟道接入区中具有有效宽度的半导体材料中的沟道，以及栅极区中的隔离区，隔离区用于在基本上不降低沟道在接入区中的有效宽度的情况下降低沟道在栅极区中的有效宽度。
另一方面，描述一种晶体管器件，其包括源极、栅极、漏极以及包括栅极区的半导体材料，栅极区位于源极和漏极之间。晶体管器件还包括分别位于源极和栅极之间以及漏极和栅极之间的半导体材料中的多个沟道接入区，半导体材料中的沟道以及半导体材料的在器件操作期间具有高电场或处于低电势的区域中或其附近的隔离区，隔离区用于提高从半导体材料中收集空穴的效率。
又另一方面，描述了一种晶体管器件，其包括具有源极宽度的源极，晶体管器件具有最大电流以及导通电阻。晶体管器件的每单位源极宽度的最大电流小于500毫安/毫米，且导通电阻乘以源极宽度小于30欧姆-毫米。
对于本文所述的所有器件来说，可应用下列中的一种或多种。器件可包括栅极区中的多个隔离区。隔离区可以是蚀刻穿过沟道的区域。器件可包括场板（fieldplate），其可沿隔离区的一个边缘或可位于栅极和漏极之间的沟道接入区上。场板可以是倾斜场板。场板可连接至栅极、源极、漏极、接地端或DC电压中的一个。隔离区可位于场板下或其附近。隔离区可包含注入进半导体材料的掺杂物，掺杂物注入进半导体材料的深度大于沟道的深度，且掺杂物可选自由Mg,Al和Fe组成的组。器件可以是III-N晶体管。器件可以是场效应晶体管。隔离区能收集半导体材料中产生的空穴。栅极或源极可接触隔离区的表面。隔离区可增加晶体管的短路存活时间。器件可以是高压器件。隔离区可位于源极之下或其附近。隔离区可位于栅极之下或其附近。隔离区可位于源极和栅极之间。器件还包括接触隔离区的表面的金属电极。器件能阻塞至少600V。导通电阻乘以源极宽度可小于15欧姆-毫米。最大电流可小于50A。导通电阻可小于1欧姆。最大电流和导通电阻的乘积可小于约5安培-欧姆。
在晶体管中可使用隔离区以在基本上不增大器件的导通电阻的情况下限制能流过器件的最大电流。或者，隔离结构或区域可被构造成收集晶体管器件中产生的空穴。隔离区可同时实现上述两种功能。
附图说明
图1是现有技术器件的俯视图；
图2是根据本说明书的器件的俯视图；
图3是沿图2的器件的截面3-3截取的截面图；
图4是沿图2的器件的截面4-4截取的截面图；
图5是沿图2的器件的截面5-5截取的截面图；以及
图6是根据本说明书的器件的截面图。
各个附图中相同的附图标记表示相同的要素。
具体实施方式
参考图2-5，描述了一种晶体管器件，其在器件的栅极区中具有比器件接入区中低的沟道电荷密度和/或低的沟道传导性，且因此具有降低的短路电流Imax，同时仍能保持低导通电阻。晶体管1包括源极14和漏极15之间的隔离区20、21和22。隔离区可被构造成通过降低或最小化流过器件的最大沟道电流（短路电流）Imax而增大或最大化晶体管1的短路存活时间，同时能保持容许的低导通电阻。或者，隔离结构或区域可被构造成收集晶体管1中产生的空穴。隔离区可同时实现上述两种功能。晶体管可以是横向器件、III-N器件、场效应晶体管、增强型器件（阈值电压>0V）、耗尽型器件（阈值电压<0V）、高压器件或这些器件的任意组合。III-N器件可以是III极化（III-面）器件、N极化（N-面）器件或半极化器件。镓面、III-面或III极化的III-N器件可包括最远离生长衬底的族III-面或[0001]面生长的III-N材料，或可包括III-N材料的族III-面或[0001]面上的源极、栅极或漏极电极。氮面、N-面或N-极化的III-N器件可包括最远离生长衬底的N-面或[0001bar]面生长的III-N材料，或可包括III-N材料的N-面或[0001bar]面上的源极、栅极或漏极电极。
当诸如晶体管的半导体器件在截止状态下操作时，材料层中可存在大电场，特别是在该器件在高压应用中使用时。这些大电场可导致在这些电场巨大的区域中产生空穴（例如通过碰撞电离）。具有正电荷的空穴朝向低电势（即低电压）的区域迁移进器件结构。这些正电荷的存在可导致器件阈值电压偏移、降低的可靠性以及其他不希望存在的影响。因此，希望最小化或消除这些空穴的影响。
而且，在其中使用高压晶体管的某些电路或系统应用中，在电路或系统失效期间，晶体管可借助源极和漏极之间的大电压而在导通态下短时操作（即传导电流）。在该短时期间，流过晶体管的电流是晶体管能传导的最大电流。该最大电流值通常被称为“短路电流”并由符号Imax表示。例如，在电机驱动电路中，有时电机会停止运转，同时伴随有大电流（即短路电流）流过电机驱动电路中的高压晶体管，且这些晶体管的源极和漏极端子上具有大电压。可将电压信号发送至晶体管的栅极以将器件关闭并由此进一步防止电流流动的控制电路具有有限的响应时间，通常约为10微秒。因此操作的这种高电流、高电压模式会持续控制电路的整个响应时间。
在上述操作的高电流、高电压模式期间，高压晶体管和/或其他电路部件会变得损坏或表现为不能操作。在不损坏晶体管的情况下，可持续操作的高电流、高电压模式的时间长度被称为“短路存活时间”，由符号τ表示并由等式τ=[ΔT*m*C]/[Imax*V]给出，其中，ΔΤ是晶体管遭受损坏之前的最大温升，m是晶体管的热质量（即晶体管沟道附近的材料质量，例如晶体管沟道的约5微米以内的材料的质量），C是晶体管沟道附近的材料的平均热容量，Imax是晶体管能传导的最大电流（即短路电流），且V是在操作的高电流、高电压模式期间跨过晶体管的平均电压。
如上述用于τ的等式所示，一种方法是增大τ以在基本不影响τ的等式中的其他参数的情况下降低短路电流Imax。例如，这可通过设计具有较低沟道电荷密度和/或较低沟道传导性的晶体管来实现。但是，通过这种方法以及通过许多其他方法来降低Imax会增大晶体管的导通电阻Ron，因此会增加正常操作期间的功耗。因此希望在基本上不影响τ的等式中的这些其他参数中任意参数的情况下降低Imax，同时仅最小化增加导通电阻。
大多数现有的III-N高电子迁移率晶体管（HEMT）以及相关晶体管器件通常处于导通，即具有负阈值电压，这意味着它们可在零栅极电压下传导电流。这些具有负阈值电压的器件被称为耗尽型（D型）器件。在某些功率电子应用中优选具有常关器件，即具有正阈值电压的器件，其不能在零栅极电压下传导电流，使得通过防止器件偶然导通而避免损坏器件或其他电路部件。常关器件通常被称为增强型（E型）器件。
参考图2-5，如在此所用的，晶体管的“栅极区”是指两个接入区23和24之间的晶体管的部分31。图2-5的晶体管包括至少部分位于器件的栅极区31中的隔离区20、21和22（图2的俯视图中所示）。
隔离区20-22是实质沟道电流不能流过的区域，即它们在源极14和漏极15之间的器件沟道中提供断开。它们可以是蚀刻区，其中半导体材料已被蚀刻穿过沟道，或者例如利用Al、Mg或Fe离子注入的离子注入区。如图3，4和5的截面图中所示，器件包括衬底10、半导体材料结构32、诸如半导体材料结构32中的二维电子气（2DEG）的传导沟道19、可包括器件的栅极下的栅绝缘体部17的绝缘材料层33、源极14、漏极15、栅极接触16、18、25和26（图2的俯视图中所示）以及场板27、28、29和30（图2的俯视图中所示）。
如图3中所示，位于栅极区31中的电极29的部分是栅极接触16，且位于漏极接入区24中的电极29的部分是场板28。例如在电路外部或固有器件（未示出）的外周的外部，栅极接触16、18、25和26可全部电连接彼此。半导体材料结构32可包括多个半导体层，例如沟道层11和阻挡层12，如图3-5中所示。在某些实施方式中，半导体材料结构包括或由III-N材料形成，且器件是III-N器件，例如III-N晶体管或FET。例如，沟道层11可以是GaN且阻挡层12可以是AlxGa1-xN。如在此所用的，术语III-氮化物或III-N材料、层、器件、结构等是指由依据化学计量方程式AlxInyGazN的化合物半导体材料组成的材料、器件或结构，其中x+y+z约为1。在III-氮化物或III-N器件中，传导沟道可以部分或整体地被包含在III-N材料层内。
图2-5中所示的倾斜场板27-30由与栅极接触16、18、25和26相同的导电材料形成。这些导电材料的实例是Ni、Pt、多晶硅、Al、Ti、Au或其组合。场板可用于诸如晶体管的半导体器件中，从而以降低峰值电场并增加器件击穿电压的方式构形器件的高电场区中的电场，由此允许更高的电压操作。场板不必需由与栅极相同的材料形成，且其不必需连接至栅极；在某些情况下，其可连接至源极、漏极、电接地端或DC电压源。绝缘材料层33（图3-5中所示）至少部分地定义栅极和场板结构的几何形状。在图3中所示的实施方式中，例如，绝缘材料层33包括栅极的漏极侧上的倾斜边缘34，且场板28位于倾斜边缘34的顶部上并接触倾斜边缘34。因此场板28是“倾斜场板”，如图3中所示。倾斜边缘34至少包括不与半导体材料结构32的主面成直角的实质部分。也可应用与和倾斜场板交替的场板结构。
仍然参考图2-5，隔离区20、21和22在基本上不降低接入区23和24中的沟道的有效宽度的情况下能有效降低栅极区31中的沟道宽度。例如，器件包括三个隔离区20、21和22，各个隔离区都具有宽度Wiso（参见图2），以便所有隔离区的总宽度Wtot等于3*Wiso。隔离区20、21和22将源极14和漏极15之间的栅极区31中的沟道宽度从值Wsource（源极接触的整个范围）降低至值（Wsource-Wtot）。因此，按系数（Wsource-Wtot）/Wsource减小与栅极区中的沟道宽度成比例的最大电流Imax，同时接入电阻（即接入区中的沟道电阻）大致保持不变。因此，基本上不会增加总的器件导通电阻，其等于固有沟道导通电阻（即栅极区31中的沟道的部分的导通电阻）与接入电阻之和。
在某些实施方式中，隔离区20、21和22用于限制Imax。它们可通过将离子注入进半导体材料结构32形成。对于III-N器件来说，可进行注入的离子包括但不限于Al、Mg或Fe。或者，隔离区可通过将半导体材料至少蚀刻至深度大于器件沟道的深度而形成，由此实际去除一部分器件沟道。隔离区可至少从离源极14最近的栅极区31一侧一直延伸至离漏极15最近的栅极区31的另一侧，因为较之其他不包括隔离区的等同器件，需要确保电流按系数(Wsource-Wtot)/Wsource减小。
对于具有连接至栅极的漏极侧边缘的场板或多个场板27、28、29和30的器件来说，如图2中所示，隔离区可任选地还向图2中所示的场板的漏极侧边缘上的漏极延伸。Wtot可在Wsource的约1%和99%之间，例如在Wsource的约10%和90%之间，约20%和80%之间，或约10%和20%之间。虽然栅极不必直接位于隔离区20、21和22上，但是其可覆盖处于器件的栅极区中的隔离区20、21和22部分或所有部分。这是有利的，因为这可简化器件制造工艺。栅极金属可电接触隔离区或可与它们电绝缘。当隔离区是蚀刻区时，沿它们边缘的电场可在器件操作期间增大或增强。因此，为了防止晶体管击穿电压的降低，需要包括沿蚀刻隔离区20、21和22的某些或全部边缘的场板。例如，与沿栅极的漏极侧边缘采用的场板相同或相似的场板结构可沿蚀刻隔离区的某些或全部边缘被使用。
图6示出具有隔离区40的器件，其中，隔离区通过将半导体材料至少蚀刻至深度大于器件沟道的深度而形成，由此实际去除一部分器件沟道。图6中所示的截面图类似于图4中所示的截面图，不同之处在于在图6中，包括栅极的电极29沿通过蚀刻而暴露的部分III-N层12和11共形地沉积。替代地，绝缘体可位于电极29和III-N层11和12（未示出）之间。当电极29和III-N层11和12之间包括绝缘体时，孔被可蚀刻穿过绝缘体以便电极29在孔区域中直接接触III-N层11和12中的一者或两者。
隔离区20、21和22还可用于在器件中的电场足够高时的过程中，例如当器件处于截至态且阻塞高电压时，收集器件材料层32中形成的空穴。隔离区用作可导致要被传输远离器件沟道附近空穴的空穴集电器，由此缓和它们对器件性能和可靠性的有害作用。隔离区可位于低电势（电压）的区域中，使得向隔离区吸引空穴。一旦空穴接近或入射在隔离区上，它们可被吸引以远离沟道附近或器件的其他有源区。例如，在某些实施方式中，空穴可在隔离区20、21和22附近或之内与电子复合。在其他实施方式中，金属电极（未示出）连接至隔离区的表面，且足够低或负电压施加至该电极以便通过电极运送空穴作为电流。在其他实施方式中，栅极金属与隔离区的表面电接触。因为栅极16在晶体管1处于截至态时通常处于低或负电压，因此栅极上的电压足以吸引空穴远离器件沟道或其他有源区附近。
对于用作空穴集电器的隔离区来说，在许多情况下，需要栅极金属16电接触隔离区20、21和22中的下层半导体材料的至少一部分。许多晶体管都包括栅极电介质17，其是栅极金属16和下层半导体材料12之间的绝缘体。当使用栅极电介质时，在隔离区20、21和22的至少一部分上需要打断电介质以便允许栅极金属16或其他电极接触下层隔离区。
隔离区20、21和22用作空穴集电器可具有以下性质。它们可以是其中半导体材料被蚀刻的区域，在某些情况下至少蚀刻穿过器件沟道。在这种情况下，金属电极或栅极金属的一部分电接触通过蚀刻暴露的半导体表面的至少一部分。替代地，它们可以是半导体材料中的离子注入区，其中注入区可延伸穿过沟道区，由此在器件沟道中形成打断部分。离子注入区能传导实质空穴但不能传导实质电子电流。例如，它们可以是p型或名义上的p型区。隔离区可位于高电场的区域中或位于高电场的区域附近。因为空穴可被产生在高电场的区域中，因此将隔离区置于其中产生空穴的区域附近可提升空穴收集效率。通常在器件操作期间具有高电场的上述区域的实例包括栅极和漏极电极之间的区域，特别是栅电极的漏极侧边缘附近或场板附近或其下。
隔离区还可位于低电压或低电势的区域中或低电压或低电势的区域附近。因为空穴被吸引向低电压或低电势的区域，所以将隔离区置于空穴被吸引处的附近可提升空穴收集效率。在器件操作期间通常处于低电压或低电势的区域的实例包括源电极附近或其下的区域，栅电极附近或其下的区域或源极和栅极电极之间的区域。替代地，隔离区可位于高电场的区域中（即在器件操作期间具有高电场的区域）。因为空穴产生在高电场的区域中，因此将隔离区置于产生空穴附近可提高空穴收集效率。可设置空穴集电器的位置的实例包括但不限于图2中所示的源电极14之下或其附近，栅电极16、18、25和26之下或其附近，源电极14和栅电极16、18、25和26之间，栅电极16、18、25和26和漏电极15之间或场板之下或其附近。Wtot可在Wsource的约1%和99%之间，例如于Wsource的约10%和20%之间，其中Wtot还是如图2中所示的所有隔离区的总组合宽度。当隔离区20、21和22是蚀刻区时，沿蚀刻的隔离区的边缘的电场可在器件操作期间增大或增强。因此，为了防止晶体管击穿电压的降低，需要包括沿蚀刻的隔离区的某些或所有边缘的场板。例如，与沿栅极的漏极侧边缘使用的场板相同或相似的场板结构可沿蚀刻的隔离区的某些或所有边缘被使用。
具有隔离区并用于限制最大电流的III-N高电子迁移率晶体管（HEMT）可具有小于500mA/mm例如小于350、150或50mA/mm，的每单位源极宽度的最大电流水平Imax，同时导通电阻Ron和源极宽度的乘积小于约30欧姆-毫米，例如小于约15、5、3、2或1欧姆-毫米。对于设计为阻塞较大电压的器件来说，导通电阻通常较大。因此，设计为能阻塞1200V的器件可具有约30欧姆-毫米或以下的导通电阻，而设计能阻塞600V的器件可具有约15欧姆-毫米或以下的导通电阻。在某些实施方式中，包括隔离区的晶体管的最大电流水平小于50A，例如小于25、10或5A。在其他实施方式中，包括隔离区的晶体管的导通电阻小于1ohm，例如小于0.5、0.2或0.1ohms。仍在其他实施方式中，最大电流水平和导通电阻的乘积可小于约5Amp-ohms。
已经描述了多个实施方式。但是，将可以理解的是在不脱离在此所述的技术和器件的精神和范围的情况下可对本发明进行各种修改。因此，其他实施方式也落入下述权利要求的范围内。

Claims (27)

1.一种具有短路存活时间的晶体管器件，包括：
源极、栅极和漏极；
半导体材料，所述半导体材料包括在所述源极和所述漏极之间的栅极区；
多个沟道接入区，所述多个沟道接入区在所述半导体材料中，分别位于所述源极和所述栅极之间以及所述漏极和所述栅极之间；
沟道，所述沟道在所述半导体材料中，具有在所述栅极区和在所述沟道接入区中的有效宽度；以及
隔离区，所述隔离区在所述栅极区中，用于在基本上不降低所述沟道在所述接入区中的有效宽度的情况下降低所述沟道在所述栅极区中的有效宽度，其中，所述源极接触所述隔离区的表面。
2.根据权利要求1所述的晶体管器件，其中，在所述栅极区中存在多个隔离区。
3.根据权利要求1所述的晶体管器件，其中，所述隔离区是蚀刻穿过所述沟道的区域。
4.根据权利要求1所述的晶体管器件，还包括沿所述隔离区的边缘的场板。
5.根据权利要求1所述的晶体管器件，其中，所述隔离区包含掺杂物，该掺杂物注入进所述半导体材料的深度大于所述沟道的深度。
6.根据权利要求5所述的晶体管器件，其中，所述掺杂物选自由Mg、Al和Fe组成的组。
7.根据权利要求1所述的晶体管器件，还包括位于在所述栅极和所述漏极之间的所述沟道接入区之上的场板。
8.根据权利要求7所述的晶体管器件，其中，所述场板是倾斜场板。
9.根据权利要求7所述的晶体管器件，其中，所述场板连接至所述栅极、所述源极、所述漏极、接地端或DC电压中的一个。
10.根据权利要求1所述的晶体管器件，其中，所述器件是III-N晶体管。
11.根据权利要求1所述的晶体管器件，其中，所述器件是场效应晶体管。
12.根据权利要求1所述的晶体管器件，其中，所述隔离区能收集在所述半导体材料中产生的空穴。
13.根据权利要求1所述的晶体管器件，其中，所述栅极接触所述隔离区的表面。
14.根据权利要求1所述的晶体管器件，其中，所述隔离区增加所述晶体管的短路存活时间。
15.根据权利要求1所述的晶体管器件，其中，所述器件是高压器件。
16.一种晶体管器件，包括：
源极、栅极和漏极；
半导体材料，所述半导体材料包括在所述源极和所述漏极之间的栅极区；
多个沟道接入区，所述多个沟道接入区在所述半导体材料中，分别位于所述源极和所述栅极之间以及所述漏极和所述栅极之间；
沟道，所述沟道位于所述半导体材料中；以及
隔离区，所述隔离区位于所述半导体材料的在器件操作期间具有高电场或处于低电势的区域中或其附近，用于提高从所述半导体材料中收集空穴的效率，其中，所述源极接触所述隔离区的表面。
17.根据权利要求16所述的晶体管器件，其中，所述隔离区位于所述源极之下或附近。
18.根据权利要求16所述的晶体管器件，其中，所述隔离区位于所述栅极之下或附近。
19.根据权利要求16所述的晶体管器件，其中，所述隔离区位于所述源极和所述栅极之间。
20.根据权利要求16所述的晶体管器件，其中，所述隔离区位于所述栅极和所述漏极之间。
21.根据权利要求16所述的晶体管器件，还包括位于在所述栅极和所述漏极之间的所述沟道接入区之上的场板。
22.根据权利要求21所述的晶体管器件，其中，所述隔离区位于所述场板之下或附近。
23.根据权利要求16所述的晶体管器件，其中，所述栅极接触所述隔离区的表面。
24.根据权利要求16所述的晶体管器件，还包括接触所述隔离区的表面的金属电极。
25.根据权利要求16所述的晶体管器件，其中，所述器件是高压器件。
26.根据权利要求16所述的晶体管器件，其中，所述器件是III-N晶体管。
27.根据权利要求16所述的晶体管器件，其中，所述隔离区能收集在所述半导体材料中产生的空穴。
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