CN104134659A - 能够进行雪崩能量处理的iii族氮化物晶体管 - Google Patents

能够进行雪崩能量处理的iii族氮化物晶体管 Download PDF

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CN104134659A
CN104134659A CN201410185139.8A CN201410185139A CN104134659A CN 104134659 A CN104134659 A CN 104134659A CN 201410185139 A CN201410185139 A CN 201410185139A CN 104134659 A CN104134659 A CN 104134659A
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voltage drop
gan fet
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semiconductor device
assembly
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S·彭哈卡
N·特珀尔内尼
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Texas Instruments Inc
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Abstract

本发明涉及一种能够进行雪崩能量处理的III族氮化物晶体管。一种半导体器件(200)，包括带有过压箝位组件(212)的GaN FET(202)，该过压箝位组件(212)电耦合到GaN FET的漏极节点(204)并且串联耦合到电压降组件(220)。该电压降组件电耦合到为GaN FET提供截止状态偏压的端子。该过压箝位组件当在GaN FET的漏极节点处的电压小于GaN FET的击穿电压时导通微小的电流，并当该电压上升至安全电压极限以上时传导大量的电流。该电压降组件被配置为提供随着来自过压箝位组件的电流增加而增加的电压降。该半导体器件被配置为当电压降组件两端的电压降达到阈值时导通该GaN FET。

Description

能够进行雪崩能量处理的III族氮化物晶体管
技术领域
本发明涉及半导体器件领域。更具体地，本发明涉及半导体器件中的氮化镓FET。
背景技术
由III-N材料如GaN制成的场效应晶体管(FET)展示了电源开关所期望的特性，如与硅FET相比的高带隙和高热导率。然而，GaN FET在操作在击穿条件下时容易损坏，这可能会发生在非箝位感性开关的操作中。
发明内容
以下提出了简化的概述，以提供对本发明一个或多个方面的基本了解。该概述不是本发明的全面综述，并且既不旨在确定本发明的关键或决定性元件，也不旨在划定其范围。相反，该概述的主要目的是以简化的形式提出本发明的一些概念作为以下提出的更详细描述的前言。
一种半导体器件包括带有过压箝位组件的GaN FET，该过压箝位组件在一端电耦合到GaN FET的漏极节点。过压箝位组件的另一端电耦合到电压降组件的第一端。电压降组件的第二端电耦合到为GaNFET提供截止状态偏压的偏置电位的端子。过压箝位组件被配置为当在GaN FET的漏极节点处的电压小于安全电压极限时传导微小的电流，该安全电压极限小于GaN FET的击穿电压，例如为GaN FET的击穿电压的百分之80。过压箝位组件被进一步配置为当在GaN FET的漏极节点处的电压上升至安全电压极限以上时传导大量的电流。电压降组件被配置为提供一个随着来自过压箝位组件的电流增加而增加的电压降。半导体器件被配置为当电压降组件两端的电压降达到阈值时导通GaN FET。
在半导体器件的工作期间，当在GaN FET的漏极节点处的电压上升至安全电压极限以上时，过压箝位组件传导大量的电流，这致使电压降组件两端的电压降增大至阈值以上，从而导通GaN FET，使得GaNFET两端的电压降被保持在击穿电压以下。
附图说明
图1到图5为带有过压箝位组件和电压降组件的包含GaN FET的半导体器件的示例的电路图。
图6到图8为根据实施例的示例性GaN FET的剖面图。
图9到图12为带有电压降组件的示例的半导体器件的剖面图。
图13到图15为带有过压箝位组件的示例的半导体器件的剖面图。
具体实施方式
以下共同待决的专利申请与本申请相关，并通过引用并入本文：
美国专利申请12/xxx,xxx(与本申请同时申请，题为“III-NITRIDEENHANCEMENT MODE TRANSISTORS WITH TUNABLE ANDHIGH GATE-SOURCE VOLTAGE RATING；”的TI-71208)；
美国专利申请12/xxx,xxx(与本申请同时申请，题为“III-NITRIDETRANSISTOR LAYOUT；”的TI-71209)；
美国专利申请12/xxx,xxx(与本申请同时申请，题为“LAYERTRANSFER OF SI100ON TO III-NITRIDE MATERIAL FORHETEROGENOUS INTEGRATION；”的TI-71492)；
美国专利申请12/xxx,xxx(与本申请同时申请，题为“RESURFIII-NITRIDE HEMTS；”的TI-72417)；
美国专利申请12/xxx,xxx(与本申请同时申请，题为“METHOD TOFORM STEPPED DIELECTRIC FOR FIELD PLATE FORMATION；”的TI-72418)；以及
美国专利申请12/xxx,xxx(与本申请同时申请，题为“GaNDIELECTRIC RELIABILITY ENHANCEMENT.”的TI-72605)。
参考附图描述本发明。附图不是按比例绘制并且提供它们仅用于描述本发明。以下参考用于说明的示例应用描述了本发明的若干方面。应该理解的是，阐述许多具体细节、关系和方法以提供对本发明的理解。然而，相关领域的技术人员将容易地认识到，可以在不具有这些具体细节中的一种或多种的情况下或利用其它方法来实践本发明。在其它情况下，未详细地示出众所周知的结构或操作以避免模糊本发明。本发明并不限于所示的动作或事件的顺序，因为一些动作可以按照不同的顺序发生和/或与其它动作或事件同时发生。此外，并不是要求所有被示出的动作或事件来实施根据本发明的方法。
一种半导体器件包括带有过压箝位组件的GaN FET，该过压箝位组件在一端电耦合到GaN FET的漏极节点。过压箝位组件的另一端电耦合到电压降组件的第一端。电压降组件的第二端电耦合到为GaNFET提供截止状态偏压的偏置电位的端子。过压箝位组件被配置为当在GaN FET的漏极节点处的电压小于安全电压极限时传导微小的电流，该安全电压极限小于GaN FET的击穿电压，例如为GaN FET的击穿电压的百分之80。过压箝位组件进一步被配置为当在GaN FET的漏极节点处的电压上升至安全电压极限以上时传导大量的电流。电压降组件被配置为提供随着来自过压箝位组件的电流的增加而增加的电压降。半导体器件被配置为当电压降组件两端的电压降达到阈值时导通GaN FET。
在半导体器件的工作期间，当在GaN FET的漏极节点处的电压上升至安全电压极限以上时，过压箝位组件传导大量的电流，这致使电压降组件两端的电压降增大至阈值以上，从而导通GaN FET，使得GaNFET两端的电压被保持在击穿电压以下。
出于说明的目的，术语“III-N”应当理解为是指半导体材料，其中III族元素(即铝、镓和铟，还可能是硼)提供了半导体材料中的一部分原子并且氮原子提供半导体材料中剩余的原子。III-N半导体材料的示例为氮化镓、氮化硼镓、氮化铝镓、氮化铟以及氮化铟铝镓。描述材料的元素化学式的术语并不暗示元素的特定化学计量。III-N材料可用变量下标书写以表示可能的化学计量范围。例如，氮化铝镓可写成AlxGa1-xN，并且氮化铟铝镓可以写成InxAlyGa1-x-yN。出于说明的目的，术语GaN FET被理解为是指包括III-N半导体材料的场效应晶体管。
图1到图5为包含带有过压箝位组件和电压降组件的GaN FET的半导体器件示例的电路图。参照图1，半导体器件100包括增强模式GaN FET102，GaN FET102的漏极节点104连接到半导体器件100的漏极端106。GaN FET102的源极节点108连接到半导体器件100的源极端110。在图1中，半导体器件源极端110被示为接地端子。在本实施例的可替代版本中，半导体器件源极端110可被连接到电压源而不是接地。GaN FET102的击穿电压可为例如40伏到1500伏。
过压箝位组件112被连接在GaN FET102的漏极节点104和GaNFET102的栅极节点114之间。在图1中，过压箝位组件112被示为包括正向偏置二极管116和反向偏置二极管118的多个二极管。过压箝位组件112被配置为使得过压箝位组件112的击穿电压小于GaN FET102的击穿电压，例如为GaN FET102的击穿电压的百分之70到百分之90。过压箝位组件112可包括例如硅pn结二极管、硅肖特基二极管、GaN肖特基二极管、AlxGa1-xN肖特基二极管或InxAlyGa1-x-yN肖特基二极管。过压箝位组件112在反向偏置二极管118击穿时传导大量的电流。
电压降组件120被连接在半导体器件100的栅极节点114和源极端110之间。在图1中，电压降组件120被示为电阻器。来自过压箝位组件112的电流流过电压降组件112。选择电压降组件120的阻抗以当过压箝位组件112处于击穿时在栅极节点114处提供所需的导通状态偏压。半导体器件100的栅极端122可能通过可选的缓冲组件124电耦合到GaN FET102的栅极节点114。缓冲组件124可包括例如电阻器或二极管，该二极管具有耦合到栅极端122的阳极以及耦合到栅极节点114的阴极。
在半导体器件100的工作期间，可通过在栅极端122处施加合适的截止状态偏压而断开GaN FET102。如果漏极端106处的电压超过过压箝位组件112的击穿电压，则过压箝位组件112传导大量的电流，该电流流过电压降组件120以在栅极节点114处提供期望的导通状态电压，从而导通GaN FET102。处于导通状态的GaN FET102将漏极端106处的电压降至安全水平，从而使得GaN FET102不经历击穿。如果存在阻滞组件124的话，阻滞组件124可有利地减少在处于导通状态电压的栅极节点114和处于截止状态偏压的栅极端122之间的电流。
参照图2，半导体器件200包括一个耗尽模式GaN FET202，GaNFET202的漏极节点204连接到半导体器件200的漏极端206。GaN FET202的源极节点208连接到半导体器件200的源极端210，该源极端210可以是接地端。GaN FET202的击穿电压可为例如200伏到600伏。
过压箝位组件212被连接在GaN FET202的漏极节点204和GaNFET202的栅极节点214之间。在图2中，过压箝位组件212被示为多个正向二极管对216和反向二极管对218。过压箝位组件212被配置为使得例如参照图1所述的过压箝位组件212的击穿电压小于GaN FET202的击穿电压。过压箝位组件212在二极管对218的反向二极管击穿时传导大量的电流。
电压降组件220连接在半导体器件200的栅极节点214和源极端210之间。在图2中，电压降组件220被示为金属氧化物半导体(MOS)晶体管，在本实施例中为n沟道金属氧化物半导体(NMOS)晶体管，例如偏置成线性模式的硅NMOS晶体管。来自过压箝位组件212的电流流过电压降组件220。选择电压降组件220的阻抗以当过压箝位组件212处于击穿时在栅极节点214处提供期望的导通状态偏压。半导体器件200的栅极端222可能通过可选的缓冲组件224电耦合到GaN FET102的栅极节点214。缓冲组件224如参照图1的缓冲组件124所描述地而进行作用。
半导体器件200的工作类似于参照图1所讨论的半导体器件100的工作。电压降组件220中的NMOS晶体管的栅极偏压在过压箝位组件212的击穿期间可被调整以在GaN FET202的栅极节点214处提供期望的导通状态电压。
参照图3，半导体器件300包括耗尽模式GaN FET302，其中GaNFET302的漏极节点304连接到半导体器件300的漏极端306。GaN FET302的源极节点308通过NMOS晶体管326被连接到半导体器件300的源极端310，该源极端在图3中被示为接地端。GaN FET302的栅极节点314被连接到源极端310。NMOS晶体管326的栅极节点(可能通过缓冲组件324)电耦合到半导体器件300的栅极端322。GaN FET302的击穿电压可为例如200伏到600伏。NMOS晶体管326的击穿电压可以小于20伏。
过压箝位组件312连接在GaN FET302的漏极节点304和NMOS晶体管326的栅极节点之间。在图3中，过压箝位组件312被示为多个反向二极管318。过压箝位组件312被配置为例如如参照图1所述的使得过压箝位组件312的击穿电压小于GaN FET302的击穿电压。过压箝位组件312当二极管318击穿时传导大量的电流。
电压降组件320被连接在NMOS晶体管324的栅极节点和半导体器件300的源极端310之间。在图3中，电压降组件320被示为电阻器。来自过压箝位组件312的电流流过电压降组件320。选择电压降组件320的阻抗以当过压箝位组件312处于击穿时在NMOS晶体管324的栅极节点处提供期望的导通状态偏压。
在半导体器件300的工作期间，可通过在栅极端322施加断开NMOS晶体管324的合适的截止状态偏压而断开氮化镓场效应晶体302，导致GaN FET302的源极节点308上的电压上升，从而断开该GaN FET302。如果漏极端306处的电压超过过压箝位组件312的击穿电压，则过压箝位组件312传导大量的电流，该电流流过电压降组件320以在NMOS晶体管324的栅极节点处提供期望的导通状态电压。当NOMS晶体管324导通时，GaN FET302的源极节点308上的电压下降，这样导通了GaN FET302。处于导通状态的GaN FET302将漏极端306处的电压降到安全水平，从而使得GaN FET302不经历击穿。
参照图4，半导体器件400包括耗尽模式GaN FET402，其中GaNFET402的漏极节点404被连接到半导体器件400的漏极端406。GaNFET402的源极节点408被连接到半导体器件400的源极端410，该源极端可以是接地端。GaN FET402的击穿电压可为例如200伏到600伏。
过压箝位组件412被连接在GaN FET402的漏极节点404和GaNFET402的栅极节点414之间。在图4中，过压箝位组件412被示为包括正向偏置二极管416和反向偏置二极管418的多个二极管。过压箝位组件412被配置为例如如参照图1所描述的使得过压箝位组件412的击穿电压小于GaN FET402的击穿电压。过压箝位组件412可包括例如硅pn结二极管、硅肖特基二极管、GaN肖特基二极管、AlGaN肖特基二极管或InAlGaN肖特基二极管。过压箝位组件412在反向偏置二极管418击穿时传导大量的电流。
电压降组件420被连接在半导体器件400的栅极节点414和栅极端422之间。在图4中，电压降组件420被示为电阻器。来自过压箝位组件412的电流流过电压降组件420。选择电压降组件420的阻抗以当过压箝位组件412处于击穿时在栅极节点414处提供期望的导通状态偏压。
在半导体器件400的工作期间，可通过在栅极端422施加合适的截止状态偏压而断开GaN FET402。如果漏极端406处的电压超过过压箝位组件412的击穿电压，则过压箝位组件412传导大量的电流，该电流流过电压降组件420以在栅极节点414处提供期望的导通状态电压，从而导通GaN FET402。处于导通状态的GaN FET402将漏极端406处的电压降到安全水平，从而使得GaN FET402不经历击穿。
参照图5，半导体器件500包括增强模式GaN FET502，其中GaNFET502的漏极节点504被连接到半导体器件500的漏极端506。GaNFET502的源极节点508被连接到半导体器件500的源极端510，该源极端可以是接地端。
过压箝位组件512被连接在GaN FET502的漏极节点504和GaNFET502的栅极节点514之间。在图5中，过压箝位组件512被示为多个正向二极管516。过压箝位组件512被配置为使得以小于GaN FET502的击穿电压的导通电压传导大量的电流。正向二极管516被配置为以小于导通电压的漏极电压传导微小的电流。形成GaN的正向二极管516可以低于导通电压的漏极电压提供期望的电流极限。
电压降组件520被连接在半导体器件500的栅极节点514和栅极端522之间。在图5中，电压降组件520被示为金属氧化物半导体(MOS)晶体管，在该示例中为NMOS晶体管。来自过压箝位组件512的电流流过电压降组件520。选择电压降组件520的阻抗以当过压箝位组件512处于击穿时在栅极节点514处提供期望的导通状态偏压。
半导体器件500的工作类似于参照图4所讨论的半导体器件400的工作。电压降组件520中的NMOS晶体管的栅极偏压在过压箝位组件512的击穿期间可以被调整在以在GaN FET502的栅极节点514处提供期望的导通状态电压。
图6到图8为根据实施例的例如参考图1到图5所讨论的示例性GaN FET的剖面图。参照图6，耗尽模式GaN FET600被形成在硅衬底602上。失配绝缘层604被形成在硅衬底602上。失配绝缘层604可为例如100至300纳米的氮化铝。
缓冲层606被形成在失配绝缘层604上。缓冲层606可为例如1至7微米厚并包括AlxGa1-xN层积层的堆叠，其在失配绝缘层604处富含铝以及在缓冲层606的上表面处富含镓。
电绝缘层608被形成在缓冲层606上。电绝缘层608可为例如300纳米至2000纳米的半绝缘氮化镓。电绝缘层608可为例如半绝缘的以在低于电绝缘层608的层和高于电绝缘层608的层之间提供期望水平的电绝缘。
低缺陷层610被形成在电绝缘层608上。低缺陷层610可为例如25到1000纳米的氮化镓。可形成低缺陷层610以将可能对电子迁移率具有不利影响的晶体缺陷最小化，该晶体缺陷可能会导致低缺陷层610(例如以低于1017cm-3的掺杂浓度)被掺杂以碳、铁或其他掺杂剂种类。
阻挡层612被形成在低缺陷层610上。阻挡层612可为例如2至30纳米的AlxGa1-xN或InxAlyGa1-x-yN。阻挡层612的组成例如为百分之24至28的氮化铝和百分之72至76的氮化镓。在低缺陷层610上形成阻挡层612会在处于阻挡层612正下方的低缺陷层610中生成具有电子密度例如为1×1012至2×1013cm-2的二维电子气体。
可选的盖层614可以被形成在阻挡层612上。盖层614可以为例如2至5纳米的氮化镓。
栅极介电层616被形成在盖层614上方(如果存在盖层614的话)和阻挡层612上方。栅极介电层616可为例如通过低压化学汽相淀积(LPCVD)或等离子体增强化学气相沉积(PECVD)而形成的10至20纳米的氮化硅。在此示例的其他版本中，栅极介电层616可包括氮化硅、二氧化硅、氮氧化硅和/或氧化铝中的一层或多层。
栅极618被形成在栅极介电层616上。栅极618可为例如100至300纳米的钨或钨钛。可使用蚀刻工艺或者剥离工艺将栅极618图案化。
穿过栅极介电层616并延伸到阻挡层612中形成源极接触620，以在低缺陷层610中形成到二维电子气体的隧道连接。源极接触620可与栅极618横向地分离例如500至1500纳米。类似地，穿过栅极介电层616并延伸到阻挡层612中形成漏极接触622，从而形成到二维电子气体的隧道连接。漏极接触622与栅极618横向地分离取决于GaN FET600的最大工作电压的距离。例如，在设计用于200伏的最大工作电压的GaN FET600中，漏极接触622可与栅极618横向地分离1至8微米。在针对600伏的最大工作电压而设计的GaN FET600中，漏极接触622可与栅极618横向地分离3至20微米。硅衬底602可能被电连接到源极接触620，或者可能被电连接到漏极接触622。GaN FET600可以被形成在图6中所示的不同层结构之中和之上。通过在阻挡层612中形成栅极凹部以及在该栅极凹部中形成可选的盖层614、栅极介电层616和栅极618而可以形成增强模式GaN FET，从而更接近低缺陷层610的上表面放置栅极618的底表面。
增强模式GaN FET600在没有施加栅极偏压时是正常断开的，这可能对开关式电源应用或医学应用是有利的。在栅极618上相对于源极接触620的正偏压高于阈值电压将导通增强模式GaN FET600。相反，在栅极618上相对于源极接触620的偏压小于阈值电压将断开增强模式GaN FET600。在栅极618和二维电子气体之间形成栅极介电层616有利地为栅极偏置电压源提供了过电压保护的边缘。栅极618可被偏置为超过阈值若干伏而不损害增强模式GaN FET600。
参照图7，例如带有如参考图6所述的失配绝缘层704、缓冲层706、电绝缘层708、低缺陷层710、阻挡层712以及可能地可选的盖层714的耗尽模式GaN FET700被形成在硅衬底702上。在低缺陷层710上形成的阻挡层712在低缺陷层710中产生二维电子气体，低缺陷层710在阻挡层712正下方。如果盖层存在的话，金属栅极718被形成在盖层714上，或者如果不存在盖层，金属栅极被形成在阻挡层712上。可如参照图6所述形成金属栅极718。如参照图6所述，形成源极接触720和漏极接触722以与二维电子气体进行隧道连接。GaN FET700可以被形成在如图7中所示的不同层结构之中或之上。可通过在阻挡层712中形成栅极凹部以及在该栅极凹部中形成可选的盖层714和栅极718而形成增强模式GaN FET。
耗尽模式GaN FET700在没有施加栅极偏压时正常是导通的。在栅极718上相对于源极接触720的负偏压低于阈值电压将会断开耗尽模式GaN FET700。耗尽模式GaN FET700有利地比带有半导体栅极或栅极介电层的其他GaN FET具有更简单的制造顺序。
参照图8，增强模式GaN FET800被形成在硅衬底802上，如参照图6所述，其具有失配绝缘层804、缓冲层806、电绝缘层808、低缺陷层810、以及带有栅极凹部的阻挡层812以及可能地可选的盖层814。来自阻挡层812的压力在阻挡层812正下方的低缺陷层810中产生二维电子气体。如果盖层存在的话，在盖层814上形成p型半导体栅极818，或者如果没有形成盖层，则在阻挡层812上形成p型半导体栅极818。半导体栅极818包括如氮化镓、AlxGa1-xN、InxAlyGa1-x-yN、InxAl1-xN以及AlN的III-N半导体的一层或多层。半导体栅极818可以具有金属栅极盖826，其形成到半导体栅极818的欧姆或肖特基接触以改善电气性能。
如参照图6所述，形成源极接触820和漏极接触822以便与二维电子气体进行隧道连接。GaN FET800可以被形成在图8所示的不同层结构之中和之上。可以通过省略栅极凹部形成耗尽模式GaN FET。
增强模式GaN FET800以类似于图6的增强模式GaN FET600的方式工作。半导体栅极818上的导通状态偏压被限制为大约6伏，以免诱导过多栅极电流通过半导体栅极818和阻挡层812之间的pn结。与其他增强模式GaN FET架构相比，半导体栅极818可有利地为增强模式GaN FET800提供更高的可靠性。
图9到图12为带有参照图1到图5所述的电压降组件的示例的半导体器件的剖面图。参照图9，半导体器件900被形成在硅衬底902之中和之上。在硅衬底902中形成阱电阻器928形式的电压降组件；阱电阻器928具有与硅衬底902相反的导电类型。形成电阻器接触930以将阱电阻器928电连接到GaN FET934。可以在场氧化物932下方形成阱电阻器928以提供所需的薄层电阻。可以例如通过离子注入形成阱电阻器928。阱电阻器928可与图9中所示的GaN FET934集成，或可以被形成在分离的衬底上。可替代地，阱电阻器928可以被形成在GaN FET934的III-N半导体层上方形成的硅层中。与其他电阻配置相比，将电压降组件形成为阱电阻器可以提供期望的可靠性和电流容量。
参照图10，半导体器件1000被形成在硅衬底1002之中和之上。薄膜电阻器1028形式的电压降组件被形成在硅衬底1002上方，可能形成在场氧化物1032上方。形成电阻器接触1030以将薄膜电阻器1028电连接到GaN FET1034。薄膜电阻器1028可以具有通常被称为多晶硅的多晶硅的电阻体、例如镍铬合金或硅铬合金的难熔金属或适于形成薄膜电阻器1028的其他导电材料。薄膜电阻器1028可与图10中所描示的GaN FET1034集成，或可以形成在分离衬底上。可替代地，薄膜电阻器1028可以被形成在GaN FET1034的III-N半导体层上方形成的硅层上。与其他电阻配置相比，将电压降组件形成为薄膜电阻器可以提供期望的薄层电阻的灵活性。
参照图11，半导体器件1100被形成在硅衬底1102之中和之上。金属氧化物半导体(MOS)晶体管1128形式的电压降组件被形成在硅衬底1102之中及之上，可能形成在可选的阱1136中。形成源极和漏极接触1130以将MOS晶体管1128电连接到GaN FET1134。MOS晶体管1128可以为NMOS晶体管或p沟道金属氧化物半导体(PMOS)晶体管。MOS晶体管1128可以被偏置为处于一直导通的状态，或可以依赖于流过串联连接的过压箝位组件(未示出)的电流而被偏置。MOS晶体管1128可与图11所描述的GaN FET1134集成，或可以被形成在分离的衬底上。可替代地，MOS晶体管1128可以被形成于在GaN FET1134的III-N半导体层上方形成的硅层上。与固定电阻器相比，将电压降组件形成为MOS晶体管可以提供灵活的电压降行为。
参照图12，半导体器件1200被形成在硅衬底1202之中和之上。III-N半导体材料的层堆叠被形成在硅衬底上以便支撑GaN FET1234和二维电子气体电阻器1228从而为GaN FET1234提供电压降组件。III-N半导体材料的层堆叠可包括参照图6所讨论的示例性的层：失配绝缘层1204、缓冲层1206、电绝缘层1208、低缺陷层1210、阻挡层1212、可能地可选的盖层1214以及可能地如氮化硅的可选介电层1216。来自阻挡层1212的压力在阻挡层1212正下方的低缺陷层1210中生成二维电子气体。二维电子气体的一部分在GaN FET1234中形成沟道导电层。二维电子气体的另一部分在二维电子气体电阻器1228中形成电阻体。二维电子气体电阻器1228可具有例如每平方300至5000欧姆的薄层电阻率。形成电阻器接触1230以与形成电阻体的二维电子气体进行隧道连接。二维电子气体电阻器1228可以可选地被隔离在如图12中所示的台面结构中，或者可以为整体架构的一部分。形成二维电子气体电阻器1228以使用GaN FET1234所使用的相同二维电子气体的一部分，这比其他集成配置可以提供半导体器件1200的更简单的和更低成本的制造工艺顺序。
图13到图15为带有参照图1到图5所示的过压箝位组件的示例的半导体器件的剖面图。参照图13，半导体器件1300被形成在硅衬底1302之中或之上。如参照图6所述，例如具有失配绝缘层1304、缓冲层1306、电绝缘层1308、低缺陷层1310、阻挡层1312、可选的盖层1314、可选的栅极介电层1316、栅极1318、源极接触1320和漏极接触1322的GaN FET1334被形成在硅衬底1302上。
在硅衬底1302之中和之上形成多个正向和反向肖特基二极管对1336形式的过压箝位组件。肖特基二极管1336包括硅衬底1302中的n型掺杂区域1338，这些n型掺杂区域提供肖特基二极管1336的阴极。掺杂区域1338上的金属或金属硅化物层1340提供了肖特基二极管1336的阳极。掺杂区域1338可通过场氧化物1342横向地绝缘。如图13中所示的，正向和反向肖特基二极管对1336例如通过半导体器件1300的金属互连而串联地电连接。二极管接触1344被形成在多个肖特基二极管对1336的端部二极管上以便提供到GaN FET1334的电连接。可替代地，多个正向和反向肖特基二极管对1336可以被形成在GaNFET1334的III-N半导体层上方形成的硅层上。与其他配置相比，将过压箝位组件形成为硅肖特基二极管可在制造的简单性和电流容量之间提供期望的平衡。
参照图14，半导体器件1400被形成在硅衬底1402之中和之上。如参照图6所述，例如具有失配绝缘层1404、缓冲层1406、电绝缘层1408、低缺陷层1410、阻挡层1412、可选的盖层1414、栅极1418、源极接触1420和漏极接触1422的GaN FET1434被形成在硅衬底1402上。在低缺陷层1410和阻挡层1412中形成多个正向和反向III-N二极管对1436形式的过压箝位组件。二极管1336包括在低缺陷层1410中的n型台面区域，其提供二极管1436的阴极。在低缺陷层1410中的台面区域上的阻挡层1412的P型岛提供二极管1436的阳极。如图14中所示的，正向和反向肖特基二极管对1436例如通过半导体器件1400的金属互连而串联地电连接。二极管接触1442被形成在多个二极管对1436的端部二极管上以便提供到GaN FET1434的电连接。与其他配置相比，将过压箝位组件形成为III-N二极管可有利地降低半导体器件1400的制造成本和复杂性。
参照图15，半导体器件1500被形成在硅衬底1502之中和之上。如参照图7所述，例如具有失配绝缘层1504、缓冲层1506、电绝缘层1508、低缺陷层1510、阻挡层1512、盖层1514、该阻挡层1512上的金属栅极层的金属栅极1518、源极接触1520和漏极接触1522的GaNFET1534被形成在硅衬底1502上。在阻挡层1512之中和之上形成多个正向和反向III-N肖特基二极管对1536形式的过压箝位组件。肖特基二极管1536包括阻挡层1512中的多个台面区域，这些台面区域提供二极管1536的阴极。在阻挡层1512中的台面区域上的金属栅极层的金属岛1546提供了二极管1536的阳极。如图15中所示的，正向和反向肖特基二极管对1536被串联地电连接。二极管接触1542被形成在多个二极管对1536的端部二极管上以便提供到GaN FET1534的电连接。与其他配置相比，将过压箝位组件形成为III-N肖特基二极管可以有利地降低带有金属栅极1518的半导体器件1500的制造成本和复杂性。
虽然以上已经描述了本发明的各种实施例，应该理解的是，它们仅以示例的方式给出，而不是限制性的。可根据披露对所披露的实施例进行多次修改而不背离本发明的精神或范围。因此，本发明的广度和范围不应受到任何上述实施例的限制。相反，本发明的范围应根据以下的权利要求书及其等价物所限定。

Claims (20)

1.一种半导体器件，其包括：
氮化镓场效应晶体管即GaN FET；
过压箝位组件，所述过压箝位组件的第一端被电耦合到所述GaN FET的漏极节点，所述过压箝位组件被配置为当在所述漏极节点处的电压小于安全电压极限时传导微小的电流，该安全电压极限小于所述GaNFET的击穿电压；所述过压箝位组件被进一步配置为当在所述GaNFET的所述漏极节点处的所述电压上升至所述安全电压极限以上时传导大量的电流；以及
电压降组件，所述电压降组件的第一端被电耦合到所述过压箝位组件的第二端，所述电压降组件的第二端被电耦合到为所述GaN FET提供截止状态偏压的偏置电位的端子，所述电压降组件被配置为提供电压降，该电压降随着来自所述过压箝位组件的电流增加而增加；
所述半导体器件被配置为当所述电压降组件两端的所述电压降达到阈值时导通所述GaN FET。
2.根据权利要求1所述的半导体器件，其中：
所述电压降组件的所述第一端电耦合到所述GaN FET的栅极节点；以及
所述电压降组件的所述第二端电耦合到所述半导体器件的栅极端。
3.根据权利要求1所述的半导体器件，其中：
所述GaN FET是耗尽模式GaN FET；
所述GaN FET的源极节点电耦合到n沟道金属氧化物半导体晶体管即NMOS晶体管的漏极节点；
所述GaN FET的栅极节点电耦合到所述NMOS晶体管的源极节点；以及
所述电压降组件的所述第二端电耦合到所述NMOS晶体管的栅极节点。
4.根据权利要求1所述的半导体器件，其中所述过压箝位组件包括串联电耦合的多个二极管。
5.根据权利要求4所述的半导体器件，其中所述多个二极管被配置为多个正向和反向二极管对。
6.根据权利要求4所述的半导体器件，其中所述二极管被形成在包括氮化镓的低缺陷层和包括AlxGa1-xN的阻挡层中，所述GaN FET被设置在所述低缺陷层和所述阻挡层的一部分中。
7.根据权利要求4所述的半导体器件，其中所述二极管被形成在包括AlxGa1-xN的阻挡层和金属栅极层中，所述GaN FET被设置在所述阻挡层的一部分内并且具有所述金属栅极层的金属栅极。
8.根据权利要求1所述的半导体器件，其中所述电压降组件是电阻器。
9.根据权利要求8所述的半导体器件，其中所述电阻器在包括氮化镓的低缺陷层中的二维电子气体中具有电阻体，所述GaN FET被设置在所述低缺陷层的一部分中并且具有在所述二维电子气体中的沟道导电层。
10.根据权利要求1所述的半导体器件，其中所述电压降组件是金属氧化物半导体晶体管即MOS晶体管。
11.一种形成半导体器件的方法，该方法包括以下步骤：
通过包括以下步骤的工艺形成GaN FET：
提供衬底；
在所述衬底上方形成包括氮化镓的低缺陷层；
在所述低缺陷层上形成包括AlxGa1-xN的阻挡层，使得二维电子气体被产生在所述阻挡层正下方的所述低缺陷层中，所述二维电子气体提供所述GaN FET的导电沟道；
在所述阻挡层的上方形成栅极；以及
形成源极和漏极接触以与所述二维电子气体进行隧道连接；
形成过压箝位组件，并且将所述过压箝位组件的第一端电耦合到所述GaN FET的漏极节点，所述过压箝位组件被配置为当所述漏极节点处的电压小于安全电压极限时传导微小的电流，该安全电压极限小于所述GaN FET的击穿电压；所述过压箝位组件被进一步配置为当在所述GaN FET的所述漏极节点处的所述电压上升至所述安全电压极限以上时传导大量的电流；
形成电压降组件，将所述电压降组件的第一端电耦合到所述过压箝位组件的第二端，并且将所述电压降组件的第二端电耦合到为所述GaNFET提供截止状态偏压的偏置电位的端子，所述电压降组件被配置为提供电压降，该电压降组件被配置为随着来自所述过压箝位组件的电流增加而增加；以及
将所述半导体器件配置为当所述电压降组件两端的所述电压降达到阈值时导通所述GaN FET。
12.根据权利要求11所述的方法，进一步包括以下步骤：
将所述电压降组件的所述第一端电耦合到所述GaN FET的栅极节点；以及
将所述电压降组件的所述第二端电耦合到所述半导体器件的栅极端。
13.根据权利要求11所述的方法，其中所述GaN FET是耗尽模式GaNFET，并且进一步包括以下步骤：
将所述GaN FET的源极节点电耦合到n沟道金属氧化物半导体晶体管即NMOS晶体管的漏极节点；
将所述GaN FET的栅极节点电耦合到所述NMOS晶体管的源极节点；以及
将所述电压降组件的所述第二端电耦合到所述NMOS晶体管的栅极节点。
14.根据权利要求11所述的方法，其中所述过压箝位组件包括串联电耦合的多个二极管。
15.根据权利要求14所述的方法，其中所述多个二极管被配置为多个正向和反向二极管对。
16.根据权利要求14所述的方法，其中所述二极管被形成在包括氮化镓的低缺陷层和包括AlxGa1-xN的阻挡层中，所述GaN FET被设置在所述低缺陷层和所述阻挡层的一部分中。
17.根据权利要求14所述的方法，其中所述二极管被形成在包括AlxGa1-xN的阻挡层和金属栅极层中，所述GaN FET被设置在所述阻挡层的一部分中，并且具有所述金属栅极层的金属栅极。
18.根据权利要求11所述的方法，其中所述电压降组件是电阻器。
19.根据权利要求18所述的方法，其中所述电阻器在包括氮化镓的低缺陷层中的二维电子气体中具有电阻体，所述GaN FET被设置在所述低缺陷层的一部分内并在所述二维电子气体中具有沟道导电层。
20.根据权利要求11所述的方法，其中所述电压降组件是金属氧化物半导体晶体管即MOS晶体管。
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