TWI443824B - 形成具彼此相連接之屏蔽電極和閘極電極的遮蔽閘極溝槽式場效電晶體之結構及方法 - Google Patents

形成具彼此相連接之屏蔽電極和閘極電極的遮蔽閘極溝槽式場效電晶體之結構及方法 Download PDF

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TWI443824B
TWI443824B TW096118749A TW96118749A TWI443824B TW I443824 B TWI443824 B TW I443824B TW 096118749 A TW096118749 A TW 096118749A TW 96118749 A TW96118749 A TW 96118749A TW I443824 B TWI443824 B TW I443824B
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Nathan Kraft
Christopher Boguslaw Kocon
Paul Thorup
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Fairchild Semiconductor
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Description

形成具彼此相連接之屏蔽電極和閘極電極的遮蔽閘極溝槽式場效電晶體之結構及方法 發明背景
本發明係一般係有關於半導體場效電晶體(FET)，且更特別係在於帶有彼此相連之屏蔽電極與閘電極的遮蔽閘極溝槽式FET。
遮蔽閘極溝槽式FET優於習用之FET，因為屏蔽電極使閘極－汲極電容(Cgd)降低，並增進電晶體之崩潰電壓。第1圖係為一習用遮蔽閘極溝槽式金屬氧化物半導體場效電晶體(MOSFET)之簡化的橫剖面圖。一n型磊晶層102在一n＋基板100上延伸。n＋源極區域108以及p＋濃稠本體區域106係形成於一p型本體區域104中，其接著形成於一磊晶層102中。溝槽110延伸通過本體區域104，並且終止於漂移區域中。溝槽110包括一個位於一閘電極122下方之屏蔽電極114。閘電極122係藉由閘極電介質120而與其相鄰的矽區域分隔，且屏蔽電極114係藉由一屏蔽電介質112而與其相鄰的矽區域隔離。
閘電極與屏蔽電極係藉由一電介質層116彼此隔開，該電介質層亦稱之為電極間電介質或IED。IED層116必須具有足夠的品質與厚度，以便支撐屏蔽電極114與閘電極122之間所存在的電位差異。另外，IED層116中或是屏蔽電極114與IED層116之間的介面中之介面陷阱電荷以及電介質陷阱電荷主要係與用以形成IED層的方法有關。
IED典型係藉由各種不同的處理方法所形成。然而，為了確保一足夠堅固與可靠，以便提供所需的電子特徵之高品質IED，導致了用以形成遮蔽閘極溝槽式FET之複雜程序。因此，對於形成屏蔽閘電極溝槽式FET之構造與方法具有需求，其能夠消除對於一高品質IED的要求，同時維持或改進諸如導通阻抗(on－resistance)之此等電子特徵。
 發明概要
根據本發明之一實施例，一種場效電晶體包括複數個延伸進入一半導體區域中之溝槽。各個溝槽包括一閘電極以及一屏蔽電極，且其間具有一電極間電介質，其中該屏蔽電極與閘電極係彼此電性連接。
在一實施例中，屏蔽電極位於各個溝槽之下方部分中，且藉由一屏蔽電介質與半導體區域隔離。一電極間電介質延伸於各個屏蔽電極上方。閘電極係位於電極間電介質上的各個溝槽之一上方部分中，且係藉由一閘電介質與半導體區域隔離。
在另一實施例中，半導體區域包括一第一傳導類型之漂移區域、一第二傳導類型之本體區域延伸於該漂移區域上，以及在本體區域中鄰接溝槽的第一傳導類型之源極區域。
在另一實施例中，半導體區域進一步包括一第一傳導類型之基板，且漂移區域延伸於該基板上，其中該等溝槽延伸通過本體區域，並且終止於漂移區域中。
在另一實施例中，該等溝槽延伸通過本體區域以及漂移區域，並且終止於基板內。
在另一實施例中，場效電晶體進一步包括其中形成該等溝槽之一活動區域以及一非作用區域。屏蔽電極以及閘電極延伸離開各個溝槽，並且進入非作用區域，屏蔽電極與閘電極於該處係藉由一閘極互連層彼此電性連接。
在另一實施例中，屏蔽電極與閘電極之間的電性連接係透過形成於非作用區域之一閘滑槽區域中的週期性連接開口達成。
在另一實施例中，屏蔽電極係藉由一透過各個溝槽中的電介質間層之額外連接而連接到閘電極。
在另一實施例中，該非作用區域包括一沿著一容納FET之晶粒的周圍延伸之終止區域，屏蔽電極與閘電極延伸離開各個溝槽，並且進入終止區域，屏蔽電極與閘電極於該處係藉由一閘極互連層彼此電性連接。
依照本發明之另一實施例，一場效電晶體係以下述方式所形成。複數個溝槽係形成延伸進入一半導體區域；一屏蔽電極係形成於各個溝槽之一底部部分中；一閘電極係形成於屏蔽電極上的各個溝槽之一上方部分中；形成一電性連接該屏蔽電極與閘電極之閘極互連層。
在一實施例中，一襯墊下方側壁以及各底部表面之屏蔽電介質層係在形成屏蔽電介質之前形成。一襯墊上溝槽側壁及屏蔽電極之一表面的電介質層係在形成閘電極之前形成。
在另一實施例中，屏蔽電極與閘電極係形成，以致於使屏蔽電極與閘電極二者皆延伸離開溝槽，並且越過一平頂區域。複數個接觸開口係形成於延伸越過平頂區域之閘電極的部分中，以便透過該等接觸開口暴露出屏蔽電極之表面區域。互連層係形成，以便充填該等接觸開口，藉以使屏蔽電極與閘電極彼此電性連接。
在另一實施例中，該平頂區域係位於一容納FET之晶粒的一非作用區域中。
在另一實施例中，電介質層係由矽之氧化所形成。
在另一實施例中，一個或更多開口係在形成閘電極之前形成於延伸越過屏蔽電極之電介質層的一部份中，以致於一旦於溝槽中形成閘電極，該閘電極便會透過一個或更多開口電性連接屏蔽電極。
圖式簡單說明
第1圖係為一習用遮蔽閘極溝槽式MOSFET之一橫剖面圖；第2A~2H圖係為根據本發明之一實施例，用以形成一屏蔽閘極溝槽式FET之一程序在各個不同步驟的簡化橫剖面圖；及第3圖係為根據本發明之一實施例，位於一屏蔽閘極溝槽式FET中之一閘滑槽的一部份之一等角視圖。
 較佳實施例之詳細說明
第2A~2H圖係為根據本發明之一實施例，用以形成一屏蔽閘極溝槽式FET之一程序在各個不同步驟的簡化橫剖面圖。在第2A~2H圖中，左側橫剖面圖顯示導致在作用區域中形成屏蔽閘極溝槽式FET構造之步驟的順序，且右側橫剖面圖顯示從作用區域到非作用區域(從右到左)之一過渡區域的對應圖式。在此揭露內容中，「作用區域」表示一晶粒含有作用胞體之的區域，且「非作用區域」表示該晶粒不包括任何作用胞體之區域。非作用區域包括沿著晶粒之周圍延伸的終止區域，以及沿著晶粒之周圍或中間延伸，或者是沿著晶粒之周圍與中間二者延伸的閘極滑槽。
在第2A圖中，溝槽210係使用習用技術形成於一半導體區域202中，且接著一屏蔽電介質212(例如包含氧化物)係形成，其襯墊著溝槽側壁與底部表面，並且延伸越過鄰接溝槽之平頂區域。第2A~2H圖中之右側橫剖面圖係通過左側橫剖面圖的溝槽中央，沿著垂直於該等左側橫剖面圖之方向所取得。因此，右側橫剖面圖顯示出左側橫剖面圖之溝槽終止於作用區域的邊緣。另外，該等橫剖面圖並非按比例繪出，且尤其係在於，右側與左側橫剖面圖中之相同層或區域的實體尺寸(例如厚度)看起來可能會不同。例如，第2A圖中，右側橫剖面中之屏蔽電介質212看起來較左側橫剖面圖式為薄。
如第2A圖之右側橫剖面圖中所示，屏蔽電介質212沿著溝槽210之底部表面延伸，並且在作用區域之邊緣向上延伸，且離開溝槽210，並越過矽區域202。在一實施例中，半導體區域202包括一n型磊晶層(未顯示)，其形成於一高度摻雜之n型基板(未顯示)中、以及溝槽210，其延伸進入磊晶層，並終止於磊晶層內。在另一變化形式中，溝槽210延伸通過磊晶層，並且終止於基板內。
在第2B圖中，屏蔽電極214係沿著溝槽210之一底部部分形成，並且以如下述方式使晶粒之非作用區域中得到電子接觸。使用已知技術，首先形成一傳導材料(例如包含摻雜或未摻雜之聚矽)充填溝槽，並且延伸越過平頂區域，及接著使其深陷進入溝槽210，以便形成屏蔽電極214。
在使傳導材料產生凹陷期間係使用一遮罩211，用以保護傳導材料延伸在晶粒之非作用區域中的部分。結果，在晶粒之非作用區域中，位於溝槽210內側中的屏蔽電極214係較平頂表面上者為厚，如第2B圖中之右側橫剖面圖中所示。另外使用遮罩211，以致於使屏蔽電極在作用區域之邊緣延伸離開溝槽210，並且越過非作用區域之平頂表面。因此位於溝槽210內側之屏蔽電極214能夠對於晶粒之非作用區域中提供電性連接性。
在第2C圖中，利用已知方法從沿著溝槽側壁以及作用區域中之平頂表面上移除屏蔽電極212，如同右側橫剖面圖所示。屏蔽電介質因此凹陷程度會低於屏蔽電極214的頂部表面。在一實施例中，屏蔽電極214係產生凹陷，以致於使其頂部表面與屏蔽電介質層212的表面共平面。如此對於後續形成閘極/電極間電介質層提供一平坦表面。
在第2D圖中，一沿著上溝槽側壁延伸之閘極電介質層216係使用習用技術形成。此程序亦導致屏蔽電極214之氧化，從而在閘電極214上方形成一電極間電介質(IED)層。如右側橫剖面圖中所示，電介質層216沿著作用與非作用區域中的屏蔽電極214之所有暴露表面延伸。如以下進一步之說明，對於形成一高品質IED典型所需要之額外的處理步驟係能夠省略。
在第2E圖中，凹陷閘電極222係形成於溝槽210中，並且以下述方式使其能夠在非作用區域中電子接觸。使用習用技術，形成一第二傳導層(例如包含摻雜聚矽)充填溝槽210，並且延伸越過晶粒之作用區域與非作用區域中的平頂表面。該第二傳導層接著係凹陷進入溝槽210中，以形成閘電極222。
在第二傳導層凹陷期間係使用一遮罩219，用以保護第二傳導材料在晶粒之非作用區域中延伸的部分。結果，在晶粒之非作用區域中，位於溝槽210內側中的閘電極222係較平頂表面上者為厚，如第2B圖中之右側橫剖面圖中所示。另外使用遮罩219，以致於使凹陷閘電極222在作用區域之邊緣處延伸離開溝槽210，並且越過非作用區域的平頂表面。因此位於溝槽210內側之閘電極222能夠對於晶粒之非作用區域中提供電性連接性。注意到的是，遮罩219在非作用區域中並未延伸越過整個屏蔽電極214。如以下即將所見者，如此有助於透過相同的接觸開口使閘電極與屏蔽電極二者相接觸。
在第2E圖中，p型本體區域204係使用習用本體植入以及驅入技術形成於半導體區域202中。高度摻雜之n型源極區域208接著係使用習用的源極植入技術形成於鄰近溝槽210之本體區域216中。
在第2F圖中，一諸如硼磷矽玻璃(BPSG)之電介質層224係使用已知技術形成於構造上方。在第2G圖中，電介質層224係產生圖案並進行蝕刻，以便在作用區域中形成源極/本體接觸開口，接著進行電介質流。如左側橫剖面圖中所示，一延伸完全覆蓋閘電極222，且部分地覆蓋源極區域208之電介質圓頂225係形成。p型濃稠本體區域206接著係使用習用植入技術形成於暴露的半導體區域202中。使用與用以在作用區域中形成接觸開口相同的遮罩/蝕刻程序，在非作用區域中之電介質層224內形成一接觸開口221，以便暴露出閘電極222之一表面區域與側壁以及屏蔽電極214的一表面區域，如右側橫剖面圖中所示。
在第2H圖中，一互連層(例如包含金屬)係形成於構造上方，且接著使其產生圖案，以便形成源極/本體互連226A以及閘極互連226B。如左側橫剖面圖中所示，源極/本體互連226A與源極區域208以及濃稠本體區域206相接觸，但藉由電介質圓頂224與閘電極222隔開。如右側橫剖面圖中所示，閘極金屬226B透過接觸開口221與屏蔽電極214以及閘電極222相接觸，從而使兩電極彼此短路。
因此，與其中屏蔽電極係浮動(亦即未電子偏壓)或偏壓到源極電位(例如接地電位)之習用屏蔽閘FET相反，在第2H圖中所示之FET中，屏蔽電極係連接且偏壓到與閘電極相同的電位。在其中屏蔽電極係浮動或連接到接地電位之習用FET中，典型係需要一高品質IED支撐屏蔽電極與閘電極之間的電位差異。然而，將屏蔽電極與閘電極彼此電性連接則消除了對於高品質IED的需求。儘管偏壓到閘極電位，屏蔽電極仍然係以一電荷平衡構造運作，對於相同的崩潰電壓而言，如此能夠使得導通阻抗降低。因此，對於相同崩潰電壓獲得一低導通阻抗，同時去除了與形成一高品質IED有關之處理步驟。理論上而言，此一構造甚至不需要一IED，但是IED會在閘極電介質形成期間自然形成。因此，使用一簡單的製造程序便能夠形成一高性能之電晶體。
閘電極與屏蔽電極之間的電子接觸能夠在任何的非作用區域中形成，諸如在晶粒之邊緣區域的終端中，或者在如第3圖中所示閘極滑槽延伸之晶粒中間處。第3圖係為根據本發明之一實施例的一屏蔽閘極溝槽式FET中之一閘極滑槽的一部份之一等角視圖。上層(例如閘極互連層326B以及電介質層324)係加以剝開，以便顯示下方的構造。如圖所示，平行於作用區域341延伸之溝槽310終止於閘極滑槽區域340的兩側。
閘極滑槽區域340在結構上係對稱於線段3－3，且各半部於構造上係類似第2H圖中所示者。屏蔽電介質312延伸離開溝槽310列，並且到達位於閘極滑槽區域340中之平頂表面上。同樣的，屏蔽電極314、電極間電介質316以及閘電極322延伸離開溝槽310列，並且到達位於閘極滑槽區域340中之平頂表面上。區域311代表作用區域341中相鄰溝槽之間的平頂。
接觸開口321暴露出屏蔽電極314之表面區域，閘極互連層326B(例如包含金屬)與該處產生電子接觸。此外，閘極互連層326B與閘電極322暴露通過電介質層324之表面區域332產生電子接觸。希望使閘極阻抗減到最小，以便使溝槽中之各個閘電極的偏壓延遲減到最短。同樣的道理，希望使溝槽中各個屏蔽電極之偏壓延遲減到最短。因此，位於閘極滑槽區域340中之接觸開口321的間隔頻率與形狀能夠進行最佳化，以便將阻抗降到最低，從而將閘極墊片到各個閘電極與屏蔽電極之延遲減到最短。能夠藉著在閘極滑槽區域中以及晶粒的終端或邊緣區域中形成閘電極對屏蔽電極之接點，進一步縮短屏蔽電極與閘電極之偏壓延遲。
根據本發明之其他實施例，屏蔽電極與閘電極能夠以其他方式進行電性連接。例如，位於各個溝槽中之IED能夠在IED上形成閘電極之前於某些位置進行蝕刻。在此實施例中，將不需要如第2H圖與第3圖中所示之接觸開口，且連接到各個溝槽中之閘電極的一閘極互連亦透過IED中之短路結合到對應的屏蔽電極。根據其他實施例，閘電極與屏蔽電極接觸能夠透過IED中之開口，以及透過形成於諸如終端與閘極滑槽區域之非作用區域中的接觸開口形成。摒除了對於形成一高品質IED之需求，導致一種簡化且更能夠加以控制之程序，用以形成具有改進汲極－源極導通阻抗(RDSon )之屏蔽閘極溝槽式MOSFET。
本發明之原理能夠應用於任何類型的屏蔽閘極FET構造，諸如專利申請案第11/026,276號，標題為「電力半導體裝置及其製造方法」之第3A、3B、4A、4C、6~8、9A~9C、11、12、15、16、24以及26A~26C圖中所示者，其揭露內容係由於所有目的完整併入本文中做為參考之用。
儘管以上提供本發明之較佳實施例的完整描述，許多另擇方式、修改以及相等物亦為可行。熟諳此技藝之人士將會體認到的是，同樣的技術能夠應用到其他類型的超結合技術構造，以及更廣義的應用於包括橫向裝置之其他類型的裝置。例如，儘管本發明之實施例於文中係描述n型通道MOSFET，本發明之原理能夠僅藉著反轉不同區域之傳導類型而應用到p型通道MOSFET。所以，上述說明不應視為本發明之範疇的限制，本發明之範疇係由所附申請專利範圍加以界定。
100．．．基板
102．．．磊晶層
104．．．本體區域
106．．．濃稠本體區域
108．．．源極區域
110．．．溝槽
112．．．屏蔽電介質
114．．．屏蔽電極
116．．．電介質層
120．．．閘極電介質
122．．．閘電極
202．．．半導體區域
204．．．本體區域
206．．．濃稠本體區域
208．．．源極區域
210．．．溝槽
211．．．遮罩
212．．．屏蔽電介質
214．．．屏蔽電極
216．．．閘極電介質層
219．．．遮罩
221．．．接觸開口
222．．．閘電極
224．．．電介質層
225．．．電介質圓頂
226A．．．源極/本體互連
226B．．．閘極互連
310．．．溝槽
311．．．區域
312．．．屏蔽電介質
314．．．屏蔽電極
316．．．電極間電介質
321．．．接觸開口
322．．．閘電極
324．．．電介質層
326B．．．閘極互連層
332．．．表面區域
340．．．閘極滑槽區域
341．．．作用區域
第1圖係為一習用遮蔽閘極溝槽式MOSFET之一橫剖面圖；第2A~2H圖係為根據本發明之一實施例，用以形成一屏蔽閘極溝槽式FET之一程序在各個不同步驟的簡化橫剖面圖；及第3圖係為根據本發明之一實施例，位於一屏蔽閘極溝槽式FET中之一閘滑槽的一部份之一等角視圖。
204．．．本體區域
206．．．濃稠本體區域
208．．．源極區域
210．．．溝槽
212．．．屏蔽電介質
214．．．屏蔽電極
216．．．閘極電介質層
222．．．閘電極
224．．．電介質層
226A．．．源極/本體互連
226B．．．閘極互連

Claims (33)

  1. 一種場效電晶體(FET)，其包含：一溝槽，其延伸進入一半導體區域，該溝槽係設置在一作用區域中；一屏蔽電極，其設置於該溝槽之一下方部分中，該屏蔽電極係藉由一屏蔽電介質與該半導體區域隔離；一電極間電介質(IED)，其設置於該屏蔽電極上方；一閘電極，其設置於該IED上方的該溝槽之一上方部分中，該閘電極係藉由一閘極電介質與該半導體區域隔離，該屏蔽電極及該閘電極延伸離開該溝槽且進入一非作用區域；及；一閘極互連層，其使該閘電極與該屏蔽電極電性連接，該閘極互連層係設置於該非作用區域中。
  2. 如申請專利範圍第1項之FET，其中該半導體區域包含：一第一傳導類型之漂移區域；一第二傳導類型之本體區域，其設置於該漂移區域上方；及該第一傳導類型之多個源極區域，其設置於該本體區域中鄰接該溝槽處。
  3. 如申請專利範圍第2項之FET，其中該閘電極在該溝槽中係凹陷成低於該半導體區域的一頂部表面，且該FET進一步包含：一接觸該等源極區域與該本體區域之互連層；及一電介質材料，其設置於該閘電極上，該電介質材 料使該閘電極與該互連層隔離。
  4. 如申請專利範圍第2項之FET，其進一步包含一第一傳導類型之基板，該漂移區域係設置於該基板上方，該溝槽延伸通過該本體區域，且終止於該漂移區域中。
  5. 如申請專利範圍第2項之FET，其進一步包含一第一傳導類型之基板，該漂移區域係設置於該基板上方，該溝槽延伸通過該本體區域與該漂移區域，且終止於該基板中。
  6. 如申請專利範圍第1項之FET，其中該閘極互連層包括通過設置於該非作用區域中的一閘極滑槽區域中之週期性的接觸開口而形成的多個接點。
  7. 如申請專利範圍第1項之FET，其中該屏蔽電極係藉由一透過該溝槽中之IED之額外的連接以電性連接到該閘電極。
  8. 如申請專利範圍第1項之FET，其中該閘電極係進一步透過至少一個位於該溝槽內側的IED中之開口以電性連接到該屏蔽電極。
  9. 如申請專利範圍第1項之FET，其進一步包括一沿著一容納該FET之晶粒的周圍延伸之終端區域，該屏蔽電極與該閘電極延伸離開該溝槽且進入該終端區域，該屏蔽電極與該閘電極於該終端區域中藉由該閘極互連層電性連接。
  10. 如申請專利範圍第9項之FET，其中該屏蔽電極與該閘電極之間的電性連接係透過設置於該終端區域中的至少 一個接觸開口加以達成。
  11. 一種位於一半導體晶粒中之場效電晶體(FET)，其包含：一具有至少一作用胞體之作用區域；一非作用區域，其不具有作用胞體；一第一傳導類型之漂移區域；一第二傳導類型之本體區域，其設置於該漂移區域上方；及一溝槽，其延伸通過該本體區域且進入該漂移區域，該溝槽具有一屏蔽電極以及一閘電極設置於其中，該屏蔽電極係配置於該閘電極下方；其中該屏蔽電極與該閘電極延伸離開該溝槽且進入該非作用區域中，該屏蔽電極與該閘電極於該非作用區域中藉由一閘極互連層電性連接。
  12. 如申請專利範圍第11項之FET，其進一步包含：該第一傳導類型之多個源極區域，其設置於該本體區域中鄰近該溝槽之處；及該第二傳導類型之多個濃稠本體區域，其設置於該本體區域中鄰近該等源極區域之處。
  13. 如申請專利範圍第12項之FET，其中該閘電極在該溝槽中係凹陷成低於該等源極區域之一頂部表面，且該FET進一步包含：一連接該等源極區域與濃稠本體區域之互連層；一設置於該閘電極上之電介質材料，該電介質材料使該閘電極與該互連層隔離。
  14. 如申請專利範圍第11項之FET，其進一步包含一第一傳導類型之基板，該漂移區域係延伸於該基板上方，該溝槽延伸通過該本體區域，並且終止於該漂移區域中。
  15. 如申請專利範圍第11項之FET，其進一步包含一第一傳導類型之基板，該漂移區域設置於該基板上方，該溝槽延伸通過該本體區域以及該漂移區域，並且終止於該基板中。
  16. 如申請專利範圍第11項之FET，其進一步包含設置於該屏蔽電極與該閘電極之間的一電極間電介質，其中該屏蔽電極係進一步藉由一透過電極間電介質形成的電連接與該閘電極電性連接。
  17. 如申請專利範圍第11項之FET，其中該非作用區域包括一延伸通過該晶粒之中間部分的閘極滑槽區域，該屏蔽電極與該閘電極延伸離開該溝槽且進入該閘極滑槽區域，且該屏蔽電極與該閘電極於該閘極滑槽區域中係藉由該閘極互連層電性連接。
  18. 如申請專利範圍第11項之FET，其中該非作用區域包括一沿著晶粒之周圍延伸的終端區域，該屏蔽電極與該閘電極延伸離開該溝槽且進入該終端區域，且該屏蔽電極與該閘電極於該終端區域中係藉由該閘極互連層電性連接。
  19. 一種場效電晶體(FET)，其包含複數個延伸進入一半導體區域中之溝槽，各個溝槽具有一閘電極與一屏蔽電極，且其間設置有一電極間電介質，各溝槽的該屏蔽電 極、該電極間電介質與該閘電極係延伸進入該FET之一非作用區域，各溝槽的該屏蔽電極與該閘電極係經由一設置於該FET之該非作用區域中的一接觸開口中之互連層彼此電性連接，該接觸開口具有一由該電極間電介質界定的第一部分以及一由該閘電極之一側壁界定的第二部分。
  20. 一種形成一場效電晶體(FET)之方法，該方法包含：在一半導體區域中形成一溝槽；形成一襯墊於該溝槽之一下方側壁與一底部表面的屏蔽電介質層；在該溝槽之一下方部分中形成一屏蔽電極；沿著一上溝槽側壁與在該屏蔽電極上形成一電介質層；於該溝槽中且於該屏蔽電極上形成一閘電極，該屏蔽電極與該閘電極係形成為使該屏蔽電極與該閘電極延伸離開該溝槽且在一平頂區域上方；於該閘電極中形成複數個接觸開口，以透過該等接觸開口暴露出該屏蔽電極之表面區域；及於該等接觸開口中形成一互連層，該互連層使該閘電極與該屏蔽電極電性連接。
  21. 如申請專利範圍第20項之方法，其中該平頂區域係設置於一容納該FET之晶粒的一非作用區域中。
  22. 如申請專利範圍第20項之方法，其中該電介質層係藉由矽之氧化所形成。
  23. 如申請專利範圍第20項之方法，其中該半導體區域包括一第一傳導類型之磊晶層，其設置於一第一傳導類型之基板上方，該方法進一步包含：在該磊晶層中形成一第二傳導類型之一本體區域；在該本體區域中鄰近該溝槽處形成該第一傳導類型之多個源極區域；及在該本體區域中鄰接該等源極區域處形成該第二傳導類型之多個濃稠本體區域。
  24. 如申請專利範圍第20項之方法，其進一步包含在形成該閘電極之前，於延伸在該屏蔽電極上方之該電介質層的一部分中形成一個或更多之開口，以致於一旦在該溝槽中形成該閘電極，該閘電極便會透過一個或更多開口與該屏蔽電極電性接觸。
  25. 一種在一半導體晶粒中形成一場效電晶體(FET)的方法，該FET包括一作用區域以及一非作用區域，該方法包含：在該作用區域中形成一溝槽，該溝槽延伸進入一半導體區域中；於該溝槽中形成一第一聚矽層，該第一聚矽層具有一延伸在該非作用區域中的一平頂區域上方之部分；凹陷該溝槽中的該第一聚矽層，以便在該溝槽之一底部部分中形成一屏蔽電極，該溝槽中之該屏蔽電極具有與在該非作用區域中的該平頂區域上方延伸之該第一聚矽層的該部分的電連續性； 利用矽之氧化形成一電介質層，以致於使該電介質層襯墊：(i)該溝槽之一暴露上方側壁；(ii)該屏蔽電極之一上方表面；以及(iii)在該平頂區域上方之該第一聚矽層的該部分的一表面區域之至少一部分；於該溝槽中形成一第二聚矽層，該第二聚矽層具有一延伸在該平頂區域中之該電介質層上方的部分；凹陷該溝槽中的該第二聚矽層，以便在該溝槽之一上方部分中形成一閘電極，該溝槽中之該閘電極具有與在該平頂區域上方延伸之該第二聚矽層的該部分的電連續性；於延伸在該平頂區域上方的該第二聚矽層的該部分以及延伸在該平頂區域上方的該電介質的該部分中形成至少一個接觸開口，以便透過該至少一個接觸開口暴露出該第一聚矽層之一表面區域；及於該至少一個接觸開口中形成一閘極互連層，該閘極互連層使該第一聚矽層與該第二聚矽層電性連接。
  26. 如申請專利範圍第25項之方法，其進一步包含：在形成該第一聚矽層之前，形成一個襯墊於該溝槽之一側壁與一底部表面之屏蔽電介質層，該屏蔽電介質層延伸在該平頂區域上方；及在使該第一聚矽層凹陷進入該溝槽之後，凹陷該溝槽中之該屏蔽電介質層，以便暴露出該溝槽之一上方側壁。
  27. 如申請專利範圍第25項之方法，其中該半導體區域包括 一第一傳導類型之磊晶層，其設置於一第一傳導類型之基板上方，該方法進一步包含：在磊晶層中形成一第二傳導類型之本體區域；在該本體區域中鄰接該溝槽處形成該第一傳導類型之多個源極區域；及在該本體區域中鄰接該等源極區域處形成該第二傳導類型之多個濃稠本體區域。
  28. 一種形成一場效電晶體(FET)之方法，其包含：形成複數個延伸進入一半導體區域中的溝槽；在各個溝槽之一底部部分中形成一屏蔽電極；在各個溝槽位於該屏蔽電極上方之一上方部分中形成一閘電極；及形成一閘極互連層，其使該屏蔽電極與該閘電極於該FET之一非作用區域中電性連接。
  29. 一種場效電晶體(FET)，其包含：一溝槽，其延伸進入一半導體區域；一屏蔽電極，其設置於該溝槽之一下方部分中；一閘電極，其設置於該溝槽之一上方部分中且設置於該屏蔽電極上方；及一閘極互連層，其使該屏蔽電極與該閘電極於該FET之一非作用區域中電性連接。
  30. 如申請專利範圍第29項之場效電晶體，其進一步包含一設置於該非作用區域中之閘極滑槽區域，該閘極互連層使該閘電極與該屏蔽電極於該閘極滑槽區域中電性連 接。
  31. 如申請專利範圍第29項之場效電晶體，其進一步包含一沿著一容納該FET之晶粒的周圍延伸之終端區域，該閘極互連層使該閘電極與該屏蔽電極於該終端區域中電性連接。
  32. 如申請專利範圍第29項之場效電晶體，其中該非作用區域含有該FET的不作用胞體。
  33. 如申請專利範圍第29項之場效電晶體，其中該半導體區域包括：一第一傳導類型之漂移區域；一第二傳導類型之本體區域，其設置於該漂移區域上方；及該第一傳導類型之一源極區域，其設置於該本體區域中鄰接該溝槽處。
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KR20090018638A (ko) 2009-02-20
WO2007149666A2 (en) 2007-12-27
AT505888A2 (de) 2009-04-15
CN101473443A (zh) 2009-07-01
US7319256B1 (en) 2008-01-15

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