JP2011139054A - 半導体装置およびその作製方法 - Google Patents
半導体装置およびその作製方法 Download PDFInfo
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- JP2011139054A JP2011139054A JP2010268671A JP2010268671A JP2011139054A JP 2011139054 A JP2011139054 A JP 2011139054A JP 2010268671 A JP2010268671 A JP 2010268671A JP 2010268671 A JP2010268671 A JP 2010268671A JP 2011139054 A JP2011139054 A JP 2011139054A
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- Prior art keywords
- layer
- oxide semiconductor
- electrode layer
- semiconductor layer
- insulating layer
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
【解決手段】絶縁表面上の結晶領域を有する酸化物半導体層と、前記酸化物半導体層と接するソース電極層およびドレイン電極層と、前記酸化物半導体層、前記ソース電極層、および前記ドレイン電極層を覆うゲート絶縁層と、前記ゲート絶縁層上の、前記結晶領域と重畳する領域のゲート電極層と、を有し、前記結晶領域は、前記酸化物半導体層の表面と略垂直な方向にc軸が配向する結晶を有する領域である半導体装置である。
【選択図】図1
Description
本実施の形態では、開示する発明の一態様に係る半導体装置の構成および作製方法について、図1乃至図16を参照して説明する。
図1は、半導体装置の構成の一例であるトランジスタ150を示す断面図である。なお、トランジスタ150は、n型トランジスタであるものとして説明するが、p型トランジスタとしても良い。
酸化物半導体において、DOS(density of state)等の物性研究は多くなされているが、これらの研究は、欠陥の準位そのものを十分に減らすという思想を含まない。開示する発明の一態様では、DOS増大の原因たり得る水や水素を酸化物半導体中より除去することで、高純度化し、真性化(i型化)した酸化物半導体を作製する。これは、DOSそのものを十分に減らすという思想に立脚するものである。そして、これによって極めて優れた工業製品の製造を可能とするものである。
酸化物半導体との比較対象たり得る半導体材料としては、炭化珪素(例えば、4H−SiC)などがある。酸化物半導体と4H−SiCはいくつかの共通点を有している。キャリア密度はその一例である。フェルミ・ディラック分布に従えば、酸化物半導体の少数キャリアは10−7/cm3程度と見積もられるが、これは、4H−SiCにおける6.7×10−11/cm3と同様、極めて低い値である。シリコンの真性キャリア密度(1.45×1010/cm3程度)と比較すれば、その程度が並はずれていることが良く理解できる。
ここで、酸化物半導体を用いたトランジスタの電導機構につき、図2乃至図5を用いて説明する。なお、以下の説明では、理解の容易のため理想的な状況を仮定しており、そのすべてが現実の様子を反映しているとは限らない。また、以下の説明はあくまでも一考察に過ぎず、発明の有効性に影響を与えるものではないことを付記する。
次に、酸化物半導体を用いたトランジスタのホットキャリア劣化耐性につき、図6及び図7を用いて説明する。なお、以下の説明では、理解の容易のため理想的な状況を仮定しており、そのすべてが現実の様子を反映しているとは限らない。また、以下の説明はあくまでも一考察に過ぎないことを付記する。
次に、酸化物半導体を用いたトランジスタにおける短チャネル効果に関し、図8および図9を用いて説明する。なお、以下の説明では、理解の容易のため理想的な状況を仮定しており、そのすべてが現実の様子を反映しているとは限らない。また、以下の説明はあくまでも一考察に過ぎないことを付記する。
開示する発明に係る技術思想の一は、酸化物半導体層におけるキャリア密度を十分に小さくし、できる限り真性(i型)に近づけようとするものである。以下、キャリア密度の求め方、および、酸化物半導体層において測定したキャリア密度に関し、図10および図11を参照して説明する。
MOSキャパシタの構造:ガラス基板上に300nmの厚さのチタン層を有し、チタン層上に100nmの厚さの窒化チタン層を有し、窒化チタン層上にIn−Ga−Zn−O系の酸化物半導体(a−IGZO)を用いた2μmの厚さの酸化物半導体層を有し、酸化物半導体層上に300nmの厚さの酸窒化珪素層を有し、酸窒化珪素層上に300nmの銀層を有する。
次に、半導体装置の構成の一例であるトランジスタ150の作製方法について図12および図13を参照して説明する。
次に、図1乃至図13において示した半導体装置の変形例について、図14乃至図16を参照して説明する。なお、図14乃至図16に示す半導体装置の構成要素の多くは、図1乃至図13において示した半導体装置と共通であるため、ここでは、相違点についてのみ説明する。
本実施の形態では、先の実施の形態に係る半導体装置とは異なる構成の半導体装置およびその作製方法について、図17乃至図22を参照して説明する。なお、本実施の形態に示す構成は、先の実施の形態において示す構成と多くの点で共通するから、以下では主として相違点についてのみ説明する。
図17は、半導体装置の構成の一例であるトランジスタ150を示す断面図である。
次に、半導体装置の構成の一例であるトランジスタ150の作製方法について図18乃至図20を参照して説明する。
次に、図17乃至図20において示した半導体装置の変形例について、図21および図22を参照して説明する。なお、図21および図22に示す半導体装置の構成要素の多くは、図17乃至図20において示した半導体装置と共通であるため、ここでは、相違点についてのみ説明する。
本実施の形態では、先の実施の形態で得られる半導体装置を搭載した電子機器の例について図23を用いて説明する。先の実施の形態で得られる半導体装置は、従来にない優れた特性を有するものである。このため、当該半導体装置を用いて新たな構成の電子機器を提供することが可能である。
101 導電層
101a ゲート電極層
102 絶縁層
106 酸化物半導体層
106a 酸化物半導体層
107a 導電層
107b 導電層
108 導電層
108a ソース電極層またはドレイン電極層
108b ソース電極層またはドレイン電極層
109a 絶縁層
109b 絶縁層
110 結晶領域
112 ゲート絶縁層
114 ゲート電極層
116 層間絶縁層
118 層間絶縁層
150 トランジスタ
200 基板
206 素子分離絶縁層
208a ゲート絶縁層
210a ゲート電極層
214 不純物領域
216 チャネル形成領域
218 サイドウォール絶縁層
220 高濃度不純物領域
224 金属化合物領域
226 層間絶縁層
228 層間絶縁層
230a ソース電極層またはドレイン電極層
230b ソース電極層またはドレイン電極層
230c 電極層
234 絶縁層
236a 電極層
236b 電極層
236c 電極層
250 トランジスタ
254a 電極層
254b 電極層
254c 電極層
254d 電極層
254e 電極層
256 絶縁層
258a 電極層
258b 電極層
258c 電極層
258d 電極層
301 本体
302 筐体
303 表示部
304 キーボード
311 本体
312 スタイラス
313 表示部
314 操作ボタン
315 外部インターフェイス
320 電子書籍
321 筐体
323 筐体
325 表示部
327 表示部
331 電源
333 操作キー
335 スピーカー
337 軸部
340 筐体
341 筐体
342 表示パネル
343 スピーカー
344 マイクロフォン
345 操作キー
346 ポインティングデバイス
347 カメラ用レンズ
348 外部接続端子
349 太陽電池セル
350 外部メモリスロット
361 本体
363 接眼部
364 操作スイッチ
365 表示部(B)
366 バッテリー
367 表示部(A)
370 テレビジョン装置
371 筐体
373 表示部
375 スタンド
377 表示部
379 操作キー
380 リモコン操作機
Claims (14)
- 絶縁表面上の結晶領域を有する酸化物半導体層と、
前記酸化物半導体層と接するソース電極層およびドレイン電極層と、
前記酸化物半導体層、前記ソース電極層、および前記ドレイン電極層を覆うゲート絶縁層と、
前記ゲート絶縁層上の、前記結晶領域と重畳する領域のゲート電極層と、
を有し、
前記結晶領域は、前記酸化物半導体層の表面と略垂直な方向にc軸が配向する結晶を有する領域である半導体装置。 - 絶縁表面上の第1のゲート電極層と、
前記第1のゲート電極層を覆う第1のゲート絶縁層と、
前記第1のゲート絶縁層上の結晶領域を有する酸化物半導体層と、
前記酸化物半導体層と接するソース電極層およびドレイン電極層と、
前記酸化物半導体層、前記ソース電極層、および前記ドレイン電極層を覆う第2のゲート絶縁層と、
前記第2のゲート絶縁層上の、前記結晶領域と重畳する領域の第2のゲート電極層と、
を有し、
前記結晶領域は、前記酸化物半導体層の表面と略垂直な方向にc軸が配向する結晶を有する領域である半導体装置。 - 請求項1または請求項2において、前記酸化物半導体層は凹部を有する半導体装置。
- 請求項1乃至請求項3のいずれか一において、前記ソース電極層および前記ドレイン電極層の上に、前記ソース電極層および前記ドレイン電極層と略同一形状の絶縁層を有する半導体装置。
- 請求項1乃至請求項4のいずれか一において、前記酸化物半導体層と接する部分に酸素との親和性が低い材料を用いた前記ソース電極層および前記ドレイン電極層を有する半導体装置。
- 請求項1乃至請求項5のいずれか一において、前記酸化物半導体層の前記結晶領域以外の領域は、非晶質構造である半導体装置。
- 請求項1乃至請求項6のいずれか一において、前記酸化物半導体層の表面の高低差は、前記ゲート電極層と重畳する領域において1nm以下である半導体装置。
- 絶縁表面上に酸化物半導体層を形成し、
前記酸化物半導体層上に導電層を形成し、
前記導電層をエッチングすることにより、ソース電極層およびドレイン電極層を形成し、
熱処理を行うことにより、該酸化物半導体層の表面と略垂直な方向にc軸が配向する結晶領域を形成し、
前記酸化物半導体層、前記ソース電極層、および前記ドレイン電極層を覆うようにゲート絶縁層を形成し、
前記ゲート絶縁層上の前記結晶領域と重畳する領域にゲート電極層を形成する、半導体装置の作製方法。 - 絶縁表面上に第1のゲート電極層を形成し、
前記第1のゲート電極層を覆うように第1のゲート絶縁層を形成し、
前記第1のゲート絶縁層上に酸化物半導体層を形成し、
前記酸化物半導体層上に導電層を形成し、
前記導電層をエッチングすることにより、ソース電極層およびドレイン電極層を形成し、
熱処理を行うことにより、該酸化物半導体層の表面と略垂直な方向にc軸が配向する結晶領域を形成し、
前記酸化物半導体層、前記ソース電極層、および前記ドレイン電極層を覆うように第2のゲート絶縁層を形成し、
前記第2のゲート絶縁層上の前記結晶領域と重畳する領域に第2のゲート電極層を形成する、半導体装置の作製方法。 - 請求項8または請求項9において、前記熱処理を550℃以上850℃以下の温度条件で行う半導体装置の作製方法。
- 請求項8乃至請求項10のいずれか一において、前記導電層をエッチングする際に、前記酸化物半導体層の一部を除去する半導体装置の作製方法。
- 請求項8乃至請求項11のいずれか一において、前記ソース電極層および前記ドレイン電極層の上に、前記ソース電極層および前記ドレイン電極層と略同一形状の絶縁層を形成する半導体装置の作製方法。
- 請求項8乃至請求項12のいずれか一において、前記酸化物半導体層と接する部分に酸素との親和性が低い材料を用いて前記ソース電極層および前記ドレイン電極層を形成する半導体装置の作製方法。
- 請求項8乃至請求項13のいずれか一において、前記酸化物半導体層として非晶質構造の酸化物半導体層を形成し、前記結晶領域以外の領域を非晶質構造として残存させる半導体装置の作製方法。
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