JP2011109079A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2011109079A JP2011109079A JP2010234811A JP2010234811A JP2011109079A JP 2011109079 A JP2011109079 A JP 2011109079A JP 2010234811 A JP2010234811 A JP 2010234811A JP 2010234811 A JP2010234811 A JP 2010234811A JP 2011109079 A JP2011109079 A JP 2011109079A
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- electrode
- insulating layer
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- oxide semiconductor
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Images
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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Abstract
【解決手段】半導体材料を含む基板に設けられたチャネル形成領域と、チャネル形成領域を挟むように設けられた不純物領域と、チャネル形成領域上の第1のゲート絶縁層と、第1のゲート絶縁層上の第1のゲート電極と、不純物領域と電気的に接続する第1のソース電極および第1のドレイン電極と、を有する第1のトランジスタと、半導体材料を含む基板上の第2のゲート電極と、第2のゲート電極上の第2のゲート絶縁層と、第2のゲート絶縁層上の酸化物半導体層と、酸化物半導体層と電気的に接続する第2のソース電極および第2のドレイン電極と、を有する第2のトランジスタと、を有する半導体装置である。
【選択図】図1
Description
本実施の形態では、開示する発明の一態様に係る半導体装置の構成および作製方法について、図1乃至図6を参照して説明する。
図1(A)には、本実施の形態に係る半導体装置の断面図を、図1(B)には、本実施の形態に係る半導体装置の平面図を、それぞれ示す。ここで、図1(A)は、図1(B)の線A1−A2および線D1−D2における断面に相当する。図1(A)および図1(B)に示される半導体装置は、下部にp型トランジスタ160を有し、上部に酸化物半導体を用いたn型トランジスタ162を有する。
次に、上記半導体装置の作製方法の一例について説明する。以下では、はじめに下部のp型トランジスタの作製方法について説明し、その後、上部のn型トランジスタの作製方法について説明する。
まず、半導体材料を含む基板100を用意する(図4(A)参照)。半導体材料を含む基板100としては、シリコンや炭化シリコンなどの単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウムなどの化合物半導体基板、SOI基板などを適用することができる。ここでは、半導体材料を含む基板100として、単結晶シリコン基板を用いる場合の一例について示すものとする。なお、一般に「SOI基板」は、絶縁表面上にシリコン半導体層が設けられた構成の基板をいうが、本明細書等においては、絶縁表面上にシリコン以外の材料からなる半導体層が設けられた構成の基板をも含む概念として用いる。つまり、「SOI基板」が有する半導体層は、シリコン半導体層に限定されない。また、SOI基板には、ガラス基板などのような絶縁基板上に絶縁層を介して半導体層が設けられた構成のものが含まれるものとする。
次に、図5および図6を用いて、層間絶縁層128上にn型トランジスタを作製する工程について説明する。なお、図5および図6では、図1に示す線A1−A2の断面および線D1−D2の断面における、n型トランジスタの作製工程を示すものであるから、n型トランジスタの下部に形成されているp型トランジスタについては省略している。
本実施の形態では、開示する発明の別の一態様に係る半導体装置の構成について、図7および図8を参照して説明する。なお、本実施の形態では、メモリ素子として用いることが可能な半導体装置の構成について示す。
本実施の形態では、開示する発明の別の一態様に係る半導体装置の構成について、図9および図10を参照して説明する。なお、本実施の形態では、メモリ素子として用いることが可能な半導体装置の構成について示す。
本実施の形態では、先の実施の形態で得られる半導体装置を搭載した電子機器の例について図11を用いて説明する。先の実施の形態で得られる半導体装置は、スイッチング特性の良い酸化物半導体を用いたトランジスタを有するので、各電子機器の消費電力を低減することができる。また、酸化物半導体の特性を利用した新たな半導体装置(例えば、メモリ素子など)が提供されるため、新たな構成の電子機器を提供することが可能である。なお、先の実施の形態に係る半導体装置は、単体、または集積化されて回路基板などに実装され、各電子機器の内部に搭載されることになる。
102 保護層
104 半導体領域
106 素子分離絶縁層
108a ゲート絶縁層
108b ゲート絶縁層
110a ゲート電極
110b ゲート配線
110c 配線
112 絶縁層
114 不純物領域
116 チャネル形成領域
118 サイドウォール絶縁層
120 高濃度不純物領域
122 金属層
124 金属化合物領域
126 層間絶縁層
128 層間絶縁層
130a ソース電極またはドレイン電極
130b ソース電極またはドレイン電極
130c ソース電極またはドレイン電極
130d ソース電極またはドレイン電極
130e 電極
132 絶縁層
134 導電層
136a 電極
136b 電極
136c ゲート電極
136d 電極
136e 電極
136f ゲート電極
138 ゲート絶縁層
140 酸化物半導体層
142a ソース電極またはドレイン電極
142b ソース電極またはドレイン電極
144 保護絶縁層
146 層間絶縁層
148 導電層
150a 電極
150b 電極
150c 電極
150d 電極
150e 電極
150f 電極
152 絶縁層
154a 電極
154b 電極
154c 電極
154d 電極
154e 電極
160 p型トランジスタ
162 n型トランジスタ
164 p型トランジスタ
166 n型トランジスタ
200 基板
206 素子分離絶縁層
208a ゲート絶縁層
210a ゲート電極
214 不純物領域
216 チャネル形成領域
218 サイドウォール絶縁層
220 高濃度不純物領域
224 金属化合物領域
226 層間絶縁層
228 絶縁層
230a ソース電極またはドレイン電極
230b ソース電極またはドレイン電極
230c 電極
232 絶縁層
236a 電極
236b 電極
236c ゲート電極
238 ゲート絶縁層
240 酸化物半導体層
242a ソース電極またはドレイン電極
242b ソース電極またはドレイン電極
244 保護絶縁層
246 層間絶縁層
250a 電極
250b 電極
250c 電極
250d 電極
250e 電極
252 絶縁層
254a 電極
254b 電極
254c 電極
254d 電極
260 トランジスタ
262 トランジスタ
301 本体
302 筐体
303 表示部
304 キーボード
311 本体
312 スタイラス
313 表示部
314 操作ボタン
315 外部インターフェイス
320 電子書籍
321 筐体
323 筐体
325 表示部
327 表示部
331 電源
333 操作キー
335 スピーカー
337 軸部
340 筐体
341 筐体
342 表示パネル
343 スピーカー
344 マイクロフォン
345 操作キー
346 ポインティングデバイス
347 カメラ用レンズ
348 外部接続端子
349 太陽電池セル
350 外部メモリスロット
361 本体
363 接眼部
364 操作スイッチ
365 表示部(B)
366 バッテリー
367 表示部(A)
370 テレビジョン装置
371 筐体
373 表示部
375 スタンド
377 表示部
379 操作キー
380 リモコン操作機
400 基板
406 素子分離絶縁層
408a ゲート絶縁層
410a ゲート電極
410b ゲート配線
414 不純物領域
416 チャネル形成領域
418 サイドウォール絶縁層
420 高濃度不純物領域
424 金属化合物領域
426 層間絶縁層
428 層間絶縁層
430a ソース電極またはドレイン電極
430b ソース電極またはドレイン電極
430c ソース電極またはドレイン電極
432 絶縁層
436a 電極
436b 電極
436c ゲート電極
438 ゲート絶縁層
440 酸化物半導体層
442a ソース電極またはドレイン電極
442b ソース電極またはドレイン電極
444 保護絶縁層
446 層間絶縁層
450a 電極
450b 電極
450c 電極
450d 電極
450e 電極
452 絶縁層
454a 電極
454b 電極
454c 電極
454d 電極
460 p型トランジスタ
462 トランジスタ
464 n型トランジスタ
Claims (10)
- 半導体材料を含む基板に設けられたチャネル形成領域と、前記チャネル形成領域を挟むように設けられた不純物領域と、前記チャネル形成領域上の第1のゲート絶縁層と、前記第1のゲート絶縁層上の第1のゲート電極と、前記不純物領域と電気的に接続する第1のソース電極および第1のドレイン電極と、を有する第1のトランジスタと、
前記半導体材料を含む基板上の第2のゲート電極と、前記第2のゲート電極上の第2のゲート絶縁層と、前記第2のゲート絶縁層上の酸化物半導体層と、前記酸化物半導体層と電気的に接続する第2のソース電極および第2のドレイン電極と、を有する第2のトランジスタと、を有する半導体装置。 - 前記第1のゲート電極と、前記第2のゲート電極とは、電気的に接続され、
前記第1のソース電極または前記第1のドレイン電極と、前記第2のソース電極または前記第2のドレイン電極とは、電気的に接続されている、請求項1に記載の半導体装置。 - 前記第1のトランジスタはp型トランジスタであり、前記第2のトランジスタはn型トランジスタである、請求項1または請求項2に記載の半導体装置。
- 前記第1のゲート電極と、前記第2のソース電極または前記第2のドレイン電極とは、電気的に接続されている、請求項1に記載の半導体装置。
- 前記半導体材料を含む基板は、単結晶半導体基板またはSOI基板である、請求項1乃至請求項4のいずれか一に記載の半導体装置。
- 前記半導体材料はシリコンである、請求項1乃至請求項5のいずれか一に記載の半導体装置。
- 前記酸化物半導体層は、In−Ga−Zn−O系の酸化物半導体材料を含んでいる、請求項1乃至請求項6のいずれか一に記載の半導体装置。
- 前記酸化物半導体層は、In2Ga2ZnO7の結晶を含んでなる、請求項1乃至請求項7のいずれか一に記載の半導体装置。
- 前記酸化物半導体層の水素濃度は5×1019atoms/cm3以下である、請求項1乃至請求項8のいずれか一に記載の半導体装置。
- 前記第2のトランジスタのオフ電流は1×10−13A以下である、請求項1乃至請求項9のいずれか一に記載の半導体装置。
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JP2012256407A (ja) * | 2011-04-15 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 記憶装置 |
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