JP2013179579A - プログラマブルロジックデバイス、及び半導体装置の作製方法 - Google Patents
プログラマブルロジックデバイス、及び半導体装置の作製方法 Download PDFInfo
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- JP2013179579A JP2013179579A JP2013012907A JP2013012907A JP2013179579A JP 2013179579 A JP2013179579 A JP 2013179579A JP 2013012907 A JP2013012907 A JP 2013012907A JP 2013012907 A JP2013012907 A JP 2013012907A JP 2013179579 A JP2013179579 A JP 2013179579A
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Abstract
【解決手段】複数のプログラマブルロジックエレメントと、上記複数のプログラマブルロジックエレメントにおいてそれぞれ行われる論理演算を定義するための、コンフィギュレーションデータが記憶されたメモリエレメントと、を有し、上記メモリエレメントは記憶素子を複数有し、上記記憶素子は、プログラマブルロジックエレメントとメモリエレメントの電気的な接続を為すノードに、上記コンフィギュレーションデータによって定められた量の電荷を、供給、保持、放出するためのスイッチと、当該ノードとの間にそれぞれ容量が形成される複数の配線とを、それぞれ有するプログラマブルロジックデバイス。
【選択図】図1
Description
図1(A)に、本発明の一態様に係るPLDの構成例を、模式的に示す。図1(A)に示すPLD100は、複数のPLE(プログラマブルロジックエレメント)101を有するロジックアレイ102と、複数の記憶素子103を有するメモリエレメント104とを有する。メモリエレメント104は、ロジックアレイ102が形成されている層の上に設けられている。
本実施の形態では、メモリエレメント104の構成例について説明する。
本実施の形態では、PLE101が有するLUT113の構成例について説明する。LUT113は複数のマルチプレクサを用いて構成することができる。そして、複数のマルチプレクサの入力端子及び制御端子のうちのいずれかにコンフィギュレーションデータ105が入力される構成とすることができる。
本実施の形態では、図6(A)に示した記憶素子103において、トランジスタ106tの活性層に酸化物半導体を用い、プログラマブルロジックエレメントが有するトランジスタ230の活性層にシリコンを用いる場合を例に挙げて、PLD及び半導体装置の作製方法について説明する。
本実施の形態では、記憶素子103のレイアウトの一例と、記憶素子103が配線にそれぞれ置き換えられたレイアウトの一例とについて、説明する。
本発明の一態様に係る半導体装置またはプログラマブルロジックデバイスは、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置(代表的にはDVD:Digital Versatile Disc等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置)に用いることができる。その他に、本発明の一態様に係る半導体装置またはプログラマブルロジックデバイスを用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯情報端末、電子書籍、ビデオカメラ、デジタルスチルカメラなどのカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンター、プリンター複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図16に示す。
32 マルチプレクサ
33 マルチプレクサ
34 マルチプレクサ
35 マルチプレクサ
36 マルチプレクサ
37 マルチプレクサ
41 マルチプレクサ
42 マルチプレクサ
43 マルチプレクサ
44 OR回路
100 PLD
101 PLE
102 ロジックアレイ
103 記憶素子
103a 記憶素子
103b 記憶素子
104 メモリエレメント
105 コンフィギュレーションデータ
106 スイッチ
106t トランジスタ
107 配線
107a 配線
107b 配線
107c 導電膜
108 配線
108c 導電膜
109 配線
109c 導電膜
110 ノード
110c 導電膜
111 容量素子
112 容量素子
113 LUT
114 レジスタ
115 コンフィギュレーションメモリ
120 半導体装置
121 配線群
122 スイッチ
123 配線エレメント
124 出力端子
125 配線
126 配線
127 トランジスタ
128 トランジスタ
129 トランジスタ
130 トランジスタ
131 トランジスタ
132 トランジスタ
140 I/Oエレメント
141 PLL
142 RAM
143 乗算器
150 配線
150c 導電膜
151t トランジスタ
160 セルアレイ
161 駆動回路
162 入出力バッファ
163 メインアンプ
164 カラムデコーダ
165 ローデコーダ
166 スイッチ回路
167 プリチャージ回路
168 センスアンプ
169 回路
170 導電膜
171 導電膜
230 トランジスタ
515 トランジスタ
516 トランジスタ
517 トランジスタ
518 トランジスタ
519 トランジスタ
520 トランジスタ
521 トランジスタ
522 トランジスタ
523 トランジスタ
700 基板
701 絶縁膜
702 半導体膜
703 ゲート絶縁膜
704 ゲート電極
705 チャネル形成領域
706 不純物領域
707 絶縁膜
708 絶縁膜
709 絶縁膜
710 導電膜
711 導電膜
712 導電膜
713 絶縁膜
714 絶縁膜
715 酸化物半導体膜
717 導電膜
718 導電膜
719 ゲート絶縁膜
720 ゲート電極
721 導電膜
722 絶縁膜
725 開口部
726 配線
727 絶縁膜
800 配線
5001 筐体
5002 筐体
5003 表示部
5004 表示部
5005 マイクロホン
5006 スピーカー
5007 操作キー
5008 スタイラス
5101 車体
5102 車輪
5103 ダッシュボード
5104 ライト
5301 筐体
5302 冷蔵室用扉
5303 冷凍室用扉
5401 筐体
5402 表示部
5403 キーボード
5404 ポインティングデバイス
5601 筐体
5602 筐体
5603 表示部
5604 表示部
5605 接続部
5606 操作キー
5801 筐体
5802 筐体
5803 表示部
5804 操作キー
5805 レンズ
5806 接続部
Claims (8)
- 複数のプログラマブルロジックエレメントと、前記複数のプログラマブルロジックエレメントにおいてそれぞれ行われる論理演算を定義するための、コンフィギュレーションデータが記憶されたメモリエレメントと、を有し、
前記メモリエレメントは記憶素子を複数有し、
前記記憶素子は、前記プログラマブルロジックエレメントと前記メモリエレメントの電気的な接続を為すノードに、前記コンフィギュレーションデータによって定められた量の電荷を、供給、保持、放出するためのスイッチと、当該ノードとの間にそれぞれ容量が形成される複数の配線とを有するプログラマブルロジックデバイス。 - 複数のプログラマブルロジックエレメントと、前記複数のプログラマブルロジックエレメントにおいてそれぞれ行われる論理演算を定義するための、コンフィギュレーションデータが記憶されたメモリエレメントと、を有し、
前記メモリエレメントは記憶素子を複数有し、
前記記憶素子は、前記プログラマブルロジックエレメントと前記メモリエレメントの電気的な接続を為すノードに、前記コンフィギュレーションデータによって定められた量の電荷を、供給、保持、放出するためのスイッチと、当該ノードとの間にそれぞれ容量が形成される複数の配線とを有し、
前記スイッチは、ドレイン電圧が3.3Vのときにオフ電流が約40fAより小さいトランジスタを有するプログラマブルロジックデバイス。 - 複数のプログラマブルロジックエレメントと、前記複数のプログラマブルロジックエレメントにおいてそれぞれ行われる論理演算を定義するための、コンフィギュレーションデータが記憶されたメモリエレメントと、を有し、
前記メモリエレメントは記憶素子を複数有し、
前記記憶素子は、前記プログラマブルロジックエレメントと前記メモリエレメントの電気的な接続を為すノードに、前記コンフィギュレーションデータによって定められた量の電荷を、供給、保持、放出するためのスイッチと、当該ノードとの間にそれぞれ容量が形成される複数の配線とを有し、
前記スイッチは、チャネル形成領域に酸化物半導体を含むトランジスタを有するプログラマブルロジックデバイス。 - 複数のプログラマブルロジックエレメントと、配線エレメントと、前記複数のプログラマブルロジックエレメントにおいてそれぞれ行われる論理演算を定義するため、或いは、前記配線エレメントによって行われる前記複数のプログラマブルロジックエレメント間の接続を定めるための、コンフィギュレーションデータが記憶されたメモリエレメントと、を有し、
前記メモリエレメントは記憶素子を複数有し、
前記記憶素子は、前記プログラマブルロジックエレメントと前記メモリエレメントの電気的な接続を為すノードに、前記コンフィギュレーションデータによって定められた量の電荷を、供給、保持、放出するためのスイッチと、当該ノードとの間にそれぞれ容量が形成される複数の配線とを有するプログラマブルロジックデバイス。 - 複数のプログラマブルロジックエレメントと、配線エレメントと、前記複数のプログラマブルロジックエレメントにおいてそれぞれ行われる論理演算を定義するため、或いは、前記配線エレメントによって行われる前記複数のプログラマブルロジックエレメント間の接続を定めるための、コンフィギュレーションデータが記憶されたメモリエレメントと、を有し、
前記メモリエレメントは記憶素子を複数有し、
前記記憶素子は、前記プログラマブルロジックエレメントと前記メモリエレメントの電気的な接続を為すノードに、前記コンフィギュレーションデータによって定められた量の電荷を、供給、保持、放出するためのスイッチと、当該ノードとの間にそれぞれ容量が形成される複数の配線とを有し、
前記スイッチは、ドレイン電圧が3.3Vのときにオフ電流が約40fAより小さいトランジスタを有するプログラマブルロジックデバイス。 - 複数のプログラマブルロジックエレメントと、配線エレメントと、前記複数のプログラマブルロジックエレメントにおいてそれぞれ行われる論理演算を定義するため、或いは、前記配線エレメントによって行われる前記複数のプログラマブルロジックエレメント間の接続を定めるための、コンフィギュレーションデータが記憶されたメモリエレメントと、を有し、
前記メモリエレメントは記憶素子を複数有し、
前記記憶素子は、前記プログラマブルロジックエレメントと前記メモリエレメントの電気的な接続を為すノードに、前記コンフィギュレーションデータによって定められた量の電荷を、供給、保持、放出するためのスイッチと、当該ノードとの間にそれぞれ容量が形成される複数の配線とを有し、
前記スイッチは、チャネル形成領域に酸化物半導体を含むトランジスタを有するプログラマブルロジックデバイス。 - 複数の第1プログラマブルロジックエレメント上に、前記複数の第1プログラマブルロジックエレメントにおいてそれぞれ行われる論理演算を定義するための、コンフィギュレーションデータが記憶されるメモリエレメントを設けることで、プログラマブルロジックデバイスを形成し、
前記プログラマブルロジックデバイスにおいて前記コンフィギュレーションデータが確定した後、前記複数の第1プログラマブルロジックエレメントと同じ論理素子を有する複数の第2プログラマブルロジックエレメント上に、前記複数の第2プログラマブルロジックエレメントのいずれかに前記コンフィギュレーションデータに従って接続された複数の配線を形成し、
前記メモリエレメントは記憶素子を複数有し、前記記憶素子は、前記第1プログラマブルロジックエレメントと前記メモリエレメントの電気的な接続を為すノードに、前記コンフィギュレーションデータによって定められた量の電荷を、供給、保持、放出するためのスイッチと、当該ノードとの間にそれぞれ容量が形成される複数の配線とを有する半導体装置の作製方法。 - 複数の第1プログラマブルロジックエレメント上に、前記複数の第1プログラマブルロジックエレメントにおいてそれぞれ行われる論理演算を定義するための、コンフィギュレーションデータが記憶されるメモリエレメントを設けることで、プログラマブルロジックデバイスを形成し、
前記プログラマブルロジックデバイスにおいて前記コンフィギュレーションデータが確定した後、前記複数の第1プログラマブルロジックエレメントと同じ論理素子を有する複数の第2プログラマブルロジックエレメント上に、前記複数の第2プログラマブルロジックエレメントのいずれかに前記コンフィギュレーションデータに従って接続された複数の配線を形成し、
前記メモリエレメントは記憶素子を複数有し、前記記憶素子は、前記第1プログラマブルロジックエレメントと前記メモリエレメントの電気的な接続を為すノードに、前記コンフィギュレーションデータによって定められた量の電荷を、供給、保持、放出するためのスイッチと、当該ノードとの間にそれぞれ容量が形成される複数の配線とを有し、前記スイッチは、チャネル形成領域に酸化物半導体を含むトランジスタを有する半導体装置の作製方法。
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JP2006313999A (ja) * | 2005-05-09 | 2006-11-16 | Renesas Technology Corp | 半導体装置 |
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JP2015181081A (ja) * | 2014-03-07 | 2015-10-15 | 株式会社半導体エネルギー研究所 | 半導体装置および電子機器 |
WO2017038095A1 (ja) * | 2015-09-02 | 2017-03-09 | 日本電気株式会社 | プログラマブル論理集積回路と半導体装置およびキャラクタライズ方法 |
JPWO2017038095A1 (ja) * | 2015-09-02 | 2018-06-28 | 日本電気株式会社 | プログラマブル論理集積回路と半導体装置およびキャラクタライズ方法 |
US10305485B2 (en) | 2015-09-02 | 2019-05-28 | Nec Corporation | Programmable logic integrated circuit, semiconductor device, and characterization method |
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US20130207170A1 (en) | 2013-08-15 |
US20160268265A1 (en) | 2016-09-15 |
JP6708767B2 (ja) | 2020-06-10 |
JP2018137452A (ja) | 2018-08-30 |
US9379113B2 (en) | 2016-06-28 |
JP6488037B2 (ja) | 2019-03-20 |
JP6310116B2 (ja) | 2018-04-11 |
JP2017195368A (ja) | 2017-10-26 |
US10600792B2 (en) | 2020-03-24 |
JP6125850B2 (ja) | 2017-05-10 |
JP2019125792A (ja) | 2019-07-25 |
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