ITMI20041675A1 - Blocco di commutazione e relativa matrice di commutazione, in particolare per architetture fpga. - Google Patents

Blocco di commutazione e relativa matrice di commutazione, in particolare per architetture fpga.

Info

Publication number
ITMI20041675A1
ITMI20041675A1 IT001675A ITMI20041675A ITMI20041675A1 IT MI20041675 A1 ITMI20041675 A1 IT MI20041675A1 IT 001675 A IT001675 A IT 001675A IT MI20041675 A ITMI20041675 A IT MI20041675A IT MI20041675 A1 ITMI20041675 A1 IT MI20041675A1
Authority
IT
Italy
Prior art keywords
switching
fpga architectures
block
matrix
switching matrix
Prior art date
Application number
IT001675A
Other languages
English (en)
Inventor
Fabio Campi
Carlo Chiesa
Luca Ciccarelli
Roberto Giansante
Andrea Lodi
Mario Toma
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT001675A priority Critical patent/ITMI20041675A1/it
Publication of ITMI20041675A1 publication Critical patent/ITMI20041675A1/it
Priority to US11/215,301 priority patent/US7463055B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
IT001675A 2004-08-30 2004-08-30 Blocco di commutazione e relativa matrice di commutazione, in particolare per architetture fpga. ITMI20041675A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT001675A ITMI20041675A1 (it) 2004-08-30 2004-08-30 Blocco di commutazione e relativa matrice di commutazione, in particolare per architetture fpga.
US11/215,301 US7463055B2 (en) 2004-08-30 2005-08-30 Switch block and corresponding switch matrix, in particular for FPGA architectures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT001675A ITMI20041675A1 (it) 2004-08-30 2004-08-30 Blocco di commutazione e relativa matrice di commutazione, in particolare per architetture fpga.

Publications (1)

Publication Number Publication Date
ITMI20041675A1 true ITMI20041675A1 (it) 2004-11-30

Family

ID=36385622

Family Applications (1)

Application Number Title Priority Date Filing Date
IT001675A ITMI20041675A1 (it) 2004-08-30 2004-08-30 Blocco di commutazione e relativa matrice di commutazione, in particolare per architetture fpga.

Country Status (2)

Country Link
US (1) US7463055B2 (it)
IT (1) ITMI20041675A1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009107030A1 (en) * 2008-02-25 2009-09-03 Nxp B.V. Reconfigurable system
US7710148B2 (en) * 2008-06-02 2010-05-04 Suvolta, Inc. Programmable switch circuit and method, method of manufacture, and devices and systems including the same
US8878566B2 (en) * 2010-09-08 2014-11-04 Nec Corporation Reconfigurable circuit
KR20130066267A (ko) * 2011-12-12 2013-06-20 한국전자통신연구원 필드 프로그래머블 게이트 어레이의 스위치 블록 회로
US9106231B2 (en) * 2012-01-11 2015-08-11 Nec Corporation Bidirectional buffer and control method thereof
JP6125850B2 (ja) * 2012-02-09 2017-05-10 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の作製方法
US9654107B2 (en) * 2012-04-27 2017-05-16 Semiconductor Energy Laboratory Co., Ltd. Programmable LSI
JP6541376B2 (ja) 2014-03-13 2019-07-10 株式会社半導体エネルギー研究所 プログラマブルロジックデバイスの動作方法
JP6677449B2 (ja) * 2014-03-13 2020-04-08 株式会社半導体エネルギー研究所 半導体装置の駆動方法
US10229470B2 (en) * 2016-08-05 2019-03-12 Intel IP Corporation Mechanism to accelerate graphics workloads in a multi-core computing architecture

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5579356A (en) * 1995-07-28 1996-11-26 Micron Quantum Devices, Inc. Timer circuit with programmable decode circuitry
US5600264A (en) * 1995-10-16 1997-02-04 Xilinx, Inc. Programmable single buffered six pass transistor configuration
US6590419B1 (en) * 1999-10-12 2003-07-08 Altera Toronto Co. Heterogeneous interconnection architecture for programmable logic devices

Also Published As

Publication number Publication date
US20060103420A1 (en) 2006-05-18
US7463055B2 (en) 2008-12-09

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