JP2000040679A - 半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置の製造方法

Info

Publication number
JP2000040679A
JP2000040679A JP10209857A JP20985798A JP2000040679A JP 2000040679 A JP2000040679 A JP 2000040679A JP 10209857 A JP10209857 A JP 10209857A JP 20985798 A JP20985798 A JP 20985798A JP 2000040679 A JP2000040679 A JP 2000040679A
Authority
JP
Japan
Prior art keywords
wafer
main surface
integrated circuit
semiconductor integrated
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10209857A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000040679A5 (enExample
Inventor
Tadashi Ohashi
直史 大橋
Junji Noguchi
純司 野口
Toshinori Imai
俊則 今井
Hide Yamaguchi
日出 山口
Nobuo Owada
伸郎 大和田
Kenji Hinode
憲治 日野出
Yoshio Honma
喜夫 本間
Seiichi Kondo
誠一 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=16579782&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP2000040679(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority to JP10209857A priority Critical patent/JP2000040679A/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to TW088112316A priority patent/TW445534B/zh
Priority to US09/356,707 priority patent/US6376345B1/en
Priority to KR1019990029445A priority patent/KR100576630B1/ko
Publication of JP2000040679A publication Critical patent/JP2000040679A/ja
Priority to US10/050,562 priority patent/US6458674B1/en
Priority to US10/222,848 priority patent/US6531400B2/en
Priority to US10/369,716 priority patent/US6800557B2/en
Priority to US10/760,292 priority patent/US20040152298A1/en
Priority to KR1020040029620A priority patent/KR100683028B1/ko
Publication of JP2000040679A5 publication Critical patent/JP2000040679A5/ja
Priority to US11/357,181 priority patent/US7510970B2/en
Priority to US12/127,564 priority patent/US7659201B2/en
Priority to US12/700,784 priority patent/US8129275B2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/0209—Cleaning of wafer backside
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
JP10209857A 1998-07-24 1998-07-24 半導体集積回路装置の製造方法 Withdrawn JP2000040679A (ja)

Priority Applications (12)

Application Number Priority Date Filing Date Title
JP10209857A JP2000040679A (ja) 1998-07-24 1998-07-24 半導体集積回路装置の製造方法
TW088112316A TW445534B (en) 1998-07-24 1999-07-20 Manufacture of semiconductor integrated circuit device
US09/356,707 US6376345B1 (en) 1998-07-24 1999-07-20 Process for manufacturing semiconductor integrated circuit device
KR1019990029445A KR100576630B1 (ko) 1998-07-24 1999-07-21 반도체 집적회로장치의 제조방법
US10/050,562 US6458674B1 (en) 1998-07-24 2002-01-18 Process for manufacturing semiconductor integrated circuit device
US10/222,848 US6531400B2 (en) 1998-07-24 2002-08-19 Process for manufacturing semiconductor integrated circuit device
US10/369,716 US6800557B2 (en) 1998-07-24 2003-02-21 Process for manufacturing semiconductor integrated circuit device
US10/760,292 US20040152298A1 (en) 1998-07-24 2004-01-21 Process for manufacturing semiconductor integrated circuit device
KR1020040029620A KR100683028B1 (ko) 1998-07-24 2004-04-28 반도체 집적회로장치의 제조방법
US11/357,181 US7510970B2 (en) 1998-07-24 2006-02-21 Process for manufacturing semiconductor integrated circuit device
US12/127,564 US7659201B2 (en) 1998-07-24 2008-05-27 Process for manufacturing semiconductor integrated circuit device
US12/700,784 US8129275B2 (en) 1998-07-24 2010-02-05 Process for manufacturing semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10209857A JP2000040679A (ja) 1998-07-24 1998-07-24 半導体集積回路装置の製造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2003327905A Division JP2004104137A (ja) 2003-09-19 2003-09-19 半導体集積回路装置の製造方法
JP2004022381A Division JP4764604B2 (ja) 2004-01-30 2004-01-30 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
JP2000040679A true JP2000040679A (ja) 2000-02-08
JP2000040679A5 JP2000040679A5 (enExample) 2004-12-24

Family

ID=16579782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10209857A Withdrawn JP2000040679A (ja) 1998-07-24 1998-07-24 半導体集積回路装置の製造方法

Country Status (4)

Country Link
US (8) US6376345B1 (enExample)
JP (1) JP2000040679A (enExample)
KR (2) KR100576630B1 (enExample)
TW (1) TW445534B (enExample)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1093161A1 (en) * 1999-10-12 2001-04-18 Applied Materials, Inc. Method and composite arrangement inhibiting corrosion of a metal layer following chemical mechanical polishing
JP2001274123A (ja) * 2000-03-27 2001-10-05 Matsushita Electric Ind Co Ltd 基板研磨装置及び基板研磨方法
WO2001099168A1 (fr) * 2000-06-23 2001-12-27 Fujitsu Limited Dispositif a semi-conducteur et procede de fabrication associe
WO2001099173A3 (en) * 2000-06-22 2002-05-23 Applied Materials Inc Method of treating a substrate
JP2002246391A (ja) * 2001-02-21 2002-08-30 Nec Corp 半導体装置の製造方法
JP2004063589A (ja) * 2002-07-25 2004-02-26 Ebara Corp ポリッシング装置
US6797609B2 (en) * 1999-08-10 2004-09-28 Renesas Technology Corp. Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
US6833109B1 (en) 1999-03-26 2004-12-21 Nec Electronics Corporation Method and apparatus for storing a semiconductor wafer after its CMP polishing
US6897150B1 (en) 1999-11-19 2005-05-24 Nec Electronics Corporation Semiconductor wafer surface and method of treating a semiconductor wafer surface
JP2005141064A (ja) * 2003-11-07 2005-06-02 Kyocera Mita Corp 電子写真感光体および画像形成装置
JP4972257B2 (ja) * 1999-06-01 2012-07-11 東京エレクトロン株式会社 半導体装置の製造方法
JP2014220441A (ja) * 2013-05-10 2014-11-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法及び半導体製造装置

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JP2000040679A (ja) * 1998-07-24 2000-02-08 Hitachi Ltd 半導体集積回路装置の製造方法
US6572453B1 (en) * 1998-09-29 2003-06-03 Applied Materials, Inc. Multi-fluid polishing process
JP2000311876A (ja) * 1999-04-27 2000-11-07 Hitachi Ltd 配線基板の製造方法および製造装置
JP4513145B2 (ja) * 1999-09-07 2010-07-28 ソニー株式会社 半導体装置の製造方法および研磨方法
JP3510562B2 (ja) * 2000-04-28 2004-03-29 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法及び処理装置
US7170115B2 (en) * 2000-10-17 2007-01-30 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device and method of producing the same
JP2002319556A (ja) * 2001-04-19 2002-10-31 Hitachi Ltd 半導体集積回路装置の製造方法
JP4803625B2 (ja) * 2001-09-04 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6579798B2 (en) * 2001-09-24 2003-06-17 Texas Instruments Incorporated Processes for chemical-mechanical polishing of a semiconductor wafer
JP2003218084A (ja) * 2002-01-24 2003-07-31 Nec Electronics Corp 除去液、半導体基板の洗浄方法および半導体装置の製造方法
US20030154999A1 (en) * 2002-02-20 2003-08-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method for preventing chemical attack on a copper containing semiconductor wafer
JP2003318151A (ja) * 2002-04-19 2003-11-07 Nec Electronics Corp 半導体装置の製造方法
TWI288443B (en) 2002-05-17 2007-10-11 Semiconductor Energy Lab SiN film, semiconductor device, and the manufacturing method thereof
US6787470B2 (en) * 2002-05-17 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Sacrificial feature for corrosion prevention during CMP
JP2004186493A (ja) * 2002-12-04 2004-07-02 Matsushita Electric Ind Co Ltd 化学的機械研磨方法及び化学的機械研磨装置
US6936534B2 (en) * 2003-09-17 2005-08-30 Micron Technology, Inc. Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization
US7700477B2 (en) * 2004-02-24 2010-04-20 Panasonic Corporation Method for fabricating semiconductor device
US8159478B2 (en) * 2004-09-27 2012-04-17 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device using the same
US7863188B2 (en) * 2005-07-29 2011-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7521266B2 (en) * 2005-11-16 2009-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Production and packaging control for repaired integrated circuits
JP2008091698A (ja) * 2006-10-03 2008-04-17 Matsushita Electric Ind Co Ltd 基板処理装置および基板処理方法
US20090029490A1 (en) * 2007-07-26 2009-01-29 Baiocchi Frank A Method of fabricating an electronic device
US8231431B2 (en) * 2008-01-24 2012-07-31 Applied Materials, Inc. Solar panel edge deletion module
JP5291991B2 (ja) * 2008-06-10 2013-09-18 株式会社日立製作所 半導体装置およびその製造方法
US7838425B2 (en) * 2008-06-16 2010-11-23 Kabushiki Kaisha Toshiba Method of treating surface of semiconductor substrate
DE102009030292B4 (de) * 2009-06-24 2011-12-01 Siltronic Ag Verfahren zum beidseitigen Polieren einer Halbleiterscheibe
US8384214B2 (en) * 2009-10-13 2013-02-26 United Microelectronics Corp. Semiconductor structure, pad structure and protection structure
JP5404361B2 (ja) 2009-12-11 2014-01-29 株式会社東芝 半導体基板の表面処理装置及び方法
US8808459B1 (en) * 2010-09-01 2014-08-19 WD Media, LLC Method for cleaning post-sputter disks using tape and diamond slurry
CN102402635B (zh) * 2010-09-19 2014-03-05 复旦大学 一种针对耦合电容影响的化学机械抛光工艺哑元金属填充方法
US20120090648A1 (en) * 2010-10-15 2012-04-19 United Microelectronics Corp. Cleaning method for semiconductor wafer and cleaning device for semiconductor wafer
CN102485424B (zh) * 2010-12-03 2015-01-21 中芯国际集成电路制造(北京)有限公司 抛光装置及其异常处理方法
US9530676B2 (en) 2011-06-01 2016-12-27 Ebara Corporation Substrate processing apparatus, substrate transfer method and substrate transfer device
WO2013089502A1 (en) * 2011-12-16 2013-06-20 Lg Siltron Inc. Apparatus and method for polishing wafer
CN108203074B (zh) * 2016-12-19 2020-07-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制备方法
US11573189B2 (en) * 2019-01-11 2023-02-07 Microchip Technology Incorporated Systems and methods for monitoring copper corrosion in an integrated circuit device

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US6376345B1 (en) 2002-04-23
US20040152298A1 (en) 2004-08-05
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US7510970B2 (en) 2009-03-31
US20020192967A1 (en) 2002-12-19
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US6531400B2 (en) 2003-03-11
US20060141792A1 (en) 2006-06-29
US20030153187A1 (en) 2003-08-14
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