IN2012DN03251A - - Google Patents

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Publication number
IN2012DN03251A
IN2012DN03251A IN3251DEN2012A IN2012DN03251A IN 2012DN03251 A IN2012DN03251 A IN 2012DN03251A IN 3251DEN2012 A IN3251DEN2012 A IN 3251DEN2012A IN 2012DN03251 A IN2012DN03251 A IN 2012DN03251A
Authority
IN
India
Prior art keywords
substrate
core
terminals
coupled
layers
Prior art date
Application number
Other languages
English (en)
Inventor
Qing Ma
Chuan Hu
Patrick Morrow
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IN2012DN03251A publication Critical patent/IN2012DN03251A/en

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    • H—ELECTRICITY
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
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US12/653,722 US9420707B2 (en) 2009-12-17 2009-12-17 Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
PCT/US2010/054931 WO2011084216A2 (en) 2009-12-17 2010-11-01 Substrate for integrated circuit devices including multi-layer glass core and methods of making the same

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US20160322290A1 (en) 2016-11-03
US9420707B2 (en) 2016-08-16
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DE112010004888B4 (de) 2019-02-07
CN102656685A (zh) 2012-09-05
GB2488265A (en) 2012-08-22
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US9761514B2 (en) 2017-09-12
DE112010004888T5 (de) 2012-10-18
WO2011084216A2 (en) 2011-07-14
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CN105977234B (zh) 2020-03-06

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