IN2012DN03251A - - Google Patents

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Publication number
IN2012DN03251A
IN2012DN03251A IN3251DEN2012A IN2012DN03251A IN 2012DN03251 A IN2012DN03251 A IN 2012DN03251A IN 3251DEN2012 A IN3251DEN2012 A IN 3251DEN2012A IN 2012DN03251 A IN2012DN03251 A IN 2012DN03251A
Authority
IN
India
Prior art keywords
substrate
core
terminals
coupled
layers
Prior art date
Application number
Other languages
English (en)
Inventor
Qing Ma
Chuan Hu
Patrick Morrow
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IN2012DN03251A publication Critical patent/IN2012DN03251A/en

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    • HELECTRICITY
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    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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DE112010004888T5 (de) 2012-10-18
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US9761514B2 (en) 2017-09-12
US9420707B2 (en) 2016-08-16
GB201208343D0 (en) 2012-06-27
TWI467717B (zh) 2015-01-01
GB2488265B (en) 2014-04-30
KR101466582B1 (ko) 2014-11-28
GB2488265A (en) 2012-08-22
US20160322290A1 (en) 2016-11-03
WO2011084216A3 (en) 2011-09-09
CN102656685A (zh) 2012-09-05
WO2011084216A2 (en) 2011-07-14
CN105977234A (zh) 2016-09-28
DE112010004888B4 (de) 2019-02-07
JP2013512583A (ja) 2013-04-11
KR20120095420A (ko) 2012-08-28
TW201138033A (en) 2011-11-01

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