EP2693472A3 - Power semiconductor module and its method of manufacturing - Google Patents

Power semiconductor module and its method of manufacturing Download PDF

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Publication number
EP2693472A3
EP2693472A3 EP13177852.4A EP13177852A EP2693472A3 EP 2693472 A3 EP2693472 A3 EP 2693472A3 EP 13177852 A EP13177852 A EP 13177852A EP 2693472 A3 EP2693472 A3 EP 2693472A3
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EP
European Patent Office
Prior art keywords
level
semiconductor devices
dielectric layer
module
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP13177852.4A
Other languages
German (de)
French (fr)
Other versions
EP2693472A2 (en
EP2693472B1 (en
Inventor
Arun Virupakska Gowda
Paul Alan Mcconnelee
Shakti Singh Chauhan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
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Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of EP2693472A2 publication Critical patent/EP2693472A2/en
Publication of EP2693472A3 publication Critical patent/EP2693472A3/en
Application granted granted Critical
Publication of EP2693472B1 publication Critical patent/EP2693472B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

A surface mount packaging structure (10) that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure (10) includes a sub-module (14) having a dielectric layer (30), semiconductor devices (12) attached to the dielectric layer (30), a first level metal interconnect structure (38) electrically coupled to the semiconductor devices (12), and a second level I/O connection (16) electrically coupled to the first level interconnect (38) and formed on the dielectric layer (30) on a side opposite the semiconductor devices (12), with the second level I/O connection (16) configured to connect the sub-module (14) to an external circuit. The semiconductor devices (12) of the sub-module (14) are attached to the first surface of a multi-layer substrate (18) structure, with a dielectric material (26) positioned between the dielectric layer (30) and the multi-layer substrate structure (18) to fill in gaps (58) in the surface-mount structure (10) and provide additional structural integrity thereto.
EP13177852.4A 2012-07-30 2013-07-24 Power semiconductor module and its method of manufacturing Active EP2693472B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/561,811 US8941208B2 (en) 2012-07-30 2012-07-30 Reliable surface mount integrated power module

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EP2693472A2 EP2693472A2 (en) 2014-02-05
EP2693472A3 true EP2693472A3 (en) 2017-08-09
EP2693472B1 EP2693472B1 (en) 2022-12-14

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EP (1) EP2693472B1 (en)
JP (1) JP6302184B2 (en)
KR (1) KR102088692B1 (en)
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KR102088692B1 (en) 2020-03-13
JP6302184B2 (en) 2018-03-28
EP2693472A2 (en) 2014-02-05
US9184124B2 (en) 2015-11-10
TW201413916A (en) 2014-04-01
EP2693472B1 (en) 2022-12-14
JP2014027272A (en) 2014-02-06
CN103579137A (en) 2014-02-12
CN110060962B (en) 2023-09-26
TWI587477B (en) 2017-06-11
US8941208B2 (en) 2015-01-27
CN110060962A (en) 2019-07-26
US20140029234A1 (en) 2014-01-30
KR20140016204A (en) 2014-02-07
CN103579137B (en) 2020-03-13
CN111508909A (en) 2020-08-07
US20150069612A1 (en) 2015-03-12
SG196753A1 (en) 2014-02-13

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