CN2613046Y - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
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- CN2613046Y CN2613046Y CNU032465173U CN03246517U CN2613046Y CN 2613046 Y CN2613046 Y CN 2613046Y CN U032465173 U CNU032465173 U CN U032465173U CN 03246517 U CN03246517 U CN 03246517U CN 2613046 Y CN2613046 Y CN 2613046Y
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- chip
- substrate
- interconnect layer
- multilayer interconnect
- packaging structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The utility model discloses a chip sealing structure and the manufacturing craft, wherein the chip sealing manufacturing craft is a manufacturing craft making use of high precise thin line, such as TFT-LCD manufacturing craft, IC manufacturing craft or a manufacturing craft with other high density base plate which is used to strengthen the line distribution density and decrease the electric connecting length to reach a manifestation of high electric property. Firstly one basic plate is regarded as a hard basic plate, wherein the basic plate is equipped with at least one slot hole, the material of the basic plate can be ceramic, glass or metal, and the basic plate can be a printing circuit board, then an embedding block is embedded to the slot hole which forms a multiple layer inner connection device layer on the basic plate with a high density welding pad (a convex pad) and micro thin line, then the embedding block is removed, the chip is embedded on the slot hole on the basic plate, the chip goes across the source surface, and is connected with the multiple layer inner connection device layer by way of covering plates connection, and is electrically connected with the internal lines of the multiple layer inner connection device layer.
Description
Technical field
The utility model relates to a kind of chip-packaging structure and manufacturing process thereof, and is particularly related to a kind of chip-packaging structure and manufacturing process thereof with highdensity contact and fine circuit.
Background technology
Cover chip bonding technology (Flip Chip Interconnect Technology, be called for short FC) be the mode of utilizing face array (area array), a plurality of chip mats (die pad) are disposed on the active surface (active surface) of chip (die), and on chip mat, form projection (bump), then chip is overturned (flip) after, utilize these projections to come respectively chip mat that electrically (electrically) and structural (mechanically) the connect chip contact (contact) to the carrier (carrier) again, make chip can be electrically connected to carrier, and be electrically connected to extraneous electronic installation via the internal wiring of carrier via projection.It should be noted that, owing to cover the chip-packaging structure of chip bonding technology (FC) applicable to high pin number (High Pin Count), and have the Chip Packaging of dwindling area simultaneously and shorten plurality of advantages such as signal transmission path, be widely used in the Chip Packaging field at present so cover the chip bonding technology, the chip-packaging structure that the chip bonding technology is covered in common application for example has the sheet of covering sphere grid array type (F1ip Chip Ball Grid Array, FC/BGA) and cover sheet Pga type (Flip ChipPin Grid Array, the chip-packaging structure of kenel such as FC/PGA).
Please refer to Fig. 1, it illustrates traditional a kind of generalized section of covering the chip-packaging structure of sheet sphere grid array type.Chip-packaging structure 100 comprises substrate (substrate) 110, a plurality of projection 120, chip 130, reaches a plurality of soldered balls 140.Wherein, substrate 110 has an end face 112 and a corresponding bottom surface 114, and substrate 110 has more a plurality of bump pads (bump pad) 116a and a plurality of solder ball pad (ball pad) 116b.In addition, chip 130 has an active surface (active surface) 132 and a corresponding back side 134, the one side with active block (activedevice) (not shown) of the active surperficial 132 general reference chips 130 of its chips 130, and chip 130 has more a plurality of chip mats 136, it is disposed at active surperficial 132 of chip 130, in order to export as the signal of chip 130 into media, wherein the position of these bump pads 116a corresponds respectively to the position of these chip mats 136.In addition, 120 difference of these projections electrically reach one of these chip mats 136 of structural connection to one of its pairing these bump pads 116a.And 140 of these soldered balls are disposed at respectively on these solder ball pads 116b, in order to electrically to reach the structural extraneous electronic installation that is connected to.
Please equally with reference to figure 1; one primer (underfill) 150 is filled in active surperficial 132 spaces that surrounded of the end face 112 and the chip 130 of substrate 110; in order to the part of protecting bump pads 116a, chip mat 136 and projection 120 to be exposed, and cushion the unmatched phenomenon of thermal stress (thermal stress) that when being heated, is produced between substrate 110 and the chip 130 simultaneously.Therefore, the chip mat 136 of chip 130 can electrically reach the structural bump pads 116a that is connected to substrate 110 via projection 120, coiling (routing) downwards electrically reaches the structural extraneous electronic installation that is connected at last to the solder ball pad 116b of the bottom surface 114 of substrate 110 via the soldered ball on the solder ball pad 116b 140 via the internal wiring 118 of substrate 110 again.
The arithmetic speed that improves chip and reduce chip manufacturing cost considering down, both inevitablely little by little dwindle the gap between area of chip and the chip mat, meaning is the relatively little by little rising of density of chip mat.Therefore, when adopting, the chip with superchip pad covers sheet (FC) kenel, and arrange in pairs or groups simultaneously sphere grid array (BGA) or pin lattice array kenels such as (PGA) are when encapsulating, because the spacing of the adjacent chip mat of chip is all very small, must adopt the substrate with high density bump pads and fine circuit this moment, chip could be disposed at the end face of substrate in the mode of covering chip bonding, and via the coiling again of the internal wiring of substrate, and the chip mat of chip is extended the bottom surface that is distributed to substrate, via the soldered ball (ball) or the stitch contacts such as (pin) of the bottom surface that is positioned at substrate, make chip can be electrically connected to extraneous electronic installation at last again.
As mentioned above, the common material of covering sheet sphere grid array type (FC/BGA) at present or covering the substrate of sheet Pga type (FC/PGA) includes pottery (ceramic) and organic material (organicmaterial) etc., and is comparatively common as organic substrate (organic substrate) of the material of dielectric layer (dielectric layer) with organic material again at present.It should be noted that, because organic substrate is subjected to the having a strong impact on of thermal expansion (thermal expansion) of dielectric layer, make that but its live width of lead and the line-spacing of organic substrate of scale of mass production only can reach 25 microns and 25 microns respectively now, so be difficult to form fine internal wiring.Simultaneously, organic substrate must be used as the internal structure of organic substrate with a core flaggy, and simultaneously increase layer (a build up) by the both sides up and down of core flaggy, in order to form multi-layer conductor leads layer (for example 1/2/1 layer or 2/2/2 layer) respectively, in other words, traditional manufacturing process can't form the single side of conductor layer in the core flaggy, makes the internal wiring of organic substrate can't be formed on the same side of core flaggy.
The utility model content
In view of this, the purpose of this utility model just provides a kind of chip-packaging structure and manufacturing process thereof, the multilayer interconnect layer (multi-layerinterconnect layer) of high density weld pad (bump pads) and fine circuit can be provided, and can effectively reduce the cost of manufacture of chip-packaging structure.
For reaching above-mentioned purpose of the present utility model, the utility model proposes a kind of chip-packaging structure, mainly constituted by a substrate, a multilayer interconnect layer and a chip.Substrate has an end face and a corresponding bottom surface, and substrate has more a slotted eye, and wherein slotted eye runs through substrate, and connects end face and bottom surface.In addition, multilayer interconnect layer has a first surface and a corresponding second surface, and multilayer interconnect layer is disposed at the end face of substrate via first surface, and the end near end face of closed trench hole, and multilayer interconnect layer has an internal wiring.In addition, chip has an active surface and a corresponding back side, and its chips embeds the slotted eye of substrate, and chip is via active surface, and covering the mode of chip bonding, the structural first surface that is connected to multilayer interconnect layer, and be electrically connected on the internal wiring of multilayer interconnect layer.
For reaching above-mentioned purpose of the present utility model, the utility model proposes a kind of Chip Packaging manufacturing process, comprising: a substrate (a) is provided, wherein substrate has an end face and a corresponding bottom surface, and substrate has a slotted eye, and slotted eye runs through substrate, and connects end face and bottom surface; (b) embed a chimeric block in slotted eye, and chimeric block has a chimeric surface, and chimeric surface in alignment is in the end face of substrate; (c) form a multilayer interconnect layer in the chimeric surface of the end face and the chimeric block of substrate, wherein multilayer interconnect layer has a first surface and a corresponding second surface, and multilayer interconnect series of strata are via first surface, and be disposed at the chimeric surface of the end face and the chimeric block of substrate, and multilayer interconnect layer has an internal wiring; (d) remove chimeric block; And (e) embed a chip in the slotted eye of substrate, its chips has an active surface and a corresponding back side, and chip is via active surface, and to cover the mode of chip bonding, and the structural first surface that is connected to multilayer interconnect layer, and be electrically connected at the internal wiring of multilayer interconnect layer.
Therefore, the utility model is the manufacturing process technology that utilizes liquid crystal display panel of thin film transistor (TFT-LCDpanel), the manufacturing process technology of integrated circuit (IC) or the manufacturing process technology of high-density base board with and produce board separately, at first with substrate as a hard floor, and embed a chimeric block in the slotted eye of substrate, then form one and have the multilayer interconnect layer of high density weld pad (bump pads) and fine circuit on substrate, remove chimeric block afterwards, at last again chip is embedded in the slotted eye of substrate, and to cover the mode of chip bonding, make chip electrically to reach and structurally be connected to multilayer interconnect layer, and finish Chip Packaging manufacturing process of the present utility model.
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Description of drawings
Fig. 1 illustrates traditional a kind of generalized section of covering the chip-packaging structure of sheet sphere grid array type; And
Fig. 2 A to 2F illustrates the schematic flow sheet of a kind of Chip Packaging manufacturing process of the utility model one preferred embodiment successively.
Wherein, being described as follows of Reference numeral:
100: chip-packaging structure 110: substrate
112: end face 114: bottom surface
116a: bump pads 116b: solder ball pad
120: projection 130: chip
132: active surperficial 134: the back side
136: chip mat 140: soldered ball
150: primer
Embodiment
Please refer to Fig. 2 A to 2F, it illustrates the schematic flow sheet of a kind of Chip Packaging manufacturing process of the utility model one preferred embodiment successively.Please refer to Fig. 2 A, one substrate 210 at first is provided, substrate 210 has an end face 212 and a corresponding bottom surface 214, and substrate 210 has at least one slotted eye 216, and end face 212 and the bottom surface 214 of for example running through substrate 210 in modes such as ultrasonic waves pore-forming, laser hole burning, mechanical type boring or chemical etchings form slotted eye 216.In addition, the material of substrate 210 for example is pottery, glass or metal, and substrate 210 also can be cheaply printed circuit board (PCB) (Printed CircuitBoard, PCB).Then please refer to Fig. 2 B, embed a chimeric block 220 in slotted eye 216, and chimeric block 220 has one chimeric surperficial 222, and chimeric surperficial 222 be the end face 212 that is aligned in substrate 210, make end face 212 and chimeric surperficial 222 of the chimeric block 220 of substrate 210 can form the surface of a planarization jointly, wherein the end face 214 of substrate 210 and chimeric surperficial 222 of chimeric block 220 must have the flatness (co-planarity) of higher level, to improve the manufacturing process yield of follow-up fine circuit.In addition, the outer surface of chimeric block 220 for example forms a glue-line (thermal release tape) 224 or solder layer (solder layer), and chimeric block 220 is via the stickiness of glue-line 224 or solder layer, and relative positioning is in slotted eye 216, and in follow-up manufacturing process, can also heat the stickiness that glue-line 224 reduces glue-line 224, conveniently to remove chimeric block 220.
Then please refer to Fig. 2 C, form a multilayer interconnect layer 230 in chimeric surperficial 222 of the end face 212 of substrate 210 and chimeric block 220, wherein multilayer interconnect layer 230 mainly comprises an isolated bottom (isolation base layer) 232, the multi-layer conductor leads layer 234 of patterning, at least one dielectric layer 236 and a plurality of conductive plunger 238, and these conductor layers 234 are to be overlapped in regular turn on the isolated bottom 232, dielectric layer 236 then is disposed between the two adjacent conductor layers 234, and these conductive plungers 238 run through dielectric layer 236 respectively and electrically connect two adjacent conductor layers 234, and these conductor layers 234 and these conductive plungers 238 formation one internal wirings (inner circuit) 240.Wherein internal wiring 240 is isolated mutually with substrate 210 by isolated bottom 232, and isolated bottom 232 for example is a dielectric materials layer, more can form at least one lead connector 246 in isolated bottom 232, so that internal wiring 240 can electrically connect substrate 210 via conductive plunger 246.
Shown in Fig. 2 C, internal wiring 240 forms a plurality of bump pads 242 at the first surface 230a of multilayer interconnect layer 230, and bump pads 242 correspondences are positioned at the scope that the slotted eye 216 of substrate 210 is surrounded.In addition, internal wiring 240 more forms a plurality of joint sheets 244 at the second surface 230b of multilayer interconnect layer 230, in order to connecting contact 290 (shown in Fig. 2 F), and contact 290 is disposed on the second surface 230b of multilayer interconnect layer 230 in the mode of face array.In addition, the material of inner online 240 conductor layer 234 for example is copper, aluminium and these alloys, and the material of dielectric layer 236 for example is silicon nitride (silicon nitride) and silica (silicon oxide) or other organic dielectric medium etc.It should be noted that in order to protect the conductor layer 234 of top layer the one anti-layer (soldermask) 250 that more can form patterning and exposes joint sheet 244 on the conductor layer 234 of top layer.
Equally shown in Fig. 2 C, because the utility model can utilize the high density manufacturing process technology of display panels or integrated circuit, form this multilayer interconnect layer 230 on substrate 210, make that live width and its scope of line-spacing of internal wiring 240 of multilayer interconnect structure 230 all can be between 1 to several microns scope.Therefore, with traditional shown in Figure 1 with the organic material be the dielectric layer material substrate 110 by contrast, produced herein multilayer interconnect layer 230 can provide more high density weld pad (bump pads) and finer circuit.In addition, when formation multilayer interconnect layer 230 is on substrate 210, more can set passive component (passive component) (not shown) simultaneously in the inside of multilayer interconnect layer 230, and be electrically connected at the internal wiring 240 of multilayer interconnect layer 230, or utilize the special coiling design of internal wiring 240 to form passive components such as electric capacity and inductance.
Equally shown in Fig. 2 C, before Chip Packaging, electrically normal for the internal wiring 240 of guaranteeing multilayer interconnect layer 230, can carry out the testing electrical property (electricaltest) of the internal wiring 240 of multilayer interconnect layer 230 in advance, so can guarantee follow-up with Chip Packaging behind multilayer interconnect layer 230, this chip-packaging structure can normal operation.At first, come testing inner circuit 240 via a plurality of spy point (not shown) contact joint sheets 244, and form a measurement circuit 226 in chimeric surperficial 222 of chimeric block 220, and the bump pads 242 of multilayer interconnect layer 230 is connected in measurement circuit 226, and via the internal wiring 240 of measurement circuit 226 testing electrical property multilayer interconnect layers 230.Because multilayer interconnect layer 230 is through behind the testing electrical property, can detect in good time can't normal operation partial circuit, with guarantee follow-up with Chip Packaging behind multilayer interconnect layer 230, this chip-packaging structure can normal operation, and then improves the qualification rate of manufacturing process.
Then please refer to Fig. 2 D, remove chimeric block 220,, and expose the bump pads 242 of the first surface 230a of multi-level interconnect 230 so that the bottom surface 214 of substrate 210 forms original slotted eye 216.Because chimeric block 220 is with glue-line 224 (or solder layer), and be embedded in the slotted eye 216 of substrate 210, so only need heat glue-line 224 (or solder layer),, the slotted eye 216 of chimeric block 220 from substrate 210 can be removed to reduce the stickiness of glue-line 224 (or solder layer).
Then please refer to Fig. 2 E, embed a chip 260 in the slotted eye 216 of substrate 210, its chips 260 has one active surperficial 262 and a corresponding back side 264, and chip has more a plurality of chip mats 266, and it is positioned at active surperficial 262 of chip 216.In addition, more a plurality of projections 268 are electrically reached structural connection chip mat 266 and bump pads 242 respectively, so can cover the mode of chip bonding, chip 260 is disposed on the first surface 230a of multilayer interconnect layer 230, and chip 260 is electrically connected at the internal wiring 240 of multilayer interconnect layer 230.So, promptly finish chip-packaging structure 200, active surperficial 262 of its chips 260 for example forms a primer layer 270, and primer layer 270 can surround projection 268, so need not insert primer extraly to the space that is surrounded between chip 260 and the multilayer interconnect layer 230.
Then please refer to Fig. 2 F, finish cover chip bonding after, this chip-packaging structure more can be inserted a sealing 272 in the space that chip 260, multilayer interconnect layer 230 and substrate 210 are surrounded, in order to coating chip 260.In addition, the back side 264 of chip 260 and the bottom surface 214 of substrate 210 more optionally dispose a fin 280, its material is the good material of thermal diffusivity, for example copper, aluminium and these alloy, conduct to the surface of chip-packaging structure 200 apace in order to the heat energy that chip 260 is produced when the working at high speed, use the heat dissipation that improves chip-packaging structure 200.Moreover, also configurable a plurality of contacts 290 on the surface of joint sheet 244, in order to connect outside electronic installation (not shown), and contact 290 for example is a soldered ball (ball) or a stitch (pin), covers sheet sphere grid array type (FC/BGA) or covers the chip-packaging structure of sheet Pga type (FC/PGA) in order to formation.
Shown in Fig. 2 F, in above-mentioned chip-packaging structure 200, be not defined as the single-chip package structure, only need change the position and the quantity of the slotted eye 216 of substrate 210 slightly, promptly applicable to encapsulating a plurality of chips 260 on single substrate 210, and the corresponding respectively slotted eye 216 that is arranged in substrate 210 of these chips 260 one, and chip 260 can electrically connect mutually via the internal wiring 240 of multilayer interconnect layer 230, so chip-packaging structure 200 will can be applicable to multiple chip module (Multi-Chip Module, MCM) and system (System In Package SIP) waits chip-packaging structure in single encapsulation.
Shown in Fig. 2 C, because the material of substrate 210 can be conductive material such as metal, therefore can utilize the earth terminal of substrate 210 as chip-packaging structure 200, its mode is for example shown in Fig. 2 C, form at least one conductive plunger 246 on the first surface 230a of multilayer interconnect layer 230, and conductive plunger 246 architecture are connected in the end face 212 of substrate 210, and are electrically connected at substrate 210, and the ground path of multilayer interconnect layer 230 is via conductive plunger 246, and is electrically connected on substrate 210.So, the substrate 210 that the internal wiring 240 of chip-packaging structure 200 can a good conductivity increases the area of its earth terminal.
In addition, the partial enlarged drawing in the lower left corner shown in Fig. 2 F, substrate 210 also can be a printed circuit board (PCB), it has a base plate line 218, and the first surface 230a of multilayer interconnect layer 230 has at least one conductive plunger 246, wherein conductive plunger 246 architecture are connected in the end face 212 of substrate 210, and be electrically connected at the base plate line 218 of substrate 210, make that the internal wiring 240 of multilayer interconnect layer 230 can be via conductive plunger 246, and be electrically connected at the base plate line 218 of substrate 210.So, chip-packaging structure 200 is laid the fine circuit except the internal wiring 240 that utilizes multilayer interconnect layer 230, more the base plate line 218 that can utilize substrate 210 to be provided increases the laying space, amasss so can improve the overall wire road surface of chip-packaging structure 200.
As shown in the above description, chip-packaging structure of the present utility model and manufacturing process thereof are as base plate with a substrate, wherein substrate has as the slotted eye as the die size, and the material of substrate can be pottery, glass or metal, and substrate also can be a printed circuit board (PCB), then be embedded in the slotted eye with a chimeric block again, and form one and have the multilayer interconnect layer of high density weld pad (bump pads) and fine circuit on substrate, then remove chimeric block, and again chip is embedded in the slotted eye of substrate, and chip is via active surface, and to cover the mode of chip bonding, the structural surface that is connected in this multilayer interconnect layer, and be electrically connected at the internal wiring of multilayer interconnect layer, obtain a chip-packaging structure at last.
In sum, chip-packaging structure of the present utility model and manufacturing process thereof have following advantage:
1. the utility model is manufacturing process technology and the production board with display panels or integrated circuit, integrated and be applied to Chip Packaging manufacturing process of the present utility model, it should be noted that, because the manufacturing process technology of display panels, integrated circuit or high-density base board is ripe in the extreme at present, so following in the situation of scale of mass production, the cost of manufacture that can significantly reduce chip-packaging structure.
2. the utility model is to utilize a plurality of probe contact joint sheets to come the testing inner circuit, and the chimeric surface of chimeric block also forms a measurement circuit, and through measurement circuit thus, come the internal wiring of testing electrical property multilayer interconnect layer whether normal, after multilayer interconnect layer, so can effectively improve the manufacturing process qualification rate of chip-packaging structure in follow-up Chip Packaging.
3. because the utility model utilizes the manufacturing process technology of display panels, the live width of the lead that it can be produced and line-spacing all can reach 1 micron, even less than 1 micron, so under the situation that the density of the chip mat of chip raises gradually, Chip Packaging manufacturing process of the present utility model can cooperate the density of the chip mat of chip fully, and provide the multilayer interconnect layer of high density weld pad (bump pads) and fine circuit, be easier to control the unit electrical resistance of the lead of multilayer interconnect layer simultaneously, to improve the electrical properties of chip-packaging structure.
4. in chip-packaging structure of the present utility model, because chimeric block is via glue-line (or solder layer), and be embedded in the slotted eye of substrate, so only need heat glue-line (or solder layer), in order to reduce the stickiness of glue-line (or solder layer), chimeric block can be removed slotted eye in substrate.
5. in chip-packaging structure of the present utility model, more can embed multiple chips or other passive component in a plurality of slotted eyes of substrate, make chip-packaging structure of the present utility model will can be applicable to multiple chip module (MCM) and system in single encapsulation Chip Packaging kenels such as (SIP).
Though the utility model with a preferred embodiment openly as above; right its is not in order to limit the utility model; those skilled in the art; in not breaking away from spirit and scope of the present utility model; when doing a little change and retouching, therefore protection range of the present utility model is when requiring to be as the criterion with appended power.
Claims (10)
1. a chip-packaging structure is characterized in that, this structure comprises:
One substrate has an end face and a corresponding bottom surface, and this substrate has more a slotted eye, and wherein this slotted eye runs through this substrate, and connects this end face and this bottom surface;
One multilayer interconnect layer, have a first surface and a corresponding second surface, and this multilayer interconnect layer is disposed at this end face of this substrate via this first surface, and seals the end near this end face of this slotted eye, and this multilayer interconnect layer has an internal wiring; And
One chip, has an active surface and a corresponding back side, wherein this chip system embeds this slotted eye of this substrate, and this chip is via this active surface, and to cover the mode of chip bonding, structural this first surface that is connected to this multilayer interconnect layer, and be electrically connected on this internal wiring of this multilayer interconnect layer.
2. chip-packaging structure as claimed in claim 1 is characterized in that, the material of this substrate comprise pottery, glass and metal one of them.
3. chip-packaging structure as claimed in claim 1 is characterized in that, the material of this substrate is a conductive material.
4. chip-packaging structure as claimed in claim 3, it is characterized in that, this multilayer interconnect layer has more at least one conductive plunger, and structural this end face that is connected to this substrate of this conductive plunger, and be electrically connected on this substrate, and this internal wiring of this multilayer interconnect layer is via this conductive plunger, and is electrically connected on this substrate.
5. chip-packaging structure as claimed in claim 1 is characterized in that this substrate is a printed circuit board (PCB), and has a base plate line.
6. chip-packaging structure as claimed in claim 5, it is characterized in that, this multilayer interconnect layer has more at least one conductive plunger, and structural this end face that is connected in this substrate of this conductive plunger, and be electrically connected on this base plate line of this substrate, and this internal wiring of this multilayer interconnect layer is via this conductive plunger, and is electrically connected on this base plate line of this substrate.
7. chip-packaging structure as claimed in claim 1 is characterized in that, more comprises a sealing, and it is filled in the space that is surrounded between this chip, this multilayer interconnect layer and this substrate.
8. chip-packaging structure as claimed in claim 1 is characterized in that, more comprises a fin, and it is disposed at this back side of this chip and this bottom surface of this substrate.
9. chip-packaging structure as claimed in claim 1 is characterized in that, more comprises a plurality of contacts, its structural this second surface that is connected to this multilayer interconnect layer, and be electrically connected at this internal wiring of this multilayer interconnect layer.
10. chip-packaging structure as claimed in claim 1 is characterized in that, more comprises at least one passive component, and it is embedded in the inside of this multilayer interconnect layer, and this passive component system is electrically connected at this internal wiring of this multilayer interconnect layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU032465173U CN2613046Y (en) | 2003-04-17 | 2003-04-17 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU032465173U CN2613046Y (en) | 2003-04-17 | 2003-04-17 | Chip packaging structure |
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| CN2613046Y true CN2613046Y (en) | 2004-04-21 |
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| CNU032465173U Expired - Lifetime CN2613046Y (en) | 2003-04-17 | 2003-04-17 | Chip packaging structure |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100341124C (en) * | 2005-03-10 | 2007-10-03 | 威盛电子股份有限公司 | Package process of chip built-in type |
| CN100437958C (en) * | 2005-11-03 | 2008-11-26 | 台湾应解股份有限公司 | Chip capsulation structure, and fabricating method |
| US7539022B2 (en) | 2005-10-04 | 2009-05-26 | Phoenix Precision Technology Corporation | Chip embedded packaging structure |
| CN101304013B (en) * | 2007-05-11 | 2010-08-11 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing top layer metallic layer on encapsulation chip from fracturing |
| CN101866898A (en) * | 2009-04-15 | 2010-10-20 | 国际商业机器公司 | The metal wiring structure that is used for C4 ball uniform current density |
| CN102194803A (en) * | 2010-03-01 | 2011-09-21 | 南茂科技股份有限公司 | Semiconductor structure |
| CN101567344B (en) * | 2008-04-21 | 2012-03-21 | 宏齐科技股份有限公司 | Semiconductor chip encapsulating structure capable of reaching front-surface electric conduction and preparing method thereof |
| CN101536181B (en) * | 2006-11-06 | 2012-06-06 | 日本电气株式会社 | Semiconductor device and method for manufacturing same |
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| CN101567344B (en) * | 2008-04-21 | 2012-03-21 | 宏齐科技股份有限公司 | Semiconductor chip encapsulating structure capable of reaching front-surface electric conduction and preparing method thereof |
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| CN110060962A (en) * | 2012-07-30 | 2019-07-26 | 通用电气公司 | Reliable surface is installed by overall power module |
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| WO2014154139A1 (en) * | 2013-03-27 | 2014-10-02 | 苏州远创达科技有限公司 | Electronic component mounting structure, manufacturing method and electronic component product |
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| CN105244329A (en) * | 2014-07-07 | 2016-01-13 | 英飞凌科技奥地利有限公司 | Electronic component and method for dissipating heat from a semiconductor die |
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