CN101567344B - Semiconductor chip encapsulating structure capable of reaching front-surface electric conduction and preparing method thereof - Google Patents
Semiconductor chip encapsulating structure capable of reaching front-surface electric conduction and preparing method thereof Download PDFInfo
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- CN101567344B CN101567344B CN 200810091203 CN200810091203A CN101567344B CN 101567344 B CN101567344 B CN 101567344B CN 200810091203 CN200810091203 CN 200810091203 CN 200810091203 A CN200810091203 A CN 200810091203A CN 101567344 B CN101567344 B CN 101567344B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 152
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000002093 peripheral effect Effects 0.000 claims abstract description 15
- 238000003466 welding Methods 0.000 claims description 92
- 238000005538 encapsulation Methods 0.000 claims description 53
- 239000000463 material Substances 0.000 claims description 48
- 239000004020 conductor Substances 0.000 claims description 37
- 238000003860 storage Methods 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 31
- 239000011810 insulating material Substances 0.000 claims description 27
- 238000009413 insulation Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000012780 transparent material Substances 0.000 claims description 14
- 238000007772 electroless plating Methods 0.000 claims description 10
- 238000007493 shaping process Methods 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000007639 printing Methods 0.000 claims description 8
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 5
- 238000005507 spraying Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 abstract description 14
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 208000034189 Sclerosis Diseases 0.000 description 2
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- 239000002184 metal Substances 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01056—Barium [Ba]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention provides a semiconductor chip encapsulating structure capable of reaching front -surface electric conduction and a preparing method thereof. The encapsulating structure comprises an encapsulating unit, a semiconductor chip, a base plate unit, a first insulating unit, a first conducting unit, a second conducting unit and a second insulating unit, wherein the encapsulating unit is provided with a central containing slot for containing the semiconductor chip and a peripheral containing slot used for containing the base plate unit, the semiconductor chip is provided with a plurality of conducting bonding pads, the first insulating unit is provided with a first insulating layer formed among a plurality of conducting bonding pads, the first conducting unit is provided with a plurality of first conducting layers, the second conducting unit is provided with a plurality of second conducting layers formed on a plurality of first conducting layers, and the second insulating unit is formed among a plurality of first conducting layers and a plurality of second conducting layers. The invention can save the wire-bond technology and avoid the condition of poor electric contact causedby wire bonding.
Description
Technical field
The present invention especially need can not reach semiconductor chip package (semiconductor chip package structure) of electrical connection and preparation method thereof through routing technology (wire-bonding process) relevant for a kind of relevant for a kind of semiconductor chip package and preparation method thereof.
Background technology
See also shown in Figure 1ly, it is the generalized section of the known package structure for LED made from routing technology (wire-bonding process).By knowing that known package structure for LED comprises among the figure: underlying structure 1, a plurality of light-emitting diode 2 that is arranged at this underlying structure 1 upper end, many leads 3, and a plurality of fluorescent colloids 4.
Wherein, Each light-emitting diode 2 is with its light output surface 20 this underlying structure 1 and being arranged on this underlying structure 1 dorsad, and the positive and negative electrode of each light-emitting diode 2 upper end zone 21,22 through two leads 3 to be electrically connected on the corresponding positive and negative electrode zone 11,12 of this underlying structure 1.Moreover each fluorescent colloid 4 is covered in this corresponding light-emitting diode 2 and two lead 3 upper ends, with this corresponding light-emitting diode 2 of protection.
Yet known routing technology also must be worried to take place because of routing has condition of poor electric contact except increasing fabrication schedule and cost sometimes.Moreover; Because an end of these two leads 3 all is arranged at the positive and negative electrode zone 21,22 of these light-emitting diode 2 upper ends; Therefore when this light-emitting diode 2 carries out ray cast through this light output surface 20, these two leads 3 will cause cast shadow, and reduce the luminescent quality of this light-emitting diode 2.
By on can know that present known package structure for LED obviously has inconvenience and exists with defective, and waits to improve.
Therefore, the above-mentioned defective of inventor's thoughts can be improved, and according to the correlation experience of being engaged in for many years in this respect, proposes a kind of reasonable in design and effectively improve the present invention of above-mentioned defective.
Prior art
1 underlying structure, 11 positive electrodes zone
12 negative electrode area
2 light-emitting diodes, 20 light-emitting areas
21 electrode zones
22 negative electrode area
3 leads
4 fluorescent colloids
The present invention
First embodiment
1a base board unit 10a perforation
The 200a positive terminal pad
The 201a negative terminal pad
The 202a light-emitting area
The 3a encapsulation unit
The 4a first conductive unit 40a first conductive layer
The 5a second conductive unit 50a second conductive layer
A tack macromolecular material
The Ba insulating material
C1a first electric conducting material
C2a second electric conducting material
Second embodiment
1b base board unit 10b perforation
21b first insulating barrier
The 200b positive terminal pad
The 201b negative terminal pad
The 202b light-emitting area
The 3b encapsulation unit
The 4b first conductive unit 40b first conductive layer
The 5b second conductive unit 50b second conductive layer
6b second insulation unit 60b second insulating barrier
A tack macromolecular material
B1b first insulating material
B2b first insulating material
C1b first electric conducting material
C2b second electric conducting material
The single semiconductor chip encapsulating structure
First embodiment
P1a, P2a semiconductor chip package
1a ' base board unit
The central storage tank of 3a ' encapsulation unit 30a '
The peripheral storage tank of 31a '
4a ' first conductive unit the 40a first conductive layer
40a ' first conductive layer
5a ' second conductive unit the 50a second conductive layer
50a ' second conductive layer
6a ' insulation unit 60a insulating barrier
Second embodiment
P1b, P2b semiconductor chip package
1b ' base board unit
21b first insulating barrier
The central storage tank of 3b ' encapsulation unit 30b '
The peripheral storage tank of 31b '
4b ' first conductive unit the 40b first conductive layer
40b ' first conductive layer
5b ' second conductive unit the 50b second conductive layer
50b ' second conductive layer
6b ' second insulation unit 60b second insulating barrier
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of logical semiconductor chip package of front-surface electric conduction and preparation method thereof of reaching.Because semiconductor chip package of the present invention does not need can reach electrical connection through routing technology, so the present invention can omit routing technology and can remove from because of routing has condition of poor electric contact and taking place.
In order to solve the problems of the technologies described above; According to wherein a kind of scheme of the present invention; A kind of logical semiconductor chip package (semiconductor chip package structure) of front-surface electric conduction of reaching is provided, and it comprises: encapsulation unit, at least one semiconductor chip, base board unit, the first insulation unit, first conductive unit, second conductive unit, and the second insulation unit.Wherein, this encapsulation unit has the peripheral storage tank of at least one central storage tank and at least one this at least one central storage tank of encirclement.This at least one semiconductor chip is placed in this at least one central storage tank; And the upper surface of this at least one semiconductor chip has a plurality of conductive welding disks; And this at least one semiconductor chip is a light-emitting diode chip for backlight unit; This encapsulation unit is fluorescent material or transparent material, and said a plurality of conductive welding disk is divided into positive terminal pad and negative terminal pad, and this light-emitting diode chip for backlight unit has the light-emitting area of the end opposite that is arranged at said a plurality of conductive welding disks in addition.This base board unit is placed in this at least one peripheral storage tank.This first insulation unit has at least one and is formed at first insulating barrier between said a plurality of conductive welding disk, so that said a plurality of conductive welding disk is insulated from each other.
This first conductive unit has a plurality of first conductive layers; And one of them first conductive layer forms on this first insulating barrier and is positioned at the top of this at least one semiconductor chip, and an end of remaining first conductive layer is electrically connected on said a plurality of conductive welding disk respectively.This second conductive unit has a plurality of second conductive layers; One of them second conductive layer forms on above-mentioned first conductive layer that is positioned at this at least one semiconductor chip top, and remaining second conductive layer is formed separately on above-mentioned a plurality of first conductive layers that are electrically connected on said a plurality of conductive welding disks respectively.This second insulation unit forming reaches said a plurality of second conductive layer each other each other in said a plurality of first conductive layers, produces electric isolated each other so that said a plurality of first conductive layer reaches said a plurality of second conductive layer each other.
The aforesaid logical semiconductor chip package of front-surface electric conduction of reaching; Wherein, This at least one semiconductor chip is optical sensing chip or image sensing chip; This encapsulation unit is transparent material or light transmissive material, and said conductive welding disk is divided into an electrode pad group and a signal pad group at least.
The aforesaid logical semiconductor chip package of front-surface electric conduction of reaching; Wherein, This at least one semiconductor chip is an IC chip, and this encapsulation unit is a light-proof material, and said conductive welding disk is divided into an electrode pad group and a signal pad group at least.
The aforesaid logical semiconductor chip package of front-surface electric conduction of reaching, wherein, first conductive layer that is electrically connected on said conductive welding disk respectively forms on this encapsulation unit and this base board unit.
The aforesaid logical semiconductor chip package of front-surface electric conduction of reaching, wherein, the part of this second insulation unit is covered on said second conductive layer.
In order to solve the problems of the technologies described above; According to wherein a kind of scheme of the present invention, a kind of manufacture method of reaching the logical semiconductor chip package (semiconductor chip package structure) of front-surface electric conduction is provided, it comprises the following steps: at first; At least two semiconductor chips are provided; Wherein each semiconductor chip has a plurality of conductive welding disks, and each semiconductor chip is a light-emitting diode chip for backlight unit, and this encapsulation unit is fluorescent material or transparent material; And said a plurality of conductive welding disk is divided into positive terminal pad and negative terminal pad, and this light-emitting diode chip for backlight unit has the light-emitting area of the end opposite that is arranged at said a plurality of conductive welding disks in addition; Then, tack macromolecular material (adhesive polymeric material) is pasted on the lower surface of base board unit with at least two perforation; Then, above-mentioned at least two semiconductor chips are placed in above-mentioned at least two perforation and are arranged on this tack macromolecular material, wherein said a plurality of conductive welding disks are towards this tack macromolecular material; And then, encapsulation unit is covered in this base board unit, this tack macromolecular material, reaches on above-mentioned at least two semiconductor chips.
Then, with the counter-rotating of this encapsulation unit and remove this tack macromolecular material, so that said conductive welding disk exposes and up; Next, being shaped has first conductive unit of a plurality of first conductive layers, and wherein two first conductive layers lay respectively at the top of these at least two semiconductor chips, and an end of remaining first conductive layer is electrically connected on said a plurality of conductive welding disk respectively; Then; Shaping has second conductive unit of a plurality of second conductive layers; And wherein two second conductive layers are formed separately at least on above-mentioned two first conductive layers that are positioned at these two semiconductor chips tops, and remaining second conductive layer is formed separately on above-mentioned a plurality of first conductive layers that are electrically connected on said a plurality of conductive welding disks respectively; Then; The insulation unit that shaping has a plurality of insulating barriers reaches said a plurality of second conductive layer each other each other in said a plurality of first conductive layers, produces electric isolated each other so that said a plurality of first conductive layer reaches said a plurality of second conductive layer each other; At last, cut above-mentioned second conductive unit, first conductive unit, base board unit, and encapsulation unit between at least two semiconductor chips in regular turn, to form at least two single semiconductor chip packages.
The aforesaid manufacture method of reaching the logical semiconductor chip package of front-surface electric conduction; Wherein, Each semiconductor chip is optical sensing chip or image sensing chip; This encapsulation unit is transparent material or light transmissive material, and said conductive welding disk is divided into an electrode pad group and a signal pad group at least.
The aforesaid manufacture method of reaching the logical semiconductor chip package of front-surface electric conduction; Wherein, Each semiconductor chip is an IC chip, and this encapsulation unit is a light-proof material, and said conductive welding disk is divided into an electrode pad group and a signal pad group at least.
The aforesaid manufacture method of reaching the logical semiconductor chip package of front-surface electric conduction wherein, in the above-mentioned step that two semiconductor chips are provided, also further comprises: form first insulating material on this semiconductor chip and said conductive welding disk at least; And remove the part first insulating material and form first insulating barrier, to expose said conductive welding disk.Wherein, This first insulating material is formed on this semiconductor chip with the mode of printing, coating or spraying; And through preparatory roasting program with this first insulating material that hardens, then through exposure, development, etching, and the cooperation of bake process to remove first insulating material of above-mentioned part.
The aforesaid manufacture method of reaching the logical semiconductor chip package of front-surface electric conduction; Wherein, In the step of this first conductive unit of above-mentioned shaping and this second conductive unit, also further comprise: form first electric conducting material on above-mentioned at least two semiconductor chips, this encapsulation unit and this base board unit and be electrically connected on said conductive welding disk; Remove first electric conducting material of part, to form said first conductive layer; Form second electric conducting material on said first conductive layer; And second electric conducting material that removes part, to form said second conductive layer.Wherein, this first electric conducting material and this second electric conducting material all form with the mode of vapor deposition, sputter, plating or electroless-plating, then first electric conducting material and second electric conducting material of cooperation to remove above-mentioned part through exposure, development and etching process.
The present invention also provides a kind of logical semiconductor chip package of front-surface electric conduction of reaching, and wherein, comprising: encapsulation unit, and it has at least one central storage tank and at least one surrounds the peripheral storage tank of this at least one central storage tank; At least one semiconductor chip; It is placed in this at least one central storage tank; And the upper surface of this at least one semiconductor chip has a plurality of conductive welding disks, and each semiconductor chip is a light-emitting diode chip for backlight unit, and this encapsulation unit is fluorescent material or transparent material; And said a plurality of conductive welding disk is divided into positive terminal pad and negative terminal pad, and this light-emitting diode chip for backlight unit has the light-emitting area of the end opposite that is arranged at said a plurality of conductive welding disks in addition; Base board unit, it is placed in this at least one peripheral storage tank; First conductive unit, it has a plurality of first conductive layers, and one of them first conductive layer is positioned at the top of this at least one semiconductor chip, and an end of remaining first conductive layer is electrically connected on said a plurality of conductive welding disk respectively; Second conductive unit; It has a plurality of second conductive layers; One of them second conductive layer forms on above-mentioned first conductive layer that is positioned at this at least one semiconductor chip top, and remaining second conductive layer is formed separately on above-mentioned a plurality of first conductive layers that are electrically connected on said a plurality of conductive welding disks respectively; And the insulation unit, it forms in said a plurality of first conductive layer and reaches said a plurality of second conductive layer each other each other, produces electric isolated each other so that said a plurality of first conductive layer reaches said a plurality of second conductive layer each other.
The aforesaid logical semiconductor chip package of front-surface electric conduction of reaching; Wherein, This at least one semiconductor chip is optical sensing chip or image sensing chip; This encapsulation unit is transparent material or light transmissive material, and said conductive welding disk is divided into an electrode pad group and a signal pad group at least.
The aforesaid logical semiconductor chip package of front-surface electric conduction of reaching; Wherein, This at least one semiconductor chip is an IC chip, and this encapsulation unit is a light-proof material, and said conductive welding disk is divided into an electrode pad group and a signal pad group at least.
The aforesaid logical semiconductor chip package of front-surface electric conduction of reaching, wherein, first conductive layer that is electrically connected on said conductive welding disk respectively forms in this encapsulation unit, this base board unit, reaches on this at least one semiconductor chip.
The aforesaid logical semiconductor chip package of front-surface electric conduction of reaching, wherein the part of this second insulation unit is covered on said second conductive layer.
Reach technology, means and the effect that predetermined purpose is taked in order further to understand the present invention; See also following about detailed description of the present invention and accompanying drawing; Believe the object of the invention, characteristic and characteristics; When can being able to thus deeply and concrete understanding, yet appended accompanying drawing only provides reference and explanation usefulness, is not to be used for the present invention is limited.
The present invention can omit routing technology and can remove from because of routing and condition of poor electric contact occurs.
Description of drawings
Fig. 1 is the generalized section of the known package structure for LED made from routing technology (wire-bonding process);
Fig. 2 can reach the flow chart of first embodiment of the manufacture method of the logical semiconductor chip package of front-surface electric conduction for the present invention;
Fig. 2 A to Fig. 2 K is respectively the making flow process generalized section that the present invention can reach first embodiment of the logical semiconductor chip package (semiconductor chip package structure) of front-surface electric conduction;
Fig. 3 can reach the flow chart of second embodiment of the manufacture method of the logical semiconductor chip package of front-surface electric conduction for the present invention;
Fig. 3 A to Fig. 3 K is respectively the making flow process generalized section that the present invention can reach second embodiment of the logical semiconductor chip package (semiconductor chip package structure) of front-surface electric conduction; And
Fig. 4 A to Fig. 4 C is the making flow process generalized section of first insulating barrier of second embodiment of the invention.
Wherein, description of reference numerals is following:
Embodiment
See also Fig. 2, reach shown in Fig. 2 A to Fig. 2 K, first embodiment of the invention provides a kind of manufacture method of reaching the logical semiconductor chip package of front-surface electric conduction, and it comprises the following steps:
Step S100: at first, please cooperate shown in Fig. 2 and Fig. 2 A, tack macromolecular material (adhesive polymeric material) A is pasted on the lower surface of the base board unit 1a with at least two perforation 10a.
Step S102: then; Please cooperate shown in Fig. 2 and Fig. 2 B; At least two semiconductor chip 2a of general are placed in above-mentioned at least two perforation 10a and are arranged on this tack high-molecular material A; Wherein each semiconductor chip 2a has a plurality of conductive welding disk 20a, and said a plurality of conductive welding disk 20a is towards this tack high-molecular material A.With first enforcement, each semiconductor chip 2a can be light-emitting diode chip for backlight unit (LED chip).
Step S104: then, please cooperate shown in Fig. 2 and Fig. 2 C, encapsulation unit 3a is covered in this base board unit 1a, this tack high-molecular material A, reaches on above-mentioned at least two semiconductor chip 2a.Implement with first; This encapsulation unit 3a can be fluorescent material (fluorescent material); And said a plurality of conductive welding disk 20a is divided into positive terminal pad (positive electrode pad) 200a and negative terminal pad (negative electrode pad) 201a, and each semiconductor chip 2a has light-emitting area (light-emitting surface) 202a of the end opposite that is arranged at said a plurality of conductive welding disk 20a in addition.
Step S106: then, please cooperate shown in Fig. 2 and Fig. 2 D, with this encapsulation unit 3a counter-rotating and remove this tack high-molecular material A, so that said a plurality of conductive welding disk 20a exposes and up.
Step S108: next, please cooperate shown in Fig. 2 and Fig. 2 E, form the first electric conducting material C1a and go up and be electrically connected on said a plurality of conductive welding disk 20a in above-mentioned at least two semiconductor chip 2a, this encapsulation unit 3a and this base board unit 1a.In addition, this first electric conducting material C1a forms with the mode of vapor deposition (evaporation), sputter (sputtering), plating (electroplating) or electroless-plating (electroless plating).
Step S110: then; Please cooperate shown in Fig. 2 and Fig. 2 F, remove the first electric conducting material C1a of part, have the first conductive unit 4a of a plurality of first conductive layer 40a with formation; And wherein two first conductive layer 40a lay respectively at the top of these at least two semiconductor chip 2a; Remaining first conductive layer 40a is electrically connected on said a plurality of conductive welding disk 20a respectively, wherein this first conductive unit 4a be the projection underlying metal (under bump metallization, UBM).In addition, the above-mentioned step that removes the first electric conducting material C1a of part is accomplished through the cooperation of exposure (exposure), development (development) and etching (etching) process.
Step S112: then, please cooperate shown in Fig. 2 and Fig. 2 G, form the second electric conducting material C2a on this first conductive unit 4a.In addition, this second electric conducting material C2a can vapor deposition (evaporation), sputter (sputtering), the mode of electroplating (electroplating) or electroless-plating (electroless plating) be formed on this first conductive unit 4a.
Step S114: then; Please cooperate shown in Fig. 2 and Fig. 2 H; Remove the second electric conducting material C2a of part; Have the second conductive unit 5a of a plurality of second conductive layer 50a with formation, and wherein two second conductive layer 50a are formed separately on above-mentioned two first conductive layer 40a that are positioned at these two semiconductor chip 2a tops at least, remaining second conductive layer 50a is formed separately on above-mentioned a plurality of first conductive layer 40a that are electrically connected on said a plurality of conductive welding disk 20a respectively.In addition, the above-mentioned step that removes the second electric conducting material C2a of part is accomplished through the cooperation of exposure (exposure), development (development) and etching (etching) process.
Step S116: next, please cooperate shown in Fig. 2 and Fig. 2 I, shaping insulating material Ba in the said first conductive layer 40a each other, the said second conductive layer 50a each other, and this second conductive unit 5a on.In addition, this insulating material Ba forms with the mode of printing (printing), coating (coating) or spraying (spring), and then passes through in advance roasting (pre-curing) program with sclerosis (hardening) this insulating material Ba.
Step S118: next; Please cooperate shown in Fig. 2 and Fig. 2 J; Remove the insulating material Ba of part has a plurality of insulating barrier 60a with formation insulation unit 6a in the said first conductive layer 40a each other, the said second conductive layer 50a each other, and the part second conductive unit 5a on to produce electricity each other isolated so that the said first conductive layer 40a reaches the said second conductive layer 50a each other.The step of the above-mentioned insulating material Ba that removes part through exposure (exposure), develop (development), etching (etching), and the cooperation of baking (curing) (with (hardening) the said insulating barrier 60a that hardens) process accomplish.
Step S120: next, please cooperate shown in Fig. 2 and Fig. 2 K, the dotted line X-X that is prolonging Fig. 2 J cuts, to form at least two single semiconductor chip packages (P1a, P2a).In other words, cut the above-mentioned second conductive unit 5a, the first conductive unit 4a, base board unit 1a, and encapsulation unit 3a between at least two semiconductor chip 2a in regular turn, to form at least two single semiconductor chip packages (P1a, P2a).
Wherein, each semiconductor chip package (P1a, P2a) comprising: encapsulation unit (packageunit) 3a ', semiconductor chip (semiconductor chip) 2a, base board unit (substrate unit) 1a ', first conductive unit (first conductive unit) 4a ', second conductive unit (secondconductive unit) 5a ', and insulation unit (conductive unit) 6a '.
In addition, this encapsulation unit 3a ' has peripheral storage tank (the outer receiving groove) 31a ' of at least one central storage tank (center receivinggroove) 30a ' and at least one this at least one central storage tank 30a ' of encirclement.This semiconductor chip 2a is placed in 30a ' in this at least one central storage tank, and the upper surface of this semiconductor chip 2a has a plurality of conductive welding disks (conductivepad) 20a.This base board unit 1a ' is placed in this at least one peripheral storage tank 31a '.
Moreover; This first conductive unit 4a ' has a plurality of first conductive layers (first conductive layer) (40a, 40a ') that form on semiconductor chip 2a, this encapsulation unit 3a ' and this base board unit 1a '; And one of them first conductive layer 40a is positioned at the top of this semiconductor chip 2a, and an end of remaining first conductive layer (40a, 40a ') is electrically connected on said a plurality of conductive welding disk 20a respectively.This second conductive unit 5a has a plurality of second conductive layers (second conductive layer) (50a, 50a '); One of them second conductive layer 50a forms on the above-mentioned first conductive layer 40a that is positioned at this semiconductor chip 2a top, and remaining second conductive layer (50a, 50a ') is formed separately on above-mentioned a plurality of first conductive layers (40a, 40a ') that are electrically connected on said a plurality of conductive welding disk 20a respectively.
In addition; This insulation unit 6a ' has a plurality of insulating barrier 60a; Said insulating barrier 60a forms in said first conductive layer (40a, 40a ') and reaches said second conductive layer (50a, 50a ') each other each other, produces electric isolated each other so that said first conductive layer (40a, 40a ') reaches said second conductive layer (50a, 50a ') each other.In addition, the part of each insulating barrier 60a is covered on said second conductive layer (50a, 50a ').
See also Fig. 3, reach shown in Fig. 3 A to Fig. 3 K, second embodiment of the invention provides a kind of manufacture method of reaching the logical semiconductor chip package of front-surface electric conduction, and it comprises the following steps:
Step S200: at first, please cooperate shown in Fig. 3 and Fig. 3 A, tack macromolecular material (adhesive polymeric material) A is pasted on the lower surface of the base board unit 1b with at least two perforation 10b.
Step S202: then; Please cooperate shown in Fig. 3 and Fig. 3 B; At least two semiconductor chip 2b of general are placed in above-mentioned at least two perforation 10b and are arranged on this tack high-molecular material A; Wherein each semiconductor chip 2b has a plurality of conductive welding disk 20b, and at least one first insulating barrier 21b forms between said a plurality of conductive welding disk 20b, and said in addition a plurality of conductive welding disk 20b are towards this tack high-molecular material A.With first enforcement, each semiconductor chip 2b can be light-emitting diode chip for backlight unit (LED chip).
In addition, the manufacture method of this at least one first insulating barrier 21b comprises the following steps (please cooperate shown in Fig. 4 A to Fig. 4 C): at first, a semiconductor chip 2b with a plurality of conductive welding disk 20b is provided; Then, form the first insulating material B1b on this semiconductor chip 2b and said a plurality of conductive welding disk 20b; Then, remove the part the first insulating material B1b and form the first insulating barrier 21b (the first insulation unit), it is formed between said a plurality of conductive welding disk 20, and surrounds said a plurality of conductive welding disk 20 with the mode of exposing said a plurality of conductive welding disk 20b.Wherein, This first insulating material B1b is formed on this semiconductor chip 2b with the mode of printing (printing), coating (coating) or spraying (spring); And through preparatory roasting (pre-curing) program with sclerosis (hardening) this first insulating material B1b, and then through exposure (exposure), develop (development), etching (etching), and the cooperation of (curing) process of baking to remove the first insulating material B1b of above-mentioned part.
Step S204: then, please cooperate shown in Fig. 3 and Fig. 3 C, encapsulation unit 3b is covered in this base board unit 1b, this tack high-molecular material A, reaches on above-mentioned at least two semiconductor chip 2b.Implement with second; This encapsulation unit 3b can be fluorescent material (fluorescent material); And said a plurality of conductive welding disk 20b is divided into positive terminal pad (positive electrode pad) 200b and negative terminal pad (negative electrode pad) 201b, and each semiconductor chip 2b has light-emitting area (light-emitting surface) 202b of the end opposite that is arranged at said a plurality of conductive welding disk 20b in addition.
Step S206: then, please cooperate shown in Fig. 3 and Fig. 3 D, with this encapsulation unit 3b counter-rotating and remove this tack high-molecular material A, so that said a plurality of conductive welding disk 20b exposes and up.
Step S208: next; Please cooperate shown in Fig. 3 and Fig. 3 E, form the first electric conducting material C1b and go up and be electrically connected on said a plurality of conductive welding disk 20b in above-mentioned at least two semiconductor chip 2b, this first insulating barrier 21b, this encapsulation unit 3b and this base board unit 1b.In addition, this first electric conducting material C1b forms with the mode of vapor deposition (evaporation), sputter (sputtering), plating (electroplating) or electroless-plating (electroless plating).
Step S210: then; Please cooperate shown in Fig. 3 and Fig. 3 F; Remove the first electric conducting material C1b of part; Have the first conductive unit 4b of a plurality of first conductive layer 40b with formation, and wherein two first conductive layer 40b lay respectively at the top of this at least two semiconductor chip 2b, remaining first conductive layer 40b is electrically connected on said a plurality of conductive welding disk 20b respectively.Wherein this first conductive unit 4b be the projection underlying metal (under bump metallization, UBM).In addition, the above-mentioned step that removes the first electric conducting material C1b of part is accomplished through the cooperation of exposure (exposure), development (development) and etching (etching) process.
Step S212: then, please cooperate shown in Fig. 3 and Fig. 3 G, form the second electric conducting material C2b on this first conductive unit 4b.In addition, this second electric conducting material C2b forms with the mode of vapor deposition (evaporation), sputter (sputtering), plating (electroplating) or electroless-plating (electroless plating).
Step S214: then; Please cooperate shown in Fig. 3 and Fig. 3 H; Remove the second electric conducting material C2b of part; The second conductive unit 5b that has a plurality of second conductive layer 50b with formation; And wherein two second conductive layer 50b are formed separately at least on above-mentioned two first conductive layer 40b that are positioned at these two semiconductor chip 2b tops, and remaining second conductive layer 50b is formed separately on above-mentioned a plurality of first conductive layer 40b that are electrically connected on said a plurality of conductive welding disk 20b respectively, and the wherein above-mentioned step that removes the second electric conducting material C2b of part is accomplished through the cooperation of exposure (exposure), development (development) and etching (etching) process.
Step S216: next, please cooperate shown in Fig. 3 and Fig. 3 I, be shaped the second insulating material B2b in the said first conductive layer 40b each other, the said second conductive layer 50b each other, and this second the conduction singly show on the 5b.In addition, this second insulating material B2b forms with the mode of printing (printing), coating (coating) or spraying (spring).
Step S218: next; Please cooperate shown in Fig. 3 and Fig. 3 J; Remove the second insulating material B2b of part has a plurality of second insulating barrier 60b with shaping the second insulation unit 6b in the said first conductive layer 40b each other, the said second conductive layer 50b each other, and this second conductive unit 5b on to produce electricity each other isolated so that the said first conductive layer 40b reaches the said second conductive layer 50b each other.The step of the above-mentioned second insulating material B2b that removes part through exposure (exposure), develop (development), etching (etching), and the cooperation of baking (curing) (with (hardening) the said second insulating barrier 60b that hardens) process accomplish.
Step S220: next, please cooperate shown in Fig. 3 and Fig. 3 K, the dotted line Y-Y that is prolonging Fig. 3 J cuts, to form at least two single semiconductor chip packages (P1b, P2b).In other words, cut the above-mentioned second conductive unit 5b, the first conductive unit 4b, base board unit 1b, and encapsulation unit 3b between at least two semiconductor chip 2b in regular turn, to form at least two single semiconductor chip packages (P1b, P2b).
Wherein, each semiconductor chip package (P1b, P2b) comprising: encapsulation unit (packageunit) 3b ', semiconductor chip (semiconductor chip) 2b, base board unit (substrate unit) 1b ', the first insulation unit (first insulative unit), first conductive unit (first conductive unit) 4b ', second conductive unit (second conductive unit) 5b ', and the second insulation unit (conductive unit) 6b '.
In addition, this encapsulation unit 3b ' has peripheral storage tank (the outer receiving groove) 31b ' of at least one central storage tank (center receivinggroove) 30b ' and at least one this at least one central storage tank 30b ' of encirclement.This semiconductor chip 2b is placed in 30b ' in this at least one central storage tank, and the upper surface of this semiconductor chip 2b has a plurality of conductive welding disks (conductivepad) 20b.This base board unit 1b ' is placed in this at least one peripheral storage tank 31b '.This first insulation unit has at least one and is formed at first insulating barrier (firstinsulative layer) 21b between said a plurality of conductive welding disk 20b, so that said a plurality of conductive welding disk 20b is insulated from each other.
Moreover; This first conductive unit 4b ' has a plurality of first conductive layers (40b, 40b '); And one of them first conductive layer 40b forms in the top that this first insulating barrier 21b went up and be positioned at this at least one semiconductor chip 2b, and an end of remaining first conductive layer (40b, 40b ') is electrically connected on said a plurality of conductive welding disk 20b respectively.This second conductive unit 5b ' has a plurality of second conductive layers (secondconductive layer) (50b, 50b '); One of them second conductive layer 50b forms on the above-mentioned first conductive layer 40b that is positioned at this semiconductor chip 2b top, and remaining second conductive layer (50b, 50b ') is formed separately on above-mentioned a plurality of first conductive layers (40b, 40b ') that are electrically connected on said a plurality of conductive welding disk 20b respectively.
In addition; This second insulation unit 6b ' has a plurality of second insulating barrier 60b; The said second insulating barrier 60b forms in said first conductive layer (40b, 40b ') and reaches said second conductive layer (50b, 50b ') each other each other, produces electric isolated each other so that said first conductive layer (40b, 40b ') reaches said second conductive layer (50b, 50b ') each other.In addition, the part of each second insulating barrier 60b is covered on said second conductive layer (50b, 50b ').
In addition, be example with first embodiment, this semiconductor chip 2a comprises following different selection with this encapsulation unit 3a:
1, this semiconductor chip 2a can be light-emitting diode chip for backlight unit (LED chip); And this encapsulation unit 3a can be fluorescent material (fluorescent material), and said a plurality of conductive welding disk 20a is divided into positive terminal pad (positive electrode pad) 200a and negative terminal pad (negativeelectrode pad) 201a.For example:, then, can produce white light beam through the cooperating of this blue led chips and this fluorescent material if this light-emitting diode chip for backlight unit is a blue led chips (blue LED chip).
2, this semiconductor chip 2a can be LED chip (LED chip set); And this encapsulation unit 3a can be transparent material (transparent material), and said a plurality of conductive welding disk 20a is divided into positive terminal pad (positive electrode pad) 200a and negative terminal pad (negative electrode pad) 201a.For example: if this LED chip is for producing the LED chip (LED chip of for example being made up of three kinds of light-emitting diodes of red, green, blue) of white light; Then enough produce the LED chip of white light and cooperating of this transparent material, also can produce white light beam through this.
3, this semiconductor chip 2a can be optical sensing chip (light sensing chip) or image sensing chip (image sensing chip); And this encapsulation unit 3a can be transparent material (transparent material) or light transmissive material (translucent material), and said a plurality of conductive welding disk 20a is divided into an electrode pad group (electrode pad set) and a signal pad group (signal pad set) at least.
4, this semiconductor chip 2a can be IC chip (IC chip); And this encapsulation unit 3a can be light-proof material (opaque material), and said a plurality of conductive welding disk 20a is divided into an electrode pad group (electrode pad set) and a signal pad group (signal pad set) at least.
In sum, because semiconductor chip package of the present invention does not need can reach electrical connection through routing technology, so the present invention can omit routing technology and can remove from because of routing has condition of poor electric contact and taking place.
The above be merely the detailed description and the accompanying drawing of the preferred specific embodiment of the present invention, but characteristic of the present invention is not limited thereto; It is not in order to restriction the present invention; All scopes of the present invention should be as the criterion with following claims, and all embodiment that meets the spirit variation similar with it of claims of the present invention all should be contained in the scope of the present invention; Those skilled in the art in the field of the invention, can think easily and variation or modify all can be encompassed in the following scope of the present invention.
Claims (9)
1. can reach the logical semiconductor chip package of front-surface electric conduction for one kind, it is characterized in that, comprise:
Encapsulation unit, it has at least one central storage tank and at least one surrounds the peripheral storage tank of this at least one central storage tank;
At least one semiconductor chip; It is placed in this at least one central storage tank; And the upper surface of this at least one semiconductor chip has a plurality of conductive welding disks, and this at least one semiconductor chip is light-emitting diode chip for backlight unit, and this encapsulation unit is fluorescent material or transparent material; And said a plurality of conductive welding disk is divided into positive terminal pad and negative terminal pad, and this light-emitting diode chip for backlight unit has the light-emitting area of the end opposite that is arranged at said a plurality of conductive welding disks in addition;
Base board unit, it is placed in this at least one peripheral storage tank;
The first insulation unit, it has at least one and is formed at first insulating barrier between said a plurality of conductive welding disk, so that said a plurality of conductive welding disk is insulated from each other;
First conductive unit; It has a plurality of first conductive layers; And one of them first conductive layer forms on this first insulating barrier and is positioned at the top of this at least one semiconductor chip, and the end system of remaining first conductive layer is electrically connected on said a plurality of conductive welding disk respectively;
Second conductive unit; It has a plurality of second conductive layers; One of them second conductive layer forms on above-mentioned first conductive layer that is positioned at this at least one semiconductor chip top, and remaining second conductive layer is formed separately on above-mentioned a plurality of first conductive layers that are electrically connected on said a plurality of conductive welding disks respectively; And
The second insulation unit, it forms in said a plurality of first conductive layer and reaches said a plurality of second conductive layer each other each other, produces electric isolated each other so that said a plurality of first conductive layer reaches said a plurality of second conductive layer each other.
2. the logical semiconductor chip package of front-surface electric conduction of reaching as claimed in claim 1, it is characterized in that: above-mentioned a plurality of first conductive layers that are electrically connected on said a plurality of conductive welding disks respectively form on this encapsulation unit and this base board unit.
3. the logical semiconductor chip package of front-surface electric conduction of reaching as claimed in claim 1, it is characterized in that: the part of this second insulation unit is covered on said a plurality of second conductive layer.
4. the manufacture method that can reach the logical semiconductor chip package of front-surface electric conduction is characterized in that, comprises the following steps:
At least two semiconductor chips are provided; Wherein each semiconductor chip has a plurality of conductive welding disks; Each semiconductor chip is a light-emitting diode chip for backlight unit; This encapsulation unit is fluorescent material or transparent material, and said a plurality of conductive welding disk is divided into positive terminal pad and negative terminal pad, and this light-emitting diode chip for backlight unit has the light-emitting area of the end opposite that is arranged at said a plurality of conductive welding disks in addition;
The tack macromolecular material is pasted on the lower surface of base board unit with at least two perforation;
Above-mentioned at least two semiconductor chips are placed in above-mentioned at least two perforation and are arranged on this tack macromolecular material, and wherein said a plurality of conductive welding disks are towards this tack macromolecular material;
Encapsulation unit is covered in this base board unit, this tack macromolecular material, reaches on above-mentioned at least two semiconductor chips;
With the counter-rotating of this encapsulation unit and remove this tack macromolecular material, so that said a plurality of conductive welding disk exposes and up;
Shaping has first conductive unit of a plurality of first conductive layers, and wherein two first conductive layers lay respectively at the top of these at least two semiconductor chips, and an end of remaining first conductive layer is electrically connected on said a plurality of conductive welding disk respectively;
Shaping has second conductive unit of a plurality of second conductive layers; And wherein two second conductive layers are formed separately at least on above-mentioned two first conductive layers that are positioned at these two semiconductor chips tops, and remaining second conductive layer is formed separately on above-mentioned first conductive layer that is electrically connected on said a plurality of conductive welding disks respectively;
The insulation unit that shaping has a plurality of insulating barriers reaches said a plurality of second conductive layer each other each other in said a plurality of first conductive layers, produces electric isolated each other so that said a plurality of first conductive layer reaches said a plurality of second conductive layer each other; And
Cut above-mentioned second conductive unit, first conductive unit, base board unit, and encapsulation unit between at least two semiconductor chips in regular turn, to form at least two single semiconductor chip packages.
5. the manufacture method of reaching the logical semiconductor chip package of front-surface electric conduction as claimed in claim 4 is characterized in that: in the above-mentioned step that at least two semiconductor chips are provided, also further comprise:
Form first insulating material on this semiconductor chip and said a plurality of conductive welding disk; And
Remove first insulating material of part and form first insulating barrier, to expose said a plurality of conductive welding disk;
Wherein, This first insulating material is formed on this semiconductor chip with the mode of printing, coating or spraying; And through preparatory roasting program with this first insulating material that hardens, then through exposure, development, etching, and the cooperation of bake process to remove first insulating material of above-mentioned part.
6. the manufacture method of reaching the logical semiconductor chip package of front-surface electric conduction as claimed in claim 4 is characterized in that: in the step of this first conductive unit of above-mentioned shaping and this second conductive unit, also further comprise:
Form first electric conducting material on above-mentioned at least two semiconductor chips, this encapsulation unit and this base board unit and be electrically connected on said a plurality of conductive welding disk;
Remove first electric conducting material of part, to form said a plurality of first conductive layer;
Form second electric conducting material on said a plurality of first conductive layers; And
Remove second electric conducting material of part, to form said a plurality of second conductive layer;
Wherein, this first electric conducting material and this second electric conducting material all form with the mode of vapor deposition, sputter, plating or electroless-plating, then first electric conducting material and second electric conducting material of cooperation to remove above-mentioned part through exposure, development and etching process.
7. can reach the logical semiconductor chip package of front-surface electric conduction for one kind, it is characterized in that, comprise:
Encapsulation unit, it has at least one central storage tank and at least one surrounds the peripheral storage tank of this at least one central storage tank;
At least one semiconductor chip; It is placed in this at least one central storage tank; And the upper surface of this at least one semiconductor chip has a plurality of conductive welding disks, and wherein this at least one half conductor chip is a light-emitting diode chip for backlight unit, and this encapsulation unit is fluorescent material or transparent material; And said a plurality of conductive welding disk is divided into positive terminal pad and negative terminal pad, and this light-emitting diode chip for backlight unit has the light-emitting area of the end opposite that is arranged at said a plurality of conductive welding disks in addition;
Base board unit, it is placed in this at least one peripheral storage tank;
First conductive unit, it has a plurality of first conductive layers, and one of them first conductive layer is positioned at the top of this at least one semiconductor chip, and an end of remaining first conductive layer is electrically connected on said a plurality of conductive welding disk respectively;
Second conductive unit; It has a plurality of second conductive layers; One of them second conductive layer forms on above-mentioned first conductive layer that is positioned at this at least one semiconductor chip top, and remaining second conductive layer is formed separately on above-mentioned a plurality of first conductive layers that are electrically connected on said a plurality of conductive welding disks respectively; And
The insulation unit, it forms in said a plurality of first conductive layer and reaches said a plurality of second conductive layer each other each other, produces electric isolated each other so that said a plurality of first conductive layer reaches said a plurality of second conductive layer each other.
8. the logical semiconductor chip package of front-surface electric conduction of reaching as claimed in claim 7, it is characterized in that: above-mentioned first conductive layer that is electrically connected on said a plurality of conductive welding disks respectively forms in this encapsulation unit, this base board unit, reaches on this at least one semiconductor chip.
9. the logical semiconductor chip package of front-surface electric conduction of reaching as claimed in claim 7, it is characterized in that: the part of this second insulation unit is covered on said a plurality of second conductive layer.
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| CN2613046Y (en) * | 2003-04-17 | 2004-04-21 | 威盛电子股份有限公司 | Chip packaging structure |
| CN101202253A (en) * | 2006-12-13 | 2008-06-18 | 育霈科技股份有限公司 | Wafer level package with good coefficient of thermal expansion efficiency performance and method of the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2613046Y (en) * | 2003-04-17 | 2004-04-21 | 威盛电子股份有限公司 | Chip packaging structure |
| CN101202253A (en) * | 2006-12-13 | 2008-06-18 | 育霈科技股份有限公司 | Wafer level package with good coefficient of thermal expansion efficiency performance and method of the same |
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