CN201238049Y - Semiconductor chip packaging structure capable of achieving electrical connection without wire bonding - Google Patents
Semiconductor chip packaging structure capable of achieving electrical connection without wire bonding Download PDFInfo
- Publication number
- CN201238049Y CN201238049Y CN 200820130552 CN200820130552U CN201238049Y CN 201238049 Y CN201238049 Y CN 201238049Y CN 200820130552 CN200820130552 CN 200820130552 CN 200820130552 U CN200820130552 U CN 200820130552U CN 201238049 Y CN201238049 Y CN 201238049Y
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- Prior art keywords
- semiconductor chip
- conductive
- unit
- routing
- conductive layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004806 packaging method and process Methods 0.000 title abstract 3
- 238000003466 welding Methods 0.000 claims description 44
- 230000004888 barrier function Effects 0.000 claims description 32
- 238000005538 encapsulation Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 18
- 238000009413 insulation Methods 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 7
- 239000012780 transparent material Substances 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 description 12
- 239000004020 conductor Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 208000034189 Sclerosis Diseases 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Led Device Packages (AREA)
Abstract
A semiconductor chip package structure capable of achieving electrical connection without wire bonding, comprising: the semiconductor device comprises a packaging unit, at least one semiconductor chip, at least one first insulating layer, a plurality of first conducting layers, at least one second insulating layer and a plurality of second conducting layers. The packaging unit is provided with at least one accommodating groove. The semiconductor chip is accommodated in the accommodating groove, and the upper surface of the semiconductor chip is provided with a plurality of conductive bonding pads. The first insulating layer is formed between the plurality of conductive pads so as to insulate the plurality of conductive pads from each other. The plurality of first conductive layers are formed on the first insulating layer, and one end of each first conductive layer is electrically connected to the corresponding conductive pad. The second insulating layer is formed between the first conductive layers to insulate the first conductive layers from each other. The plurality of second conductive layers are formed on the other opposite ends of the plurality of first conductive layers, respectively. The utility model discloses can omit the routing and avoid taking place electrical contact failure because of the routing.
Description
Technical field
The utility model relates to a kind of semiconductor chip package, relates in particular to a kind of semiconductor chip package that does not need can reach by routing electric connection.
Background technology
See also shown in Figure 1, the generalized section of the package structure for LED that it is made in the routing mode for prior art.By among the figure as can be known, the package structure for LED of prior art comprises: underlying structure 1a, a plurality of light-emitting diode 2a that is arranged at this underlying structure 1a upper end, many lead 3a, and a plurality of fluorescent colloid 4a.
Wherein, each light-emitting diode 2a is with its light output surface 20a this underlying structure 1a and being arranged on this underlying structure 1a dorsad, and the positive electrode zone 21a of each light-emitting diode 2a upper end and negative electrode area 22a are electrically connected at corresponding positive electrode zone 11a and the negative electrode area 12a of this underlying structure 1a via two lead 3a.Moreover each fluorescent colloid 4a is covered in this corresponding light-emitting diode 2a and two lead 3a upper ends, with this corresponding light-emitting diode 2a of protection.
Yet the routing mode of prior art also must be worried to take place because of routing has the situation of poor electrical contact except increasing fabrication schedule and cost sometimes.Moreover, because the end of these two lead 3a all is arranged at the positive electrode zone 21a and the negative electrode area 22a of this light-emitting diode 2a upper end, therefore when this light-emitting diode 2a carries out ray cast via this light output surface 20a, these two lead 3a will cause cast shadow, and reduce the luminescent quality of this light-emitting diode 2a.
Summary of the invention
Technical problem to be solved in the utility model is to provide a kind of semiconductor chip package that does not need can reach by routing electric connection.Because semiconductor chip package of the present utility model does not need can reach electric connection by routing, so the utility model can omit routing and can remove the situation generation that poor electrical contact is arranged because of routing from.
In order to solve the problems of the technologies described above, according to wherein a kind of scheme of the present utility model, a kind of semiconductor chip package that does not need can reach by routing electric connection is provided, and it comprises: encapsulation unit, semiconductor chip, the first insulation unit, first conductive unit, the second insulation unit, and second conductive unit.This encapsulation unit has at least one storage tank.This at least one semiconductor chip is placed in this at least one storage tank, and the upper surface of this at least one semiconductor chip has a plurality of conductive welding disks.This first insulation unit has at least one and is formed at first insulating barrier between above-mentioned a plurality of conductive welding disk, so that above-mentioned a plurality of conductive welding disk is insulated from each other.This first conductive unit has a plurality of first conductive layers that are formed on this at least one first insulating barrier, and an end of each first conductive layer is electrically connected at corresponding conductive welding disk.This second insulation unit has at least one and is formed at second insulating barrier between above-mentioned a plurality of first conductive layer, so that above-mentioned a plurality of first conductive layer is insulated from each other.This second conductive unit has second conductive layer on a plurality of another end opposite that are formed at above-mentioned a plurality of first conductive layers.
Above-mentioned the need can be reached in the semiconductor chip package of electric connection by routing, this at least one semiconductor chip can be light-emitting diode chip for backlight unit, this encapsulation unit can be fluorescent material or transparent material, and described a plurality of conductive welding disk is divided into positive terminal pad and negative terminal pad, and this light-emitting diode chip for backlight unit has the light-emitting area of the end opposite that is arranged at described a plurality of conductive welding disks in addition.
Above-mentioned the need can be reached in the semiconductor chip package of electric connection by routing, this at least one semiconductor chip can be optical sensing chip, this encapsulation unit can be transparent material or light transmissive material, and described a plurality of conductive welding disk is divided into electrode pad group and signal pad group at least.
Above-mentioned the need can be reached in the semiconductor chip package of electric connection by routing, this at least one semiconductor chip can be integrated circuit (IC) chip, this encapsulation unit is a light-proof material, and described a plurality of conductive welding disk is divided into electrode pad group and signal pad group at least.
Therefore, by above-mentioned semiconductor chip package of the present utility model and preparation method thereof as can be known, because semiconductor chip package of the present utility model does not need can reach electric connection by routing, so the utility model can omit routing and can remove the situation generation that poor electrical contact is arranged because of routing from.
In order further to understand the utility model is to reach technology, means and the effect that predetermined purpose is taked, see also following about detailed description of the present utility model and accompanying drawing, believe the purpose of this utility model, feature and characteristics, when obtaining thus deeply and concrete understanding, yet accompanying drawing is only for reference and explanation, is not to be used for the utility model is limited.
Description of drawings
The generalized section of the package structure for LED that Fig. 1 makes in the routing mode for prior art;
Fig. 2 A to Fig. 2 K is respectively the section schematic flow sheet of first embodiment that the utility model does not need can reach by routing the semiconductor chip package of electric connection; And
Fig. 3 A to Fig. 3 D is respectively the cut-away section schematic flow sheet of second embodiment that the utility model does not need can reach by routing the semiconductor chip package of electric connection.
Wherein, description of reference numerals is as follows:
[prior art]
1a underlying structure 11a positive electrode zone
The 12a negative electrode area
2a light-emitting diode 20a light-emitting area
21a positive electrode zone
The 22a negative electrode area
The 3a lead
The 4a fluorescent colloid
[the utility model]
1 semiconductor chip, 10 conductive welding disks
100 positive terminal pad
101 negative terminal pad
102 light-emitting areas
2 encapsulation units
3 first insulating barriers
4 first conductive layers, 41 first's conductive layers
42 second portion conductive layers
5 second insulating barriers
6 second conductive layers
A tack macromolecular material
B1 first insulating barrier
B1 first insulating material
C1 first electric conducting material
B2 second insulating material
The X dotted line
＜single semiconductor chip encapsulating structure 〉
P1, P2 semiconductor chip package
1 light-emitting diode chip for backlight unit
10 conductive welding disks
2 ' encapsulation unit
20 ' storage tank
3 ' the first insulating barriers
4,4 ' the first conductive layers
5 second insulating barriers
6,6 ' the second conductive layers
Embodiment
See also shown in Fig. 2 A to Fig. 2 K, the utility model first embodiment provides a kind of manufacture method that does not need can reach by routing the semiconductor chip package of electric connection, and it comprises the following steps:
Step S100: at first, please cooperate shown in Fig. 2 A, at least two semiconductor chips 1 are arranged on tack macromolecular material (the adhesive polymeric material) A, wherein each semiconductor chip 1 has a plurality of conductive welding disks 10, and above-mentioned a plurality of conductive welding disk 10 is towards this tack high-molecular material A.With first enforcement, each semiconductor chip 1 can be light-emitting diode chip for backlight unit.
Step S102: then, please cooperate shown in Fig. 2 B, encapsulation unit 2 is covered on above-mentioned two semiconductor chips 1 at least.Implement with first, this encapsulation unit 2 can be fluorescent material, and above-mentioned a plurality of conductive welding disk 10 is divided into positive terminal pad 100 and negative terminal pad 101, and each semiconductor chip 1 has the light-emitting area 102 of the end opposite that is arranged at above-mentioned a plurality of conductive welding disk 10 in addition.
Step S104: then, please cooperate shown in Fig. 2 C, with 2 counter-rotatings of this encapsulation unit and remove this tack high-molecular material A, so that above-mentioned a plurality of conductive welding disk 10 exposes and up.
Step S106: next, please cooperate shown in Fig. 2 D, form the first insulating material B1 on this encapsulation unit 2, to cover these at least two semiconductor chips 1 and above-mentioned a plurality of conductive welding disk 10.In addition, this first insulating material B1 is formed on this encapsulation unit 2 in the mode of printing (printing), coating (coating) or spraying (spring), and through overbaking (curing) program with sclerosis (hardening) this first insulating material B1.
Step S108: and then, please cooperate shown in Fig. 2 E, remove the first insulating material B1 of part, to form first insulating barrier 3 that at least one is used to expose above-mentioned a plurality of conductive welding disk 10.In other words, by exposing (exposure), develop (development), reach the cooperation of etching (etching) process, remove the first insulating material B1 of above-mentioned part, and, make that above-mentioned a plurality of conductive welding disk 10 is insulated from each other by forming above-mentioned at least one first insulating barrier 3 between above-mentioned a plurality of conductive welding disks 10.
Step S110: then, please cooperate shown in Fig. 2 F, form the first electric conducting material C1 in this at least one first insulating barrier 3 and the above-mentioned a plurality of conductive welding disk 10.In addition, this first electric conducting material C1 is formed on this at least one first insulating barrier 3 and the above-mentioned a plurality of conductive welding disk 10 in the mode of evaporation (evaporation), sputter (sputtering), plating (electroplating) or electroless-plating (electroless plating).
Step S112: then, please cooperate shown in Fig. 2 G, remove the first electric conducting material C1 of part, to form a plurality of first conductive layers 4 that are electrically connected at above-mentioned a plurality of conductive welding disk 10 respectively.In other words, the cooperation by exposure, development and etching process to be removing the first electric conducting material C1 of above-mentioned part, and above-mentioned a plurality of first conductive layer 4 is formed on this at least one first insulating barrier 3 and is electrically connected at above-mentioned a plurality of conductive welding disk 10.
Step S114: next, please cooperate shown in Fig. 2 H, form the second insulating material B2 on above-mentioned a plurality of first conductive layers 4 and this at least one first insulating barrier 3.In addition, this second insulating material B2 with the printing, the coating or the spraying mode be formed on above-mentioned a plurality of first conductive layer 4 and this at least one first insulating barrier 3, and through the overbaking program with this second insulating material B2 that hardens.Moreover, above-mentioned a plurality of first conductive layer 4 is divided into a plurality of firsts conductive layer 41 and a plurality of second portion conductive layer 42, and an end of each first's conductive layer 41 is electrically connected at corresponding conductive welding disk 10, and the two ends of each second portion conductive layer 42 are electrically connected at corresponding conductive welding disk 10 respectively.
Step S116: and then, please cooperate shown in Fig. 2 I, remove the part the second insulating material B2 and form a plurality of second insulating barriers 5, expose the part of above-mentioned a plurality of first conductive layers 4.In other words, by exposing, develop, reach the cooperation of etching process, remove the second insulating material B2 of above-mentioned part, and above-mentioned a plurality of second insulating barrier 5 is formed between above-mentioned a plurality of first conductive layer 4.Moreover above-mentioned a plurality of second insulating barriers 5 are formed at respectively between above-mentioned a plurality of firsts conductive layer 41 and the above-mentioned a plurality of second portion conductive layer 42.
Step S118: then, please cooperate shown in Fig. 2 J, form a plurality of second conductive layers 6 respectively on above-mentioned a plurality of first conductive layers 4, to be electrically connected at above-mentioned a plurality of conductive welding disk 10, wherein above-mentioned a plurality of second insulating barriers 5 are formed between above-mentioned a plurality of second conductive layer 6.In addition, above-mentioned a plurality of second conductive layer 6 is formed on above-mentioned a plurality of first conductive layer 4 by the mode of evaporation, sputter, plating or electroless-plating.Moreover, second conductive layer 6 (second conductive layer 6 of outer rim) of a part is formed at another end opposite of above-mentioned a plurality of firsts conductive layer 41, and second conductive layer 6 of remainder (second conductive layer 6 at center) is formed at the middle place of each second portion conductive layer 42.
Step S120: next, please cooperate shown in Fig. 2 K, the dotted line X that is prolonging Fig. 2 J cuts, to form at least two single semiconductor chip packages (P1, P2).
Wherein, each semiconductor chip package P1, P2 comprise: semiconductor chip 1, encapsulation unit 2, the first insulation unit, first conductive unit, the second insulation unit, and second conductive unit.
Moreover, at least one storage tank 20 of this encapsulation unit 2 ' have '.This semiconductor chip 1 be placed in this at least one storage tank 20 ' in, and the upper surface of this semiconductor chip 1 has a plurality of conductive welding disks 10.This first insulation unit have at least one be formed at first insulating barrier 3 between above-mentioned a plurality of conductive welding disk 10 ', so that above-mentioned a plurality of conductive welding disk 10 is insulated from each other.This first conductive unit have a plurality of be formed at this at least one first insulating barrier 3 ' on first conductive layer 4,4 ', and each first conductive layer 4,4 ' an end be electrically connected at corresponding conductive welding disk 10.This second insulation unit have at least one be formed at above-mentioned a plurality of first conductive layer 4,4 ' between second insulating barrier 5 so that above-mentioned a plurality of first conductive layer 4,4 ' insulated from each other.This second conductive unit have a plurality of be formed at above-mentioned a plurality of first conductive layer 4,4 ' another end opposite on second conductive layer 6,6 '.
See also shown in Fig. 3 A to Fig. 2 C, the utility model second embodiment provides a kind of manufacture method that does not need can reach by routing the semiconductor chip package of electric connection, and it comprises the following steps:
At first, cooperate Fig. 3 A, form at least one first insulating barrier B1 (not before the pressurized) on the equal A of tack macromolecular material.
Then, cooperate Fig. 3 B, at least two semiconductor chips 1 are arranged on this at least one first insulating barrier B1 (behind the pressurized), and wherein each semiconductor chip 1 has a plurality of conductive welding disks 10, and above-mentioned a plurality of conductive welding disk 10 towards this at least one first insulating barrier B1.
Then, cooperate Fig. 3 C, encapsulation unit 2 is covered on above-mentioned two semiconductor chips 1 at least.
Next, cooperate Fig. 3 D, with these encapsulation unit 2 counter-rotatings and remove this tack high-molecular material A, so that this at least one insulating barrier B1 exposes and up.
Moreover subsequent step is identical with the S108 to S120 of first embodiment, to finish the making of single semiconductor chip encapsulating structure.
In addition, this semiconductor chip 1 comprises following different selection with this encapsulation unit 2:
One, as described in above-mentioned first embodiment and second embodiment, this semiconductor chip 1 can be light-emitting diode chip for backlight unit, and this encapsulation unit 2 can be fluorescent material, and above-mentioned a plurality of conductive welding disk 10 is divided into positive terminal pad 100 and negative terminal pad 101.For example:, then, can produce white light beam by the cooperating of this blue led chips and this fluorescent material if this light-emitting diode chip for backlight unit is a blue led chips.
Two, this semiconductor chip 1 can be light-emitting diode chip for backlight unit, and this encapsulation unit 2 can be transparent material, and above-mentioned a plurality of conductive welding disk 10 is divided into positive terminal pad 100 and negative terminal pad 101.For example:, then, also can produce red beam by the cooperating of this red light emitting diodes chip and this transparent material if this light-emitting diode chip for backlight unit is a red light emitting diodes chip.
Three, this semiconductor chip 1 can be optical sensing chip, and this encapsulation unit 2 can be transparent material or light transmissive material, and above-mentioned a plurality of conductive welding disk 10 is divided into electrode pad group and signal pad group at least.
Four, this semiconductor chip 1 can be integrated circuit (IC) chip, and this encapsulation unit 2 can be light-proof material, and above-mentioned a plurality of conductive welding disk 10 is divided into electrode pad group and signal pad group at least.
In sum, by above-mentioned semiconductor chip package of the present utility model and preparation method thereof as can be known, because semiconductor chip package of the present utility model does not need can reach electric connection by routing, so the utility model can omit routing and can remove the situation generation that poor electrical contact is arranged because of routing from.
Yet below only be the detailed description and the accompanying drawing of the specific embodiment of one of the utility model the best, but feature of the present utility model is not limited thereto, so above detailed description is not in order to restriction the utility model with accompanying drawing, all scopes of the present utility model should be as the criterion with claims, all embodiment that meets the spirit variation similar of the utility model claim scope with it, all should be contained in the category of the present utility model, any those skilled in the art are in field of the present utility model, and the variation that can expect easily or modification all can be encompassed in the scope of the present utility model.
Claims (4)
1, a kind of semiconductor chip package that does not need can reach by routing electric connection is characterized in that comprising:
Encapsulation unit, it has at least one storage tank;
At least one semiconductor chip, it is placed in this at least one storage tank, and the upper surface of this at least one semiconductor chip has a plurality of conductive welding disks;
The first insulation unit, it has at least one and is formed at first insulating barrier between described a plurality of conductive welding disk, so that described a plurality of conductive welding disk is insulated from each other, wherein this first insulating barrier is formed on this encapsulation unit and this at least one semiconductor chip;
First conductive unit, it has a plurality of first conductive layers that are formed on this at least one first insulating barrier, and an end of each first conductive layer is electrically connected at corresponding conductive welding disk;
The second insulation unit, it has at least one and is formed at second insulating barrier between described a plurality of first conductive layer, so that described a plurality of first conductive layer is insulated from each other, wherein said a plurality of second insulating barriers are covered on described a plurality of first conductive layer; And
Second conductive unit, it has second conductive layer on a plurality of another end opposite that are formed at described a plurality of first conductive layers, and wherein said a plurality of second insulating barriers are formed between described a plurality of second conductive layer.
2, the semiconductor chip package that does not need to reach electric connection as claimed in claim 1 by routing, it is characterized in that: this at least one semiconductor chip is a light-emitting diode chip for backlight unit, this encapsulation unit is fluorescent material or transparent material, and described a plurality of conductive welding disk is divided into positive terminal pad and negative terminal pad, and this light-emitting diode chip for backlight unit has the light-emitting area of the end opposite that is arranged at described a plurality of conductive welding disks in addition.
3, the semiconductor chip package that does not need to reach electric connection as claimed in claim 1 by routing, it is characterized in that: this at least one semiconductor chip is an optical sensing chip, this encapsulation unit is transparent material or light transmissive material, and described a plurality of conductive welding disk is divided into electrode pad group and signal pad group at least.
4, the semiconductor chip package that does not need to reach electric connection as claimed in claim 1 by routing, it is characterized in that: this at least one semiconductor chip is an integrated circuit (IC) chip, this encapsulation unit is a light-proof material, and described a plurality of conductive welding disk is divided into electrode pad group and signal pad group at least.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200820130552 CN201238049Y (en) | 2008-07-16 | 2008-07-16 | Semiconductor chip packaging structure capable of achieving electrical connection without wire bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200820130552 CN201238049Y (en) | 2008-07-16 | 2008-07-16 | Semiconductor chip packaging structure capable of achieving electrical connection without wire bonding |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201238049Y true CN201238049Y (en) | 2009-05-13 |
Family
ID=40650784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200820130552 Expired - Fee Related CN201238049Y (en) | 2008-07-16 | 2008-07-16 | Semiconductor chip packaging structure capable of achieving electrical connection without wire bonding |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201238049Y (en) |
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2008
- 2008-07-16 CN CN 200820130552 patent/CN201238049Y/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090513 Termination date: 20120716 |