CN100341124C - Package process of chip built-in type - Google Patents
Package process of chip built-in type Download PDFInfo
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- CN100341124C CN100341124C CNB2005100537224A CN200510053722A CN100341124C CN 100341124 C CN100341124 C CN 100341124C CN B2005100537224 A CNB2005100537224 A CN B2005100537224A CN 200510053722 A CN200510053722 A CN 200510053722A CN 100341124 C CN100341124 C CN 100341124C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention relates to a chip built-in type packaging process. A support plate is arranged on a pasting belt, wherein the pasting belt is provided with at least one positioning mark which is arranged on the surface of the pasting belt, and the support plate is provided with at least one chip-containing hole; a chip is arranged on the pasting belt and is arranged in the chip-containing hole, wherein the chip is provided with a plurality of jointing pads which are arranged on the surface of the chip facing the pasting belt; a plurality of through holes which penetrate through the pasting belt are formed to expose the jointing pads; conducting materials are filled in the through holes to form a plurality of conducting pore passages, and the conducting pore passages are respectively connected with the jointing pads; finally, a multi-layer inner connecting wire structure is formed on the surface without the chip of the pasting belt, the multi-layer inner connecting wire structure is provided with an inner circuit which is connected with the conducting pore passages, and the inner circuit is provided with a plurality of metal pads which are arranged on the surface of the multi-layer inner connecting wire structure far away from the pasting belt.
Description
Technical field
The present invention relates to a kind of chip encapsulating manufacturing procedure, and particularly have and relate to a kind of chip built-in type (chipembedded) encapsulation procedure.
Background technology
In today of height information society, be many-sided requirements such as high speed processingization, multifunction, productive setization (integration), miniaturization and and low priceization of strengthening electronic element, so chip encapsulation technology is also and then towards microminiaturized, densification development.Known sphere grid array (Ball GridArray, BGA) encapsulation technology often adopts base plate for packaging (package substrate) as the carrier (carrier) of integrated circuit chip (IC chip) and utilize chip bonding (flip chipbonding) or routing joining technique electrical connection technologies such as (wire bonding), chip is electrically connected to the end face of base plate for packaging, and soldered ball (solder ball) face array is connected to the bottom surface of base plate for packaging (area array).Therefore, chip is able to a plurality of soldered balls via the internal wiring of base plate for packaging and bottom thereof, and is electrically connected to the electronic installation of next level, for example printed circuit board (PCB) etc.
Yet, because existing known BGA encapsulation technology must be utilized the base plate for packaging of high wiring density (high layoutdensity), and electric connection technology such as collocation chip bonding or routing joint, thereby cause the signal transmission path long.Therefore, known develop a kind of bumpless increase the layer (Bump-lessBuild-Up a Layer, BBUL) the chip built-in type encapsulation technology of kenel, it omits the processing procedure that chip is connected to known base plate for packaging, promptly omit the processing procedure that chip bonding or routing engage, make a multi-layer internal connection line (multi-layeredinterconnection structure) and directly go up at the active surface (active surface) of chip, and in the mode of face array, on multi-layer internal connection line, make contacts such as soldered ball or stitch, in order to be electrically connected to the electronic installation of next level.
See also shown in Figure 1A～1F, for having the generalized section of known a kind of chip encapsulating manufacturing procedure now.
Shown in Figure 1A, the known chip encapsulating manufacturing procedure of this kind is to provide one to paste band (tape) 110 and a supporting bracket (stiffener) 120 earlier, and supporting bracket 120 is attached at is with on 110.Supporting bracket 120 is in order to increase structural strength and radiating efficiency, to have a chip accommodation hole 122 on it, is the lower ends that cover chip accommodation hole 122 and paste with 110.
Shown in Figure 1B and Fig. 1 C, then dispose a chip 130 and be with on 110, and make chip 130 be positioned at chip accommodation hole 122 in subsides.Dispose a plurality of joint sheets 134 on the active surface 132 of chip 130.And insert a sealing (encapsulant compound) 140 at chip 130 and chip accommodation hole 122.Owing to paste with 110 act on when making chip 130 be disposed in the chip accommodation hole 122, suitable location and bracing force can be arranged, therefore be about to paste in the fixing back of finishing chip 130 and be with 110 to remove, and carry out cleaning action to guarantee not have the residue that pastes with 110 on the chip 130.
Shown in Fig. 1 D, for example on the surface of the active surface 132 of chip 130 and supporting bracket 120, form a multi-layer internal connection line 150 afterwards with Layer increasing method (build-up).Multi-layer internal connection line 150 comprises a plurality of conductor layers 152, at least one dielectric layer 154 and a plurality of conductive blind hole 156 of patterning, wherein these conductor layers 152 are active surfaces 132 of being overlapped in chip 130 in regular turn with the surface of supporting bracket 120 on, and be connected in the joint sheet 134 of chip 130.154 of each dielectric layers are disposed between the two adjacent conductor layers 152, and these conductive blind holes 156 are to run through one of these dielectric layers 154 respectively, and electrically connect at least two conductor layers 152.These conductor layers 152 and these conductive blind holes 156 are the common internal wirings 158 that constitute, and it forms a plurality of metal gaskets 159 in the surface of multi-layer internal connection line 150.
Shown in Fig. 1 E, then form a welding cover layer (solder mask) 160 on multi-layer internal connection line 150.Welding cover layer 160 has a plurality of openings 162, and it exposes metal gasket 159.
Shown in Fig. 1 F, in the opening 162 of welding cover layer 160, print a pre-welding material 170 earlier, on pre-welding material 170, form a plurality of conduction stitch 180 again, promptly finish chip-packaging structure 100.
From the above, known package process of chip built-in type has following shortcoming.Because the subsides band need remove after use and will carry out cleaning, makes processing procedure too loaded down with trivial details and consuming time.After pasting band and removing from chip and supporting bracket, the coplanarity between chip and the supporting bracket (coplanarity) is difficult for keeping, and can cause the reliability reduction of the multi-layer internal connection line of follow-up formation.When forming multi-layer internal connection line, no matter be Laser drill (laser drilling) or little shadow (photolithography), all lack telltale mark, thereby cause the precision of processing procedure and yield to promote.
This shows that above-mentioned existing chip built-in type encapsulation procedure obviously still has inconvenience and defective, and demands urgently further being improved in method and use.In order to solve the problem that package process of chip built-in type exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and general manufacture method does not have appropriate method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new package process of chip built-in type, just become the current industry utmost point to need improved target.
Because the defective that above-mentioned existing chip built-in type encapsulation procedure exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new package process of chip built-in type, can improve general existing chip built-in type encapsulation procedure, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome the defective that existing chip built-in type encapsulation procedure exists, and provide a kind of new package process of chip built-in type, technical problem to be solved is to make it be suitable for shortening the required time of encapsulation procedure, improve setting accuracy and output, improve the structure planarization and encapsulate reliability, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.In order to reach the foregoing invention purpose,, mainly comprise the following steps according to package process of chip built-in type of the present invention.At first disposing a supporting bracket is with in subsides.The material system of pasting band adopts the dielectric material of seeing through property, and pastes band and have at least one first telltale mark, and it is positioned on the surface of pasting band.Has at least one chip accommodation hole on the supporting bracket.Then dispose a chip on subsides are with, and make chip be positioned at the chip accommodation hole.Chip is an active surface towards the surface of pasting band.Chip has most joint sheets, and it is disposed on the active surface.Form a plurality of perforations afterwards on subsides are with, it passes through prick sticking tape to expose joint sheet.Then insert conductive materials in perforation, in order to form a plurality of conductions duct (conducting via).The conduction duct is connected to joint sheet.At last by forming a multi-layer internal connection line with reference to this first telltale mark on the surface of subsides with configuring chip not.Multi-layer internal connection line has an internal wiring, and it is connected in the conduction duct.Internal wiring has a plurality of metal gaskets, and it is positioned at the surface of being with away from subsides of multi-layer internal connection line.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, package process of chip built-in type of the present invention has following advantage at least:
1, in chip encapsulating manufacturing procedure of the present invention, employed subsides are with and are disposed telltale mark, and need not remove the subsides band in the processing procedure.Therefore, for example forming perforation on subsides are with no matter be in the Laser drill mode, or form the opening of dielectric layer in the multi-layer internal connection line in modes such as Laser drill or exposure imagings, perhaps with chip configuration when subsides are with and be positioned the chip accommodation hole, all can utilize this one to have specifically labelled subsides and bring and accurately finish positioning operation.
2, owing to of the present inventionly have specifically labelled subsides band and can improve setting accuracy, thus can carry out chip encapsulating manufacturing procedure to a large amount of chips simultaneously, thereby significantly shorten the required time of chip encapsulating manufacturing procedure.In addition, owing to of the present inventionly have specifically labelled subsides band and will make and can keep preferable coplanarity between chip and the supporting bracket, and then promote the encapsulation reliability.
In sum, the package process of chip built-in type that the present invention is special is suitable for shortening the required time of encapsulation procedure, improves setting accuracy and output, improves structure planarization and encapsulation reliability.It has above-mentioned many advantages and practical value, and in like product and manufacture method, do not see have similar method to publish or use and really genus innovation, no matter it all has bigger improvement on manufacture method or function, have large improvement technically, and produced handy and practical effect, and the multinomial effect that has enhancement than existing chip built-in type encapsulation procedure, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Figure 1A～1F is depicted as the generalized section of known a kind of chip encapsulating manufacturing procedure.
Fig. 2 A～2G is depicted as the flow process generalized section of the package process of chip built-in type of a preferred embodiment of the present invention.
Figure 3 shows that the calcspar of the electronic system of a preferred embodiment of the present invention.
100: chip-packaging structure 110: paste band
120: supporting bracket 122: the chip accommodation hole
130: chip 132: active surface
134: joint sheet 140: sealing
150: multi-layer internal connection line 152: conductor layer
154: dielectric layer 156: conductive blind hole
158: internal wiring 159: metal gasket
160: welding cover layer 162: opening
170: pre-welding material 180: the conduction stitch
200: chip-packaging structure 210: paste band
212: telltale mark 216: line layer
220: supporting bracket 222: the chip accommodation hole
230,232: adhesion coating 240: chip
242: active surface 244: joint sheet
250: sealing 260: the conduction duct
270: multi-layer internal connection line 272: internal wiring
274: metal gasket 276: dielectric layer
278: conductor layer 280: conducting sphere
300: electronic system 310: circuit board
312: bus 330: power-supply unit
340: internal storage location 350: microprocessor
O1: perforation O2: opening
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of package process of chip built-in type, manufacture method, step, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
See also shown in Fig. 2 A～2G, be the flow process generalized section of the package process of chip built-in type of a preferred embodiment of the present invention.Shown in Fig. 2 A, in package process of chip built-in type, at first provide one to paste and to be with 210, its material for example be polyimides (Polyimide, PI).Subsides are with 210 to have at least one telltale mark 212 (this sentences four and is example), and it is positioned at and pastes with on 210 the surface.These telltale marks 212 are not limited to only to be configured in the arbitrary single surface of pasting with 210, also configurable in subsides with 210 two sides.
In addition, paste and to be with 210 for example to have a line layer 216, line layer 216 is to be arranged in to paste with 210 in successive process not on the surface of the chip 240 of hookup 2C, in order to the internal wiring 272 that reconfigures conduction duct 260 and Fig. 2 F and between link position.The formation method of telltale mark 212 for example is to be with in subsides to form a material layer (figure does not show) on 210, utilize little shadow, etch process to come patterned material layer and form telltale mark 212 again, wherein the material of material layer for example is that metal or other process apparatus are easy to the material with reference to identification.It should be noted that being positioned at conplane these telltale marks 212 also can be made of same conductive pattern (indicating) with line layer 216, and conductive pattern is to form by little shadow, etching one conductive layer.
Then see also shown in Fig. 2 B, dispose a supporting bracket 220 and be with on 210 in subsides.Has at least one chip accommodation hole 222 on the supporting bracket 220.Supporting bracket 220 need have enough structural strengths and better heat radiating effect, to provide subsequent configuration in the required protection of the chip 240 of wherein Fig. 2 C.For example be to attach each other between supporting bracket 220 and subsides are with 210 by an adhesion coating 230.Simultaneously, 216 of line layers are positioned at and paste with on 210 the surfaces away from supporting bracket 220.
Then see also shown in Fig. 2 C, dispose a chip 240 and be with on 210, and make chip 240 be positioned at chip accommodation hole 222 in subsides.Chip 240 is an active surface 242 towards subsides with 210 surface, disposes a plurality of joint sheets 244 on it.Chip 240 for example is to be attached at by an adhesion coating 230 to be with on 210.When chip 240 is attached at via adhesion coating 230 when being with 210, can chip 240 accurately be positioned in the chip accommodation hole 222 by reference location mark 212.In addition, after positioning chip 240 is in chip accommodation hole 222, for example more insert a sealing 250 between chip 240 and chip accommodation hole 222, and chip 240 firmly is fixed within the chip accommodation hole 222, in order to reduce chip 240 and supporting bracket 220 and subsides with the displacement between 210, make successive process can be directly with reference to pasting with the telltale mark 212 on 210, and the position of reference chip 240 again.After inserting sealing 250, for example more a sclerosis processing procedure (curing process) is carried out in sealing 250.
Then see also shown in Fig. 2 D, be with on 210 in subsides for example to form a plurality of perforation O1 in the Laser drill mode, it passes through prick sticking tape 210 and adhesion coating 230 to expose these joint sheets 244 respectively.When the Laser drill mode forms perforation O1, for example be to paste by reference to position away from the lip-deep telltale mark 212 of chip 240, or position with the lip-deep telltale mark 212 of 210 its close chips 240 by the subsides of seeing through property of reference tool with 210.In addition, before forming perforation O1, for example more form an adhesion coating 232 with 210 on away from the surface of supporting bracket 220, and these perforation O1 after forming also run through adhesion coating 232 in subsides.
Then see also shown in Fig. 2 E, insert conductive materials in perforation O1, in order to form a plurality of conductions duct 260.Each conduction duct 260 is connected to a joint sheet 244, and partially conductive duct 260 for example is connected in line layer 216, and utilizes line layer 216, and extends to beyond the active surface 242 of chip 240.
Then see also shown in Fig. 2 F, form a multi-layer internal connection line 270 in subsides with 210 not on the surface of configuring chip 240.Multi-layer internal connection line 270 comprises a plurality of dielectric layers 276, a plurality of line layer 278 and a plurality of conductions duct 279.Wherein these dielectric layers 276 and these line layers 278 are to be superimposed with each other in regular turn, these dielectric layers 276 are then run through in these conduction ducts 279 respectively, electrically connect wantonly two adjacent line layers 278 or paste with the conduction duct 260 in 210 and the line layer 278 of the most approaching subsides band.These line layers 278 and these conduction ducts 279 are internal wirings 272 that constitute multi-layer internal connection line 270.Internal wiring 272 is to constitute a plurality of metal gaskets 274 away from subsides with 210 line layer 278 by it.The generation type of multi-layer internal connection line 270 for example is to adopt Layer increasing method to be made in subsides to be with on 210.Dielectric layer 276 is for example to form a plurality of opening O2 thereon in the mode of Laser drill, and promptly utilizes the conduction duct 279 in these openings O2 between the two adjacent conductor layers 278 and electrically connect mutually.
Seeing also at last shown in Fig. 2 G, for example form a conducting sphere 280 or conduction stitch respectively on each metal gasket 274, is example with conducting sphere 280 only at this.The effect of conducting sphere 280 is to provide chip 240 and the extraneous approach that electrically connects, therefore the joint sheet 244 of chip 240 is to be electrically connected to metal gasket 274 via conducting electricity duct 260 and internal wiring 272 in regular turn, and wherein the signal path of part joint sheet 244 for example more comprises the lead that line layer 216 is constituted.
Please continue to consult shown in Fig. 2 G, part telltale mark 212 for example is positioned at chip accommodation hole 222 belows, makes that the navigation system of process apparatus can reference location mark 212, and chip 240 is positioned in the chip accommodation hole 222 exactly.In addition, in package process of chip built-in type of the present invention, the subsides that can adopt navigation system for process apparatus to have seeing through property (visibility) are with 210, therefore the navigation system of process apparatus can see through to paste and be with 210, paste with the telltale mark on 210 the another side 212 and search out, and position with reference to these telltale marks 212.Thus, telltale mark 212 can be not limited to and be configured in which surface of pasting with 210, for example be configured near chip or away from the surface of chip, and the location of the location of chip 240 and Laser drill all can be undertaken by reference location mark 212.
See also shown in Figure 3ly, be the calcspar of the electronic system (ElectronicSystem) of a preferred embodiment of the present invention.See also shown in Figure 3ly, electronic system 300 can comprise a computer system or a communication chip system.Specifically, electronic system 300 for example is applicable to that (PersonalComputer, PC) or an action communication device, wherein mobile communication device for example is the personal digital assistant (PDA) that a mobile phone or has the Mobile Communications function to a PC.Electronic system 300 is to be suitable for being provided on the circuit board 310, and it is made of a bus 312, an internal storage location 340 and a chip built-in type encapsulating structure 200.Internal storage location 340 is connected with bus 312.Chip built-in type encapsulating structure 200 is connected with bus 312, and wherein the composition of chip built-in type encapsulating structure 200 is identical with the chip built-in type encapsulating structure of last embodiment.
In addition, electronic system 300 also can comprise a power-supply unit 330, and it is disposed on the circuit board 310.Chip 240 in the chip built-in type encapsulating structure 200 for example is a microprocessor (microprocessor).Perhaps, electronic system 300 more comprises a microprocessor 350.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (20)
1, a kind of package process of chip built-in type is characterized in that it comprises:
Dispose a supporting bracket and be with in subsides, the material of this subsides band is to adopt the dielectric material of seeing through property, and this subsides band has at least one first telltale mark, and it is positioned on the surface of this subsides band, has at least one chip accommodation hole on this supporting bracket;
Dispose a chip and be with in these subsides, and make this chip be positioned at this chip accommodation hole, wherein this chip is an active surface towards the surface of this subsides band, and this chip has most joint sheets, and it is disposed on this active surface;
Form most perforations and be with in these subsides, wherein those perforations run through this subsides band, to expose those joint sheets;
Insert conductive materials in those perforations, in order to form most conduction ducts, those conduction ducts are connected to those joint sheets; And
Do not dispose on the surface of this chip in this subsides band by form a multi-layer internal connection line with reference to this first telltale mark, this multi-layer internal connection line has an internal wiring, it is connected in those conduction ducts, and this internal wiring has most metal gaskets, and it is positioned at the surface of being with away from these subsides of this multi-layer internal connection line.
2, package process of chip built-in type according to claim 1 is characterized in that wherein said chip is to be with by being disposed at these subsides with reference to this first telltale mark.
3, package process of chip built-in type according to claim 2 is characterized in that wherein said first telltale mark is positioned at the surface of close this chip of this subsides band.
4, package process of chip built-in type according to claim 2, it is characterized in that wherein said first telltale mark be positioned at this subsides band away from the surface of this chip.
5, package process of chip built-in type according to claim 1, it is characterized in that wherein said first telltale mark be positioned at this subsides band away from the surface of this chip.
6, package process of chip built-in type according to claim 1 is characterized in that wherein said first telltale mark is positioned at the surface of close this chip of this subsides band.
7, package process of chip built-in type according to claim 1 is characterized in that wherein said those perforations are to be with by being formed at these subsides with reference to this first telltale mark.
8, package process of chip built-in type according to claim 1 is characterized in that wherein said subsides are with more to dispose at least one second telltale mark, and this first telltale mark and this second telltale mark lay respectively at the two sides of this subsides band.
9, package process of chip built-in type according to claim 8 is characterized in that wherein said chip is to be with by being disposed at these subsides with reference to this second telltale mark.
10, package process of chip built-in type according to claim 8 is characterized in that wherein said multi-layer internal connection line is to be with by being formed at these subsides with reference to this second telltale mark.
11, package process of chip built-in type according to claim 8 is characterized in that wherein said those perforations are to be with by being formed at these subsides with reference to this second telltale mark.
12, package process of chip built-in type according to claim 1, it is characterized in that wherein said subsides band has more a line layer, it is disposed at these subsides and is with, this line layer be positioned at this subsides band away from the surface of this chip, and this line layer is to connect those conduction duct and this internal wirings.
13, package process of chip built-in type according to claim 1, it is characterized in that wherein disposing this chip in these subsides with on method comprise that this chip is attached at these subsides to be with.
14, package process of chip built-in type according to claim 1, it is characterized in that wherein disposing this supporting bracket in these subsides with on method comprise that this supporting bracket is attached at these subsides by an adhesion coating to be with.
15, package process of chip built-in type according to claim 1 is characterized in that it comprises that more configuration one adhesion coating is between this subsides band and this multi-layer internal connection line.
16, package process of chip built-in type according to claim 1 is characterized in that the method that wherein forms this multi-layer internal connection line comprises Layer increasing method (build up).
17, package process of chip built-in type according to claim 1 is characterized in that wherein more being included in and forming a conducting sphere on those metal gaskets respectively after forming this multi-layer internal connection line.
18, package process of chip built-in type according to claim 1 is characterized in that wherein after forming this multi-layer internal connection line, more is included in and forms a conduction stitch on those metal gaskets respectively.
19, package process of chip built-in type according to claim 1 is characterized in that wherein disposing this chip when these subsides are with, and more comprises inserting a sealing between this chip and this chip accommodation hole.
20, package process of chip built-in type according to claim 19 after it is characterized in that wherein inserting this sealing, more comprises a sclerosis processing procedure is carried out in this sealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100537224A CN100341124C (en) | 2005-03-10 | 2005-03-10 | Package process of chip built-in type |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100537224A CN100341124C (en) | 2005-03-10 | 2005-03-10 | Package process of chip built-in type |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1677629A CN1677629A (en) | 2005-10-05 |
| CN100341124C true CN100341124C (en) | 2007-10-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100537224A Active CN100341124C (en) | 2005-03-10 | 2005-03-10 | Package process of chip built-in type |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100341124C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104377187B (en) * | 2013-08-16 | 2017-06-23 | 碁鼎科技秦皇岛有限公司 | IC support plates, the semiconductor devices with the IC support plates and preparation method |
| TWI556365B (en) * | 2014-04-23 | 2016-11-01 | 矽品精密工業股份有限公司 | Prefabricated package structure, method for drilling thereto and drilling device |
Citations (4)
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|---|---|---|---|---|
| JPH10326951A (en) * | 1997-05-23 | 1998-12-08 | Ngk Spark Plug Co Ltd | Wiring board |
| JP2001015557A (en) * | 1999-07-02 | 2001-01-19 | Matsushita Electronics Industry Corp | Semiconductor device and manufacture thereof |
| CN1395302A (en) * | 2001-07-10 | 2003-02-05 | 北京握奇数据系统有限公司 | Chip packaging method and packaging method of its double-interface card |
| CN2613046Y (en) * | 2003-04-17 | 2004-04-21 | 威盛电子股份有限公司 | Chip packaging structure |
-
2005
- 2005-03-10 CN CNB2005100537224A patent/CN100341124C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10326951A (en) * | 1997-05-23 | 1998-12-08 | Ngk Spark Plug Co Ltd | Wiring board |
| JP2001015557A (en) * | 1999-07-02 | 2001-01-19 | Matsushita Electronics Industry Corp | Semiconductor device and manufacture thereof |
| CN1395302A (en) * | 2001-07-10 | 2003-02-05 | 北京握奇数据系统有限公司 | Chip packaging method and packaging method of its double-interface card |
| CN2613046Y (en) * | 2003-04-17 | 2004-04-21 | 威盛电子股份有限公司 | Chip packaging structure |
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|---|---|
| CN1677629A (en) | 2005-10-05 |
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