JP2001015557A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JP2001015557A
JP2001015557A JP18875799A JP18875799A JP2001015557A JP 2001015557 A JP2001015557 A JP 2001015557A JP 18875799 A JP18875799 A JP 18875799A JP 18875799 A JP18875799 A JP 18875799A JP 2001015557 A JP2001015557 A JP 2001015557A
Authority
JP
Japan
Prior art keywords
semiconductor element
carrier substrate
concave portion
semiconductor device
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18875799A
Other languages
Japanese (ja)
Inventor
Kazuhiro Ishikawa
和弘 石川
Shinya Matsumura
信弥 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP18875799A priority Critical patent/JP2001015557A/en
Publication of JP2001015557A publication Critical patent/JP2001015557A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/273Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a resin portion between a semiconductor element and a carrier board is reliably formed while preventing the bulging out of a superfluous portion of resin, to thereby prevent the degradation of adhesive strength between the semiconductor element and the carrier board, and wherein the size of the carrier board is not increased due to the presence of a recognition mark. SOLUTION: This semiconductor device comprises: a carrier board 8 having a recess 7 with a vertically stepping portion in the upper surface thereof, electrodes within the recess 7, and external electrodes 3 on the bottom thereof, the electrodes 3 being connected to the electrodes within the recess 7; a semiconductor element 1 placed into the recess 7 of the board 8 and connected to the electrodes of the board 8 through projecting electrodes 2; and a resin portion 9 provided between the element 1 and the recess 7 of the board 8. This structure prevents a resin from bulging out, which in turn prevents the degradation of adhesive strength between the element 1 and the board 8, and allows a position recognition mark 6 to be located close to the recess 7, i.e., the semiconductor element mounting region. As a result, the size of the board is prevented from increasing, whereby a small-sized semiconductor device can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はフリップチップ実装
工法を用いて、半導体素子をキャリア基板等の被接合体
に樹脂を介在させて実装した半導体装置およびその製造
方法に関するものであり、特に半導体素子と基板等の被
接合体との間に樹脂を効果的に介在させた半導体装置お
よびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element is mounted on a member to be bonded such as a carrier substrate by using a flip-chip mounting method with a resin interposed therebetween, and a method of manufacturing the same. TECHNICAL FIELD The present invention relates to a semiconductor device in which a resin is effectively interposed between a substrate and a body such as a substrate, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、樹脂基板、セラミック基板等の半
導体キャリアや半導体素子、またはプリント基板等のマ
ザーボードヘのチップ実装技術として、主とする半導体
素子をフリップチップ実装する工法が盛んに開発されて
いる。
2. Description of the Related Art In recent years, as a chip mounting technique for a semiconductor carrier or a semiconductor element such as a resin substrate or a ceramic substrate, or a motherboard such as a printed circuit board, a method of flip-chip mounting a main semiconductor element has been actively developed. I have.

【0003】以下、従来のフリップチップ実装工法を用
いた半導体装置の製造方法について図面を参照しながら
説明する。図10〜図13は従来の半導体装置の製造方
法を示す各工程ごとの断面図である。
Hereinafter, a method for manufacturing a semiconductor device using a conventional flip chip mounting method will be described with reference to the drawings. 10 to 13 are cross-sectional views for respective steps showing a conventional method for manufacturing a semiconductor device.

【0004】まず図10に示すように、フリップチップ
しようとする半導体素子1を用意し、その半導体素子1
上の複数の電極パッド(図示せず)上に各々、突起電極
2(バンプ)を形成する。なお、この工程では、さらに
突起電極2の頭頂部の高さを一定にそろえるためにバン
プレベリングが施され、このレベリングでは、平坦板治
具を用いた加圧によるレベリングによって、突起電極2
の高さは、概ね50[μm]にレベリング調整されてい
る。
First, as shown in FIG. 10, a semiconductor device 1 to be flip-chip prepared is prepared.
A protruding electrode 2 (bump) is formed on each of the upper electrode pads (not shown). In this step, bump leveling is further performed in order to make the height of the top of the protruding electrode 2 uniform, and in this leveling, the bump electrode 2 is pressed by leveling using a flat plate jig.
Is leveled to approximately 50 [μm].

【0005】次に図11に示すように、上面に搭載しよ
うとする半導体素子の電極パッドと対応した電極(図示
せず)を有し、底面にその電極と基板内部のビアホール
により接続された外部電極3を有したセラミックなどの
絶縁性のキャリア基板4を用意し、その上面の電極領域
に対して、絶縁性の樹脂フィルム5を載置する。また、
ここではキャリア基板4の上面には、半導体素子をキャ
リア基板に接合する際の半導体素子の位置認識のための
認識マーク6が設けられている。
Next, as shown in FIG. 11, an electrode (not shown) corresponding to an electrode pad of a semiconductor element to be mounted is provided on an upper surface, and an external electrode connected to the electrode by a via hole in the substrate is provided on a bottom surface. An insulating carrier substrate 4 made of ceramic or the like having the electrodes 3 is prepared, and an insulating resin film 5 is placed on the electrode region on the upper surface thereof. Also,
Here, a recognition mark 6 for recognizing the position of the semiconductor element when the semiconductor element is bonded to the carrier substrate is provided on the upper surface of the carrier substrate 4.

【0006】そして図12に示すように、樹脂フィルム
5が載置されたキャリア基板4に対して、その樹脂フィ
ルム5を挟み込むように半導体素子1をその突起電極2
を下にして、認識マーク6により位置合わせし、押圧す
る。すなわち、半導体素子1の突起電極2とキャリア基
板4の電極とを位置合わせして、互いの電極を接続する
ものである。両者間に介在する樹脂フィルム5は、押圧
によって外側領域に逃げながら広がっていくため、突起
電極2とキャリア基板4の電極との間は導通がとれるも
のである。なお、この工程は加熱状況下で行われ、樹脂
フィルム5が軟化され、外側領域に逃げながら広がって
いくものである。
Then, as shown in FIG. 12, the semiconductor element 1 is placed on the projecting electrode 2 so as to sandwich the resin film 5 with respect to the carrier substrate 4 on which the resin film 5 is mounted.
Is positioned downward with the recognition mark 6 and pressed. That is, the protruding electrode 2 of the semiconductor element 1 and the electrode of the carrier substrate 4 are aligned, and the electrodes are connected to each other. Since the resin film 5 interposed therebetween spreads while escaping to the outer region by pressing, conduction between the protruding electrode 2 and the electrode of the carrier substrate 4 can be established. This step is performed under a heating condition, so that the resin film 5 is softened and spreads while escaping to the outer region.

【0007】したがって図13に示すように、半導体素
子1とキャリア基板4とが突起電極2を介して互いの電
極が接続され、両者間には樹脂フィルム5による絶縁性
の樹脂が介在し、また底面には外部電極3を有したフリ
ップチップ実装型の半導体装置が得られるものである。
Therefore, as shown in FIG. 13, the semiconductor element 1 and the carrier substrate 4 are connected to each other via the protruding electrode 2, and an insulating resin by a resin film 5 is interposed therebetween. A flip-chip mounted semiconductor device having an external electrode 3 on the bottom surface is obtained.

【0008】[0008]

【発明が解決しようとする課題】しかしながら前記従来
の半導体装置の製造方法では、半導体素子とキャリア基
板との間に介在した樹脂による諸問題があった。
However, the conventional method of manufacturing a semiconductor device has various problems due to the resin interposed between the semiconductor element and the carrier substrate.

【0009】以下、その諸問題について図面を参照しな
がら説明する。図14は従来の半導体装置を示す平面図
である。
Hereinafter, the problems will be described with reference to the drawings. FIG. 14 is a plan view showing a conventional semiconductor device.

【0010】図14に示すように、半導体素子1とキャ
リア基板4との間の樹脂フィルム5が、接続時の押圧力
によって、外方に逃げようとするが、その逃げ量によっ
て、樹脂フィルム5の樹脂が広がってしまうため、キャ
リア基板4に設ける接合のための位置認識マーク6を基
板の外方部分寄りに配置しなければならず、その結果、
全体としてキャリア基板4を大きくしなければならず、
半導体装置として小型化が困難であった。逆に、認識マ
ーク6を半導体素子1を搭載する近辺に設けた場合は、
樹脂フィルムが接合時の押圧で広がって、認識マークに
被ってしまうため、認識ができず、半導体素子1とキャ
リア基板4の電極との精度の高い接続は困難であった。
As shown in FIG. 14, the resin film 5 between the semiconductor element 1 and the carrier substrate 4 tries to escape outward by the pressing force at the time of connection. Because the resin spreads, the position recognition mark 6 for bonding provided on the carrier substrate 4 must be arranged near the outer portion of the substrate, and as a result,
As a whole, the carrier substrate 4 must be enlarged,
It has been difficult to reduce the size of the semiconductor device. Conversely, when the recognition mark 6 is provided in the vicinity where the semiconductor element 1 is mounted,
Since the resin film spreads due to the pressure at the time of joining and covers the recognition mark, recognition cannot be performed, and it is difficult to connect the semiconductor element 1 and the electrode of the carrier substrate 4 with high accuracy.

【0011】さらに、半導体素子1とキャリア基板4と
の間の樹脂フィルム5が、接続時の押圧力によって、外
方に逃げようとするが、その逃げ量によって、基板半導
体素子1の各辺の側面からはみ出る量に差が生じてしま
う。この樹脂フィルム5のはみ出し量の違いによって、
応力印加に差が生じて、製品としての信頼性を損ねると
いう課題があった。この押圧時の樹脂フィルム5の逃げ
量の差は、キャリア基板上面に対して、樹脂フィルムを
載置する際、その位置決め精度のバラツキ、および樹脂
フィルム量の違いによるものである。
Further, the resin film 5 between the semiconductor element 1 and the carrier substrate 4 tends to escape outward by the pressing force at the time of connection. There is a difference in the amount protruding from the side. Depending on the difference in the amount of protrusion of the resin film 5,
There is a problem in that a difference occurs in stress application and the reliability as a product is impaired. The difference in the escape amount of the resin film 5 at the time of pressing is due to a variation in the positioning accuracy and a difference in the amount of the resin film when the resin film is placed on the upper surface of the carrier substrate.

【0012】また、半導体素子1とキャリア基板4との
接続時の押圧力如何によっては、樹脂フィルム5の半導
体素子1の側面部分が弛みを有し、半導体素子/キャリ
ア基板間の接続強度の劣化を引き起こす恐れがあった。
樹脂フィルム5の弛みが、少ない場合であれば、製品の
検査工程においても影響はなく、検査工程を進めること
ができるが、樹脂フィルム5の弛みが、その高さが大き
い場合であれば、製品検査時のソケット収納で、余分な
厚みとなり、半導体素子自体にソケットによる押圧力が
印加され、半導体素子の割れを引き起こす恐れもある。
Further, depending on the pressing force at the time of connection between the semiconductor element 1 and the carrier substrate 4, the side surface of the semiconductor element 1 of the resin film 5 is slackened, and the connection strength between the semiconductor element and the carrier substrate is deteriorated. Could cause
If the slack of the resin film 5 is small, there is no effect in the inspection process of the product, and the inspection process can proceed. However, if the slack of the resin film 5 is large, When the socket is stored during the inspection, the thickness becomes excessive, and the pressing force of the socket is applied to the semiconductor element itself, which may cause the semiconductor element to crack.

【0013】本発明は前記従来の課題を解決するもので
あり、半導体素子/キャリア基板間の樹脂を余分なはみ
出しを抑えて確実に形成し、両者間の接着強度の劣化を
防止し、かつ認識マークの配置によるキャリア基板の大
型化を避けた半導体装置を提供するものであり、また半
導体素子とキャリア基板との間に位置精度よく樹脂を介
在した半導体装置およびその製造方法を提供することを
目的とする。
SUMMARY OF THE INVENTION The present invention is to solve the above-mentioned conventional problems, and it is possible to form a resin between a semiconductor element and a carrier substrate with certainty by suppressing excess protrusion, to prevent deterioration of the adhesive strength between the two, and to recognize the problem. It is an object of the present invention to provide a semiconductor device in which a carrier substrate is prevented from being enlarged due to the arrangement of marks, and to provide a semiconductor device in which a resin is interposed between a semiconductor element and a carrier substrate with high precision and a method of manufacturing the same. And

【0014】[0014]

【課題を解決するための手段】前記従来の課題を解決す
るために本発明の半導体装置およびその製造方法は以下
のような構成を有している。すなわち、本発明の半導体
装置は、上面に段差部分が垂直な凹部と、前記凹部内の
面に配線電極を有し、底面に前記配線電極と基板内部の
ビアホールにより接続された外部電極を有したキャリア
基板と、前記キャリア基板の前記凹部に載置され、前記
配線電極とその主面の電極パッドとが突起電極を介して
接続された半導体素子と、前記半導体素子と前記キャリ
ア基板の凹部との間に設けられた樹脂部と、前記キャリ
ア基板の上面の前記凹部の対角部近傍に設けられた位置
認識マークとよりなる半導体装置である。
In order to solve the above-mentioned conventional problems, a semiconductor device and a method of manufacturing the same according to the present invention have the following configurations. That is, the semiconductor device of the present invention has a concave portion having a step portion perpendicular to the upper surface, a wiring electrode on a surface inside the concave portion, and an external electrode connected to the wiring electrode and a via hole inside the substrate on a bottom surface. A carrier element, a semiconductor element mounted on the concave portion of the carrier substrate, wherein the wiring electrode and an electrode pad on the main surface thereof are connected via a protruding electrode; and a semiconductor element and the concave portion of the carrier substrate. A semiconductor device comprising a resin portion provided therebetween and a position recognition mark provided near a diagonal portion of the concave portion on the upper surface of the carrier substrate.

【0015】具体的には、半導体素子の面とキャリア基
板上面との間に放熱性接着剤を介して放熱板が設けられ
ている半導体装置である。
Specifically, the semiconductor device has a heat radiating plate provided between the surface of the semiconductor element and the upper surface of the carrier substrate via a heat radiating adhesive.

【0016】また本発明の半導体装置の製造方法は、半
導体素子の電極パッド上に突起電極を形成する工程と、
上面に段差部分が垂直な凹部と、前記凹部内に前記半導
体素子の電極パッドと対応した電極と、底面に前記電極
と基板内部のビアホールにより接続された外部電極と、
基板上面の前記凹部の対角部近傍に設けられた位置認識
マークとを有したキャリア基板とを用意する工程と、前
記キャリア基板の凹部に前記凹部の底面積と同等面積を
有した樹脂フィルムを載置する工程と、前記半導体素子
の前記突起電極が形成された面を樹脂フィルムが載置さ
れた前記キャリア基板の凹部に対して前記位置認識マー
クによって位置合わせする工程と、前記半導体素子の前
記突起電極が形成された面を樹脂フィルムが載置された
前記キャリア基板の凹部に対して押圧し、前記半導体素
子の前記突起電極と前記キャリア基板の上面の電極とを
接続する工程とよりなる半導体装置の製造方法である。
Further, the method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a protruding electrode on an electrode pad of a semiconductor element;
A concave portion having a step portion perpendicular to the upper surface, an electrode corresponding to the electrode pad of the semiconductor element in the concave portion, and an external electrode connected to the electrode and a via hole inside the substrate on the bottom surface,
A step of preparing a carrier substrate having a position recognition mark provided near a diagonal portion of the concave portion on the upper surface of the substrate, and a resin film having an area equivalent to the bottom area of the concave portion in the concave portion of the carrier substrate. Mounting, and positioning the surface of the semiconductor element on which the protruding electrodes are formed with the position recognition mark with respect to the concave portion of the carrier substrate on which a resin film is mounted; and Pressing the surface on which the protruding electrodes are formed against the concave portion of the carrier substrate on which the resin film is mounted, and connecting the protruding electrodes of the semiconductor element and the electrodes on the upper surface of the carrier substrate. It is a manufacturing method of an apparatus.

【0017】具体的には、半導体素子の突起電極が形成
された面を樹脂フィルムが載置されたキャリア基板の凹
部に対して押圧し、前記半導体素子の前記突起電極と前
記キャリア基板の上面の電極とを接続する工程は、加熱
状況下で行う半導体装置の製造方法である。
Specifically, the surface of the semiconductor element on which the projecting electrodes are formed is pressed against the concave portion of the carrier substrate on which the resin film is mounted, and the projecting electrodes of the semiconductor element and the upper surface of the carrier substrate are pressed. The step of connecting the electrodes is a method of manufacturing a semiconductor device performed under a heating condition.

【0018】前記構成の通り、本発明の半導体装置は、
凹部に樹脂部が収納した形で介在しているので、半導体
素子/キャリア基板間の樹脂を余分なはみ出しを抑えて
確実に形成し、両者間の接着強度の劣化を防止した半導
体装置を実現できる。また、凹部の段差が垂直に構成さ
せているので、搭載した半導体素子と凹部の大きさ(開
口面積)とを同等レベルの大きさとすることができ、凹
部の近傍の対角部分の基板上に位置認識マークを配置で
きるため、キャリア基板を必要以上に大きくせず、位置
認識マークを配置できる。
As described above, the semiconductor device of the present invention comprises:
Since the resin portion is interposed in the recess so as to be housed, the resin between the semiconductor element and the carrier substrate is reliably formed by suppressing excess protrusion, and a semiconductor device in which the adhesive strength between the two is prevented from deteriorating can be realized. . In addition, since the step of the concave portion is formed vertically, the size (opening area) of the mounted semiconductor element and the concave portion can be set to the same level, and the diagonal portion near the concave portion can be formed on the substrate. Since the position recognition mark can be arranged, the position recognition mark can be arranged without making the carrier substrate unnecessarily large.

【0019】また本発明の半導体装置の製造方法の通
り、キャリア基板の凹部にその凹部の底面積の同等面
積、またはそれより小さく相似形を有した樹脂フィルム
を載置するため、セルフアライメント的に位置決めが行
われ、位置決め精度のバラツキを抑え、半導体素子/キ
ャリア基板の接続時の押圧でも外方に逃げる樹脂フィル
ムを均一とすることができる。さらに、キャリア基板の
凹部は、垂直な段差で形成されているため、半導体素子
/キャリア基板の接続時の押圧で外方に逃げる樹脂フィ
ルムは、凹部からはみ出さず、かつ、外方に逃げる樹脂
フィルムを均一にし、かつその凹部内に確実に形成する
ことができる。そのため応力印加によっても局所な印加
を避け、製品としての信頼性を損ねることを防止でき
る。また、樹脂が凹部からはみ出さないため、認識マー
クを基板の凹部の対角の近傍に配置しても、その認識マ
ークが樹脂で覆われないので、キャリア基板を必要以上
に大きくする必要はない。
According to the method of manufacturing a semiconductor device of the present invention, a resin film having an area equal to or smaller than the bottom area of the concave portion is placed in the concave portion of the carrier substrate. Positioning is performed, and variations in positioning accuracy can be suppressed, and the resin film that escapes outward even when pressed when the semiconductor element / carrier substrate is connected can be made uniform. Further, since the concave portion of the carrier substrate is formed by a vertical step, the resin film which escapes outward by pressing when connecting the semiconductor element / carrier substrate does not protrude from the concave portion and the resin film which escapes outward. The film can be made uniform and can be reliably formed in the recess. Therefore, it is possible to avoid local application even by applying a stress, thereby preventing the reliability of the product from being impaired. Further, since the resin does not protrude from the concave portion, even if the recognition mark is arranged near the diagonal of the concave portion of the substrate, the recognition mark is not covered with the resin, so that the carrier substrate does not need to be made larger than necessary. .

【0020】[0020]

【発明の実施の形態】以下、本発明の半導体装置および
その製造方法の一実施形態について、図面を参照しなが
ら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

【0021】まず本発明の半導体装置の一実施形態につ
いて説明する。図1,図2は本実施形態の半導体装置を
示す断面図である。
First, one embodiment of the semiconductor device of the present invention will be described. 1 and 2 are cross-sectional views illustrating a semiconductor device according to the present embodiment.

【0022】まず、図1に示すように、本実施形態の半
導体装置は、上面に段差部分が垂直な凹部7と、その凹
部内の面に配線電極(図示せず)を有し、底面にその配
線電極と基板内部のビアホールにより接続された外部電
極3を有したキャリア基板8と、そのキャリア基板8の
凹部7に載置され、基板の配線電極とその主面の電極パ
ッドとが突起電極2を介して接続された半導体素子1
と、その半導体素子1とキャリア基板8の凹部7との間
に設けられた樹脂部9とよりなるものである。
First, as shown in FIG. 1, the semiconductor device of the present embodiment has a concave portion 7 having a vertical step on the upper surface, a wiring electrode (not shown) on the surface within the concave portion, and A carrier substrate 8 having an external electrode 3 connected to the wiring electrode by a via hole inside the substrate and a recessed portion 7 of the carrier substrate 8 are provided. Semiconductor device 1 connected via
And a resin portion 9 provided between the semiconductor element 1 and the concave portion 7 of the carrier substrate 8.

【0023】本実施形態の半導体装置は、搭載する半導
体素子の面積と同等またはそれよりも大きい開口部を有
した凹部7に樹脂部9が収納された形で介在しているの
で、半導体素子1/キャリア基板8間の樹脂部9が余分
なはみ出しを抑えられて確実に形成されており、両者間
の接着強度の劣化を防止した半導体装置である。
In the semiconductor device of this embodiment, since the resin portion 9 is housed in the recess 7 having an opening equal to or larger than the area of the semiconductor element to be mounted, the semiconductor element 1 This is a semiconductor device in which the resin portion 9 between the / carrier substrates 8 is reliably formed with excessive protrusion suppressed, and deterioration of the adhesive strength between the two is prevented.

【0024】基板上の凹部7において、その段差角度は
垂直(90度)であり、樹脂部9が確実にその凹部内に
形成されるような角度である。凹部7の段差が垂直に構
成されているので、搭載した半導体素子1と凹部7の大
きさ(開口面積)とを同等レベルの大きさとすることが
でき、凹部7の近傍の対角部分の基板上に位置認識マー
ク6を配置できるため、キャリア基板を必要以上に大き
くせず、位置認識マーク6を配置できるものである。
In the concave portion 7 on the substrate, the step angle is vertical (90 degrees), and is an angle such that the resin portion 9 is securely formed in the concave portion. Since the step of the concave portion 7 is formed vertically, the size (opening area) of the mounted semiconductor element 1 and the concave portion 7 can be set to the same level, and the diagonal substrate near the concave portion 7 can be formed. Since the position recognition mark 6 can be disposed thereon, the position recognition mark 6 can be disposed without making the carrier substrate unnecessarily large.

【0025】また、キャリア基板8の上面の高さと同一
面にまで樹脂部9が形成されているものである。すなわ
ち、半導体素子1の突起電極2の面と側面部とを樹脂部
9で包囲した構造である。このような構造とすることに
より、さらに半導体素子1/キャリア基板8間の接着強
度の劣化を防止でき、信頼性を高めることができる。
The resin portion 9 is formed up to the same level as the height of the upper surface of the carrier substrate 8. That is, the semiconductor element 1 has a structure in which the surface and the side surface of the protruding electrode 2 are surrounded by the resin portion 9. With such a structure, it is possible to further prevent the adhesive strength between the semiconductor element 1 and the carrier substrate 8 from deteriorating, thereby improving reliability.

【0026】なお、本実施形態では、樹脂部9はエポキ
シ樹脂を主成分とする絶縁性の樹脂であり、キャリア基
板8としては、絶縁性基板としてセラミック基板、エポ
キシ樹脂を主成分とする樹脂基板であり、上面に配線パ
ターンとその配線電極を有し、その配線電極と内部接続
された外部電極を底面に有した基板である。また本実施
形態では、樹脂部9はフィルム状の樹脂を介在させ、樹
脂部としたものであるが、流動性のある樹脂を介在させ
て樹脂部を形成してもよい。
In this embodiment, the resin portion 9 is an insulating resin mainly composed of epoxy resin, and the carrier substrate 8 is a ceramic substrate as an insulating substrate or a resin substrate mainly composed of epoxy resin. This is a substrate having a wiring pattern and its wiring electrode on the upper surface, and having an external electrode internally connected to the wiring electrode on the bottom surface. Further, in the present embodiment, the resin part 9 is a resin part with a film-like resin interposed therebetween, but the resin part may be formed with a fluid resin.

【0027】さらに凹部7の深さ(段差)は、半導体素
子1を収納し、半導体素子1底面側とキャリア基板8の
上面とを同一面とするのであれば、半導体素子1の厚み
+突起電極2の高さ以上の深さ(段差)とし、本実施形
態では、半導体素子1の厚みが300[μm]であり、
突起電極2の高さがレベリング後で50[μm]である
ため、凹部7の深さを350[μm]としている。また
図1に示すように、半導体素子1の底面側をキャリア基
板8の上面よりも突出させる場合は、凹部7の深さを2
50[μm]程度としてもよい。
Further, the depth (step) of the concave portion 7 is determined by the thickness of the semiconductor element 1 plus the protrusion electrode if the semiconductor element 1 is housed and the bottom surface of the semiconductor element 1 and the upper surface of the carrier substrate 8 are flush with each other. 2, and the thickness of the semiconductor element 1 is 300 [μm] in this embodiment.
Since the height of the protruding electrode 2 is 50 [μm] after leveling, the depth of the concave portion 7 is set to 350 [μm]. In addition, as shown in FIG. 1, when the bottom surface side of the semiconductor element 1 is protruded from the upper surface of the carrier substrate 8, the depth of the recess
It may be about 50 [μm].

【0028】また本実施形態の半導体装置において、凹
部7の面とキャリア基板8の底面との厚みTについて
は、0.1[mm]〜0.5[mm]とすることによ
り、熱膨張による搭載した半導体素子1の突起電極2に
印加される応力による影響を抑制できるため、フリップ
チップ実装の信頼性を向上させることができるものであ
る。
Further, in the semiconductor device of the present embodiment, the thickness T between the surface of the concave portion 7 and the bottom surface of the carrier substrate 8 is set to 0.1 [mm] to 0.5 [mm], so that the thickness T due to thermal expansion is increased. Since the influence of the stress applied to the bump electrode 2 of the mounted semiconductor element 1 can be suppressed, the reliability of flip-chip mounting can be improved.

【0029】次に図2に示す半導体装置は、樹脂部9の
高さが図1に示した半導体装置と異なる構成であり、半
導体素子1の底面(背面)、キャリア基板8の上面部分
に放熱性接着剤10により、放熱部材11を設けたもの
である。
Next, the semiconductor device shown in FIG. 2 is different from the semiconductor device shown in FIG. 1 in that the height of the resin portion 9 is different from that of the semiconductor device shown in FIG. The heat dissipating member 11 is provided by the adhesive 10.

【0030】本実施形態の構造により、放熱部材11が
半導体素子1より発せられる熱を半導体素子1の背面お
よび、キャリア基板8から受け、外部に放熱させること
ができるので、発熱による半導体素子1の劣化、特性不
良を防止できるものである。
According to the structure of this embodiment, the heat radiating member 11 can receive the heat generated from the semiconductor element 1 from the back surface of the semiconductor element 1 and the carrier substrate 8 and radiate the heat to the outside. Deterioration and poor characteristics can be prevented.

【0031】また、図2に示したように半導体素子1の
突起電極2の面と側面部とを樹脂部9で包囲した構造で
あるため、半導体素子1からの発熱をキャリア基板8側
に伝導させ、放熱部材11によって効率よく外部に放熱
できるものである。
Further, as shown in FIG. 2, since the surface and the side surface of the protruding electrode 2 of the semiconductor element 1 are surrounded by the resin portion 9, heat generated from the semiconductor element 1 is conducted to the carrier substrate 8 side. Thus, the heat radiating member 11 can efficiently radiate heat to the outside.

【0032】次に本発明の半導体装置の製造方法は、主
として、半導体素子の電極パッドとキャリア基板上の電
極とをフィルム状の樹脂を介在させて接続する半導体装
置の製造方法においては、キャリア基板として、垂直な
段差部を有した凹部と、その凹部内に半導体素子の電極
パッドと対応した電極を有したキャリア基板を用い、そ
のキャリア基板の凹部にその凹部の底面積と同等面積を
有した樹脂フィルムを載置し、半導体素子の電極パッド
が形成された面を樹脂フィルムが載置されたキャリア基
板の凹部に対して押圧し、半導体素子の電極パッドとキ
ャリア基板上の電極とを接続することを主眼とするもの
である。
Next, the method of manufacturing a semiconductor device according to the present invention mainly includes a method of manufacturing a semiconductor device in which an electrode pad of a semiconductor element and an electrode on a carrier substrate are connected via a film-like resin. As a concave portion having a vertical step portion and a carrier substrate having electrodes corresponding to the electrode pads of the semiconductor element in the concave portion, the concave portion of the carrier substrate had the same area as the bottom area of the concave portion. The resin film is placed, and the surface of the semiconductor element on which the electrode pads are formed is pressed against the concave portion of the carrier substrate on which the resin film is placed, and the electrode pads of the semiconductor element are connected to the electrodes on the carrier substrate. It is the main purpose.

【0033】以下、本発明の半導体装置の製造方法の一
実施形態について図面を参照しながら説明する。
Hereinafter, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

【0034】図3〜図7は本実施形態の半導体装置の製
造方法を示す断面図である。
FIGS. 3 to 7 are sectional views showing a method for manufacturing the semiconductor device of the present embodiment.

【0035】まず図3に示すように、基板に対してフリ
ップチップしようとする半導体素子1を用意し、その半
導体素子1上の複数の電極パッド(図示せず)上に各
々、突起電極2(バンプ)を形成する。なお、この工程
では、さらに突起電極2の頭頂部の高さを一定にそろえ
るためにバンプレベリングが施され、このレベリングで
は、平坦板治具を用いた加圧によるレベリングによっ
て、突起電極2の高さは、概ね50[μm]にレベリン
グ調整されている。
First, as shown in FIG. 3, a semiconductor element 1 to be flip-chip mounted on a substrate is prepared, and projecting electrodes 2 (not shown) are formed on a plurality of electrode pads (not shown) on the semiconductor element 1. (Bump) is formed. In this step, bump leveling is further performed to make the height of the top of the protruding electrode 2 uniform, and in this leveling, the height of the protruding electrode 2 is increased by leveling using a flat plate jig. The level is adjusted to about 50 [μm].

【0036】次に図4に示すように、上面に段差部分が
垂直な構成を有した凹部7と、その凹部7内に半導体素
子の電極パッドと対応した配線電極と、底面にその配線
電極と基板内部のビアホールにより接続された外部電極
3と、基板上面の凹部7の対角部近傍に設けられた位置
認識マーク6とを有したキャリア基板8を用意し、その
キャリア基板8の凹部7にその凹部7の底面積と同等面
積、同等形状を有した樹脂フィルム5を載置する。本実
施形態では、凹部7の面積と同等であって、搭載する半
導体素子と相似形の樹脂フィルム5を用いているので、
樹脂フィルム5の位置決めがセルフアライメント的に行
われ、位置決め精度のバラツキを抑え、半導体素子/キ
ャリア基板の接続時の押圧時に外方に逃げる樹脂(樹脂
フィルム)を均一とすることができる。また、ここで載
置する樹脂フィルム5は、エポキシ樹脂を主成分とする
絶縁性の樹脂フィルムであり、その厚みは40[μm]
のシートを用いているが、キャリア基板8の凹部7の深
さ(段差)と、半導体素子の側端面の所望とする被覆面
積によっては、100[μm]程度でもよい。
Next, as shown in FIG. 4, a concave portion 7 having a structure in which a step portion is perpendicular to the upper surface, a wiring electrode corresponding to the electrode pad of the semiconductor element in the concave portion 7, and a wiring electrode on the bottom surface. A carrier substrate 8 having an external electrode 3 connected by a via hole inside the substrate and a position recognition mark 6 provided near a diagonal portion of a concave portion 7 on the upper surface of the substrate is prepared. The resin film 5 having the same area and the same shape as the bottom area of the recess 7 is placed. In the present embodiment, since the resin film 5 having the same area as the recess 7 and having a similar shape to the semiconductor element to be mounted is used,
The positioning of the resin film 5 is performed in a self-aligned manner, the variation in positioning accuracy can be suppressed, and the resin (resin film) that escapes outward when pressed when the semiconductor element / carrier substrate is connected can be made uniform. The resin film 5 placed here is an insulating resin film containing an epoxy resin as a main component, and has a thickness of 40 [μm].
The sheet may be about 100 [μm] depending on the depth (step) of the concave portion 7 of the carrier substrate 8 and the desired covering area of the side end face of the semiconductor element.

【0037】次に図5に示すように、半導体素子1の突
起電極2が形成された面を樹脂フィルム5が載置された
キャリア基板8の凹部7に対して、配置した位置認識マ
ーク6により位置合わせした後、押圧して半導体素子1
の突起電極2とキャリア基板8の上面の電極とを接続す
る。この工程では、加熱状況下で行なわれるものであ
り、キャリア基板8がセラミック基板の場合は220
[℃]であり、またキャリア基板8が樹脂基板の場合は
180[℃]であり、その接続のための押圧時間は、2
0[sec]程度の数10[sec]である。
Next, as shown in FIG. 5, the surface of the semiconductor element 1 on which the protruding electrodes 2 are formed is positioned with respect to the concave portion 7 of the carrier substrate 8 on which the resin film 5 is mounted, by using the position recognition mark 6 arranged. After the alignment, press the semiconductor element 1
Are connected to the electrodes on the upper surface of the carrier substrate 8. This step is performed under a heating condition, and when the carrier substrate 8 is a ceramic substrate, 220
[° C.], and 180 ° C. when the carrier substrate 8 is a resin substrate, and the pressing time for the connection is 2 ° C.
It is several tens [sec] of about 0 [sec].

【0038】ここで図6に示すように、接続のための押
圧において、半導体素子1を樹脂フィルム5を介在させ
てキャリア基板8に対して押圧した場合、キャリア基板
8側は加熱されているので、樹脂フィルム5は軟化して
おり、押圧により樹脂は広がり、外方に逃げる(矢印
A)。そしてその外方に逃げる過程では、樹脂は凹部7
の垂直な壁に当接することにより、凹部7内を充填し、
凹部7とキャリア基板8との境界部分でその表面張力に
よって留まり、はみ出しはない。なお、過剰な厚みの樹
脂フィルム5を用いると、凹部7から樹脂がはみ出して
しまう恐れがあるので、適宜、最適の厚みの樹脂フィル
ムを用いる。
As shown in FIG. 6, when the semiconductor element 1 is pressed against the carrier substrate 8 with the resin film 5 interposed in the pressing for connection, the carrier substrate 8 side is heated. The resin film 5 is softened, and the resin spreads by pressing and escapes outward (arrow A). In the process of escaping to the outside, the resin
Filling the recess 7 by abutting against the vertical wall of
At the boundary between the concave portion 7 and the carrier substrate 8, it stays due to its surface tension and does not protrude. If the resin film 5 having an excessive thickness is used, the resin may run out of the recess 7. Therefore, an appropriate thickness of the resin film is used as appropriate.

【0039】したがって図7に示すように、上面に段差
部分が垂直な構成を有した凹部7と、その凹部内の面に
配線電極(図示せず)を有し、底面にその配線電極と基
板内部のビアホールにより接続された外部電極3と、基
板上面の凹部7の対角部近傍に設けられた位置認識マー
ク6とを有したキャリア基板8と、そのキャリア基板の
凹部7に載置され、基板の配線電極とその主面の電極パ
ッドとが突起電極2を介して接続された半導体素子1
と、その半導体素子1とキャリア基板8の凹部7との間
に設けられた樹脂部9とよりなるフリップチップ実装型
の半導体装置が得られるものである。
Accordingly, as shown in FIG. 7, a concave portion 7 having a structure in which a step portion is perpendicular to the upper surface, a wiring electrode (not shown) on the surface within the concave portion, and the wiring electrode and the substrate on the bottom surface. A carrier substrate 8 having an external electrode 3 connected by an internal via hole and a position recognition mark 6 provided in the vicinity of a diagonal portion of the concave portion 7 on the upper surface of the substrate, and placed on the concave portion 7 of the carrier substrate; A semiconductor element 1 in which a wiring electrode of a substrate and an electrode pad on its main surface are connected via a protruding electrode 2
And a resin portion 9 provided between the semiconductor element 1 and the concave portion 7 of the carrier substrate 8 to obtain a flip-chip mounting type semiconductor device.

【0040】本実施形態の半導体装置の製造方法により
得られた半導体装置は、図8,図9に示すように、半導
体素子1/キャリア基板8間の樹脂9の余分なはみ出し
を抑えて確実かつ均一に形成し、両者間の接着強度の劣
化を防止した半導体装置である。そして余分なはみ出し
を抑えることができる構成を有したキャリア基板8であ
るため、凹部7の対角の近傍の基板上に位置認識マーク
6を配置でき、キャリア基板8としては、必要以上に大
きくする必要はない。なお、図8は本実施形態の半導体
装置を示す平面図であり、図9は図8の半導体装置のA
−A1箇所の断面図である。
As shown in FIGS. 8 and 9, the semiconductor device obtained by the method for manufacturing a semiconductor device according to the present embodiment can reliably and reliably prevent the resin 9 between the semiconductor element 1 and the carrier substrate 8 from protruding. This is a semiconductor device that is formed uniformly and prevents deterioration in adhesive strength between the two. Since the carrier substrate 8 has a configuration capable of suppressing excess protrusion, the position recognition mark 6 can be arranged on the substrate near the diagonal of the concave portion 7, and the carrier substrate 8 is made unnecessarily large. No need. FIG. 8 is a plan view showing the semiconductor device of the present embodiment, and FIG.
It is sectional drawing of -A1 location.

【0041】なお、本実施形態において、キャリア基板
としては、底面に複数の外部接続用のランドである外部
電極が形成され、その外部電極と内部ビアによって電気
的に接続した配線電極をその表面に有する絶縁性基板で
あるが、キャリア基板としては、プリント基板等のマザ
ー実装基板であってもよい。
In the present embodiment, a plurality of external electrodes, which are lands for external connection, are formed on the bottom surface of the carrier substrate, and wiring electrodes electrically connected to the external electrodes by internal vias are formed on the surface thereof. The carrier board may be a mother mounting board such as a printed board.

【0042】以上、本実施形態の半導体装置では、凹部
に樹脂部が収納した形で介在しているので、半導体素子
/キャリア基板間の樹脂を余分なはみ出しを抑えて確実
に形成し、両者間の接着強度の劣化を防止した半導体装
置を実現できる。また位置認識マークを凹部、すなわち
半導体素子を搭載する領域の近傍に配置できるので、基
板の大型化を抑え、小型の半導体装置を実現できる。
As described above, in the semiconductor device of the present embodiment, since the resin portion is interposed in the recess so as to be housed therein, the resin between the semiconductor element and the carrier substrate is reliably formed by suppressing excess protrusion, and the resin is formed between the semiconductor element and the carrier substrate. Semiconductor device in which deterioration of the adhesive strength of the semiconductor device is prevented. In addition, since the position recognition mark can be arranged in the concave portion, that is, in the vicinity of the region where the semiconductor element is mounted, the size of the substrate can be suppressed and a small semiconductor device can be realized.

【0043】また半導体装置の製造方法においては、キ
ャリア基板の凹部にその凹部の底面積の同等面積または
それより小さく、半導体素子の面積以上であって相似形
を有した樹脂フィルムを載置するため、セルフアライメ
ント的に位置決めが行われ、位置決め精度のバラツキを
抑え、半導体素子/キャリア基板の接続時の押圧でも外
方に逃げる樹脂フィルムを均一とすることができる。
Further, in the method of manufacturing a semiconductor device, a resin film having a similar shape which is equal to or smaller than the bottom area of the concave portion, is equal to or larger than the area of the semiconductor element, and is mounted on the concave portion of the carrier substrate. In addition, positioning is performed in a self-alignment manner, variation in positioning accuracy is suppressed, and the resin film that escapes outward even when pressed when the semiconductor element / carrier substrate is connected can be made uniform.

【0044】[0044]

【発明の効果】以上、本発明の半導体装置は、半導体素
子/キャリア基板間の樹脂が余分なはみ出しを抑えて確
実に形成され、両者間の接着強度の劣化を防止した半導
体装置である。また半導体素子とキャリア基板との間に
位置精度よく樹脂を介在した半導体装置である。
As described above, the semiconductor device according to the present invention is a semiconductor device in which the resin between the semiconductor element and the carrier substrate is reliably formed by suppressing excess protrusion, and deterioration of the adhesive strength between the two is prevented. Further, the present invention is a semiconductor device in which a resin is interposed between a semiconductor element and a carrier substrate with high positional accuracy.

【0045】また本発明の半導体装置の製造方法によ
り、キャリア基板の凹部にその凹部の底面積の同等面積
またはそれより小さく、半導体素子の面積以上であって
相似形を有した樹脂フィルムを載置するため、セルフア
ライメント的に位置決めが行われ、位置決め精度のバラ
ツキを抑え、半導体素子/キャリア基板の接続時の押圧
でも外方に逃げる樹脂フィルムを均一とすることができ
る。そのため、半導体素子/キャリア基板の両者間の接
着強度の劣化を防止し、半導体素子とキャリア基板との
間に位置精度よく樹脂を介在した半導体装置を実現でき
るものである。さらに、樹脂が凹部からはみ出さないた
め、認識マークを基板の凹部の対角の近傍に配置して
も、その認識マークが樹脂で覆われないので、キャリア
基板を必要以上に大きくする必要はなく小型化を実現で
きる。
Further, according to the method of manufacturing a semiconductor device of the present invention, a resin film having a similar shape that is equal to or smaller than the area of the bottom of the recess, is equal to or larger than the area of the semiconductor element and is larger than the area of the semiconductor element is placed in the recess of the carrier substrate. Therefore, positioning is performed in a self-alignment manner, variation in positioning accuracy can be suppressed, and a resin film that escapes outward even when pressed when the semiconductor element / carrier substrate is connected can be made uniform. Therefore, it is possible to prevent the deterioration of the adhesive strength between the semiconductor element and the carrier substrate, and to realize a semiconductor device in which a resin is interposed between the semiconductor element and the carrier substrate with high positional accuracy. Furthermore, since the resin does not protrude from the concave portion, even if the recognition mark is arranged near the diagonal of the concave portion of the substrate, the recognition mark is not covered with the resin, so that the carrier substrate does not need to be made larger than necessary. Miniaturization can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の半導体装置を示す断面図FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施形態の半導体装置を示す断面図FIG. 2 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

【図3】本発明の一実施形態の半導体装置を示す断面図FIG. 3 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

【図4】本発明の一実施形態の半導体装置の製造方法を
示す断面図
FIG. 4 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;

【図5】本発明の一実施形態の半導体装置の製造方法を
示す断面図
FIG. 5 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;

【図6】本発明の一実施形態の半導体装置の製造方法を
示す断面図
FIG. 6 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;

【図7】本発明の一実施形態の半導体装置の製造方法を
示す断面図
FIG. 7 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;

【図8】本発明の一実施形態の半導体装置を示す平面図FIG. 8 is a plan view showing a semiconductor device according to one embodiment of the present invention;

【図9】本発明の一実施形態の半導体装置を示す断面図FIG. 9 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

【図10】従来の半導体装置の製造方法を示す断面図FIG. 10 is a sectional view showing a conventional method for manufacturing a semiconductor device.

【図11】従来の半導体装置の製造方法を示す断面図FIG. 11 is a sectional view showing a conventional method for manufacturing a semiconductor device.

【図12】従来の半導体装置の製造方法を示す断面図FIG. 12 is a sectional view showing a conventional method for manufacturing a semiconductor device.

【図13】従来の半導体装置の製造方法を示す断面図FIG. 13 is a sectional view showing a conventional method for manufacturing a semiconductor device.

【図14】従来の半導体装置の課題示す平面図FIG. 14 is a plan view showing a problem of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 突起電極 3 外部電極 4 キャリア基板 5 樹脂フィルム 6 位置認識マーク 7 凹部 8 キャリア基板 9 樹脂部 10 放熱性接着剤 11 放熱部材 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Protruding electrode 3 External electrode 4 Carrier board 5 Resin film 6 Position recognition mark 7 Depression 8 Carrier board 9 Resin part 10 Heat dissipation adhesive 11 Heat dissipation member

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 上面に段差部分が垂直な凹部と、前記凹
部内の面に配線電極を有し、底面に前記配線電極と基板
内部のビアホールにより接続された外部電極を有したキ
ャリア基板と、前記キャリア基板の前記凹部に載置さ
れ、前記配線電極とその主面の電極パッドとが突起電極
を介して接続された半導体素子と、前記半導体素子と前
記キャリア基板の凹部との間に設けられた樹脂部と、前
記キャリア基板の上面の前記凹部の対角部近傍に設けら
れた位置認識マークとよりなることを特徴とする半導体
装置。
A carrier substrate having a concave portion having a vertical step portion on an upper surface, a wiring electrode on a surface in the concave portion, and an external electrode on a bottom surface connected to the wiring electrode by a via hole in the substrate; A semiconductor element mounted on the concave portion of the carrier substrate, wherein the wiring electrode and an electrode pad on the main surface thereof are connected via a protruding electrode; and a semiconductor element is provided between the semiconductor element and the concave portion of the carrier substrate. And a position recognition mark provided near a diagonal portion of the recess on the upper surface of the carrier substrate.
【請求項2】 半導体素子の面とキャリア基板上面との
間に放熱性接着剤を介して放熱板が設けられていること
を特徴とする請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein a heat radiating plate is provided between the surface of the semiconductor element and the upper surface of the carrier substrate via a heat radiating adhesive.
【請求項3】 半導体素子の電極パッド上に突起電極を
形成する工程と、上面に段差部分が垂直な凹部と、前記
凹部内に前記半導体素子の電極パッドと対応した電極
と、底面に前記電極と基板内部のビアホールにより接続
された外部電極と、基板上面の前記凹部の対角部近傍に
設けられた位置認識マークとを有したキャリア基板とを
用意する工程と、前記キャリア基板の凹部に前記凹部の
底面積と同等面積を有した樹脂フィルムを載置する工程
と、前記半導体素子の前記突起電極が形成された面を樹
脂フィルムが載置された前記キャリア基板の凹部に対し
て前記位置認識マークによって位置合わせする工程と、
前記半導体素子の前記突起電極が形成された面を樹脂フ
ィルムが載置された前記キャリア基板の凹部に対して押
圧し、前記半導体素子の前記突起電極と前記キャリア基
板の上面の電極とを接続する工程とよるなることを特徴
とする半導体装置の製造方法。
Forming a protruding electrode on the electrode pad of the semiconductor device, a concave portion having a vertical step on the upper surface, an electrode corresponding to the electrode pad of the semiconductor device in the concave portion, and the electrode on the bottom surface. Preparing a carrier substrate having an external electrode connected by a via hole inside the substrate and a position recognition mark provided near a diagonal portion of the recess on the upper surface of the substrate; and Mounting a resin film having an area equal to the bottom area of the concave portion, and recognizing the position of the surface of the semiconductor element on which the protruding electrode is formed with respect to the concave portion of the carrier substrate on which the resin film is mounted. Aligning with the mark;
The surface of the semiconductor element on which the protruding electrodes are formed is pressed against a concave portion of the carrier substrate on which a resin film is mounted, and the protruding electrodes of the semiconductor element are connected to the electrodes on the upper surface of the carrier substrate. A method of manufacturing a semiconductor device, comprising the steps of:
【請求項4】 半導体素子の突起電極が形成された面を
樹脂フィルムが載置されたキャリア基板の凹部に対して
押圧し、前記半導体素子の前記突起電極と前記キャリア
基板の上面の電極とを接続する工程は、加熱状況下で行
うことを特徴とする請求項3に記載の半導体装置の製造
方法。
4. A surface of the semiconductor element on which the projecting electrodes are formed is pressed against a concave portion of the carrier substrate on which the resin film is mounted, and the projecting electrodes of the semiconductor element and the electrodes on the upper surface of the carrier substrate are contacted. 4. The method according to claim 3, wherein the connecting step is performed under a heating condition.
JP18875799A 1999-07-02 1999-07-02 Semiconductor device and manufacture thereof Pending JP2001015557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18875799A JP2001015557A (en) 1999-07-02 1999-07-02 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18875799A JP2001015557A (en) 1999-07-02 1999-07-02 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JP2001015557A true JP2001015557A (en) 2001-01-19

Family

ID=16229248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18875799A Pending JP2001015557A (en) 1999-07-02 1999-07-02 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JP2001015557A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100341124C (en) * 2005-03-10 2007-10-03 威盛电子股份有限公司 Package process of chip built-in type
JP2012511814A (en) * 2008-12-13 2012-05-24 ミュールバウアー アーゲー Method and apparatus for manufacturing electronic assembly and electronic assembly thereof
US8405194B2 (en) 2009-06-30 2013-03-26 Denso Corporation Semiconductor device including two heat sinks and method of manufacturing the same
JP2018093007A (en) * 2016-12-01 2018-06-14 富士通株式会社 Optical module and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100341124C (en) * 2005-03-10 2007-10-03 威盛电子股份有限公司 Package process of chip built-in type
JP2012511814A (en) * 2008-12-13 2012-05-24 ミュールバウアー アーゲー Method and apparatus for manufacturing electronic assembly and electronic assembly thereof
US8405194B2 (en) 2009-06-30 2013-03-26 Denso Corporation Semiconductor device including two heat sinks and method of manufacturing the same
JP2018093007A (en) * 2016-12-01 2018-06-14 富士通株式会社 Optical module and manufacturing method thereof

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