JPH10326951A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatly grind a chip-loading surface for securing the coplanarity of an electrode group, without eliminating a mark for positioning or the like in a wiring board which is composed by readably providing the mark on a flip chip loading surface side. SOLUTION: A mark 121 is formed on an upper surface 112a of a ceramic layer 112 immediately below a ceramic layer 11 for forming the chip loading surface 102, so as to turn an upper surface 122 of a mark 121 to a level lower than that of a chip-loading surface 102. Then, an opening 123 is provided on the ceramic layer 111 of a highest layer, so as to read the mark 121 from the side of the flip chip loading surface 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip mounting wiring board for mounting and connecting electronic components such as ICs, and more particularly, to a flip-chip (hereinafter referred to as a flip-chip) having a large number of electrodes (external terminals) on one main surface. , Simply referred to as chips)
The present invention relates to a wiring board (hereinafter, also simply referred to as a substrate) formed mainly of an insulating material such as ceramic or resin for connection.

[0002]

2. Description of the Related Art FIGS. 6 and 7 show an example of a wiring board 101 for connecting a flip chip (shown by a two-dot chain line) 201. FIG. It is itself composed of a plurality of insulating layers 1
An electrode (not shown) of the chip 201 (hereinafter, a chip-side electrode is referred to as a bump) is formed on the upper surface of a flip-chip mounting surface (hereinafter, also referred to as a chip mounting surface) 102 on which the flip chip 201 is mounted. ) Are provided. Further, as shown in FIG.
02 has relatively large marks (also referred to as fiducial marks or alignment marks) 121 to 121 made of the same material as the electrode 103, for example, at three locations near the outer periphery of the substrate 101. It should be noted that one mark in the figure is composed of four parts 121a to 121a. This is used for correctly positioning and connecting the chip 201 in an assembling process, and for positioning (confirmation) when performing an underfill (resin filling) between the connection surface of the substrate 101 and the chip 201 thereafter. . In addition to the marks for positioning as described above, marks indicating the product number and direction of the wiring board may be formed.

A chip 201 is mounted on such a wiring board 101.
When mounting and connecting, the peripheries (positions) of these three positioning marks 121 to 121 are read, and the positions of the electrodes 103 and the solder bumps (not shown) formed thereon are determined based on the peripheries (positions). To detect. Then, the position of the chip 201 is corrected and positioned so that each bump of the chip 201 faces the detection position, mounted correctly on the wiring board 101, and the solder bumps are melted to join them.

When the wiring board 101 has, for example, a ceramic laminated structure, it has conventionally been manufactured as follows. That is, a via hole required for electrical conduction (for internal wiring) is formed in a predetermined ceramic green sheet, and a required metallizing paste is screen-printed on the hole and the sheet surface. At this time, in the production of the ceramic green sheet forming the chip mounting surface (uppermost layer) 102, a metallized paste for forming the mark 121 is used for capping the tip (electrode for pad) of the chip bonding electrode (pad). Perform screen printing at the same time as printing the metallizing paste.

Next, a metallized paste for the mark 121 and the electrode 103 is printed, and the chip mounting surface 10 is formed.
The second green sheet is printed on the uppermost layer, and a plurality of other green sheets on which internal wiring such as vias are printed are laminated and thermocompressed. Then, the substrate is cut and baked, and Ni
Perform a surface treatment such as (nickel) plating. As shown in FIG. 7, the wiring substrate 101 manufactured in this manner has electrodes 103 and marks 121 on its chip mounting surface 102.
Is formed in a protruding state by the thickness.

A chip 201 is mounted and connected to such a wiring board 101 in a later step, and the width of the variation (one end) allowed on the upper end face (tip face) of the electrode (group) 103 of the board 101 is determined. Flatness), that is, the chip mounting surface 102
At the upper end face of the electrode 103 at (co)
Planarity) requires a high degree of corporality to correspond to that of the upper end surface of the bump of the chip 201. However, in the manufacture of the ceramic substrate as described above, deformation such as warpage or undulation as shown by a two-dot chain line in FIG. 7 tends to occur during firing. The corporalities of the upper end surfaces of 103 to 103 are impaired. For this reason,
In the above-mentioned manufacturing method, it may be difficult to ensure high corporality on the upper end surface of the electrode (group). Therefore, such a request is conventionally made by re-firing before plating to correct the warpage and the like. (Fix) was forced to do.

[0007] However, by such correction, the electrode 10
The corporality obtained on the top face of 3 is at most 2
It is in the range of about 5 μm, and it is difficult to obtain a very high degree of coplanarity, for example, within 10 μm. Therefore, to meet such demands, after firing, the chip mounting surface 102 is polished to a flat surface and the chip mounting surface 1 is polished.
It is conceivable to obtain a high degree of coplanarity with respect to the upper end surface of the electrode (group) 103 while eliminating the warpage and the like by using the upper surface of the electrode 103 and the upper end surface of the electrode 103 as one plane.

[0008]

However, when trying to obtain a coplanarity of the upper end surface of the electrode 103 by such planar polishing, the thickness (metallized layer) of the mark 121 is extremely thin, usually about 10 μm. At this time, the mark 121 is simultaneously scraped off and disappears. Moreover, in this type of wiring board 101, the mark 1
Reference numeral 21 is formed on the chip mounting surface 102 at a position relatively near the outer periphery thereof. Therefore, the fired substrate 101
Is the chip mounting surface 102 as shown by the two-dot chain line in FIG.
Is curved so as to form a concave, the chip mounting surface is polished intensively without substantially polishing the chip mounting surface, and the mark is scraped off. As described above, in the wiring substrate 101 having the above structure, it is not possible to obtain the coplanarity of the upper end surface of the electrode (group) (hereinafter, also referred to as the coplanarity of the electrode) without erasing the mark by planar polishing.

Note that the substrate is fired without printing the metallizing paste for the mark, the warpage due to the firing is eliminated by polishing, the alignment is performed again, the capping of the upper end surface of the electrode is performed, and the metallizing paste for the mark is formed. Is also conceivable. However, this method is not only inefficient, but also difficult to secure a high corporate collaterality in the electrode because it is inefficient because re-firing eventually causes warpage.

The present invention has been devised in view of the above points, and an object of the present invention is to provide various marks used for positioning in flip chip connection and the like on the flip chip mounting surface side. In order to ensure the co-polarity of the electrodes, the wiring board is provided so that the mark can be removed, and the chip mounting surface can be polished without losing the mark. An object of the present invention is to provide a wiring board having a mounting surface polished in a plane.

[0011]

In order to solve the above-mentioned problems, the present invention provides a flip chip mounting surface provided with a large number of electrodes for flip chip connection, and a mark provided readable on the flip chip mounting surface side. In the wiring board, the mark is provided so as to be present below the flip chip mounting surface. In this specification, the “flip chip mounting surface” or the “chip mounting surface” refers to a main surface of the wiring board on which the flip chip is mounted (joined).

According to the above-described means, in the wiring board according to the present invention, the mark is provided so as to exist below the flip-chip mounting surface. For a predetermined amount. Therefore, the upper end surfaces of a large number of electrode groups existing on the chip mounting surface can have a high degree of corporate personality, similarly to the chip mounting surface. Note that, in the above means, "the mark is provided so as to be present below the flip chip mounting surface" is not limited to the case where the upper surface of the mark is below the flip chip mounting surface in the present invention. This is because even if the portion is above the flip chip mounting surface, the same effect can be obtained even when the lower part of the mark is provided with a thickness below the flip chip mounting surface. That is, even in this case, a predetermined amount of the flip chip mounting surface can be polished without losing the mark in a later step. In this specification, “polishing” means polishing or grinding.

The following configuration (structure) is preferred for a wiring board having an insulating material laminated structure such as a ceramic laminated structure or a resin laminated structure. That is, in the wiring board having the insulating material laminated structure, the flip-chip mounting surface is provided with a large number of electrodes for flip-chip connection, and the mark is readable on the flip-chip mounting surface side. The mark is formed on the upper surface of the insulating material layer below the insulating material layer forming the flip chip mounting surface so as to be lower than the flip chip mounting surface, and is formed above the insulating material layer on which the mark is formed. The mark is made readable by providing an opening for exposing the mark in the insulating material layer.

Also in this configuration, the flip chip mounting surface can be moved by a predetermined amount without erasing the mark in a later step.
Plane polishing can be performed. That is, since the upper surface of the mark is lower than the chip mounting surface, the upper surface of the uppermost insulating material layer forming the chip mounting surface can be polished (ground) by a predetermined amount without erasing the mark, There is no hindrance to reading the mark thereafter. Therefore, by setting an appropriate polishing allowance on the upper surface of the insulating material layer that forms the flip chip mounting surface, the upper end surface of a large number of electrode groups existing on the chip mounting surface has a high degree of cooperativeness like the chip mounting surface. I can do it. This allows
Even if the wiring substrate is, for example, a ceramic laminated structure product, and the chip mounting surface is warped so as to be concave by firing, the chip mounting surface can be polished without losing the mark. Therefore, even in such a substrate, a desired coplanarity can be obtained on the upper end surface of the electrode.

In the above-mentioned means, the mark is formed on the upper surface of the insulating material layer below the insulating material layer forming the chip mounting surface. In consideration of the thickness of the insulating material layer forming the surface, the thickness of the metallized layer forming the mark, and the like, the following configuration is more preferable. That is, in the wiring board having the insulating material laminated structure, the flip-chip mounting surface is provided with a large number of electrodes for flip-chip connection, and the mark is readable on the flip-chip mounting surface side. The mark is formed on the upper surface of the insulating material layer immediately below the insulating material layer forming the flip chip mounting surface so as to be lower than the flip chip mounting surface, and the insulating material layer forming the flip chip mounting surface is formed. The mark is formed to be readable by providing an opening for exposing the mark. In this specification, the “mark” includes a mark for positioning in flip-chip connection and the like, a variety of marks indicating a product number, a direction, and the like, but is not limited by its use.

For example, the degree of deformation (warpage or the like) during firing allowed on the main surface of the substrate having the ceramic laminated structure is 27
μm, so that the polishing allowance to be set to obtain the coplanarity of the chip mounting surface is 0.1 μm.
There is almost no problem if it is about mm. On the other hand, the thickness of the insulating material layer forming the chip mounting surface can be made relatively thick as about 0.3 mm, and the thickness of the metallized layer forming the mark is about 10 μm to ensure reading. This is because it may be extremely thin. Further, although the mark is exposed in the means, the mark in the means may be readable, so that the opening in each means may be filled with a transparent resin (for example, epoxy resin). Note that in this specification, “transparent” means that there is a degree of transparency that does not hinder the reading of the mark.

In the above-mentioned wiring board according to the present invention, when the flip chip mounting surface is planarly polished without erasing the mark, an extremely high level is provided on the upper end surface of the electrode together with the chip mounting surface. Corporality is ensured, and therefore, connectivity with the flip chip is improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a wiring board according to the present invention will be described in detail with reference to FIGS. However, in this example, a case in which the present invention is embodied in a wiring board having a multilayer structure including many ceramic layers will be described. In the figure, reference numeral 101 denotes a wiring board of the present example, which is formed in a rectangular flat plate shape, and although not shown in detail, a flip chip 201 to be mounted is mounted on a chip mounting surface 102, that is, a portion near the center of the upper surface (main surface) 102 of the substrate. A large number of electrodes (groups) 103 for connection to bumps (not shown) of the same chip 201 as in plan view (when the chip mounting surface 102 is viewed from above) so as to face each bump of the chip 201. The insulation is ensured with a suitable pitch and arrangement, and a large number of them are formed vertically and horizontally. However, the upper end surface of the electrode 103 (hereinafter also referred to as an electrode surface) is formed substantially flush with the upper surface of the ceramic layer 111 forming the uppermost layer of the substrate 101, that is, the chip mounting surface 102. The electrodes 103 to 103 are respectively connected to the ceramic layers 112 to 115 via vias 104 extending thereunder.
Connected to a number of internal wirings and vias formed on
It is connected to each electrode (not shown) for taking out the external wiring formed at 05.

The chip mounting surface 102 of the substrate 101
Marks (marks for positioning in this example) 121 having the same configuration (metallization layer) as the electrode 103 are formed independently at, for example, three places on the side near the outer periphery. However, in this example, each mark 121 is divided into four rectangular portions 121a in plan view, and a predetermined amount is provided on the upper surface 112a of the ceramic layer 112 immediately below the uppermost ceramic layer 111 forming the chip mounting surface 102. Of thickness Mt. The ceramic layer 112 forming the chip mounting surface 102 has the mark 1
At a position corresponding to 21, a window-like opening 123 which is substantially square and is larger than the mark 121 is provided in a plan view so that the entire mark 121 is exposed. Thus, mark 1
21 is formed so as to be read from the chip mounting surface 102 side.

The thickness of one ceramic layer forming the wiring board 101 of this embodiment is about 0.1 to 0.3 mm, and the thickness Mt of the mark 121 formed by printing and simultaneously firing a metallized paste. Is 10 μm in this example. Therefore, the mark 121 in this example is provided such that the upper surface 122 thereof is lower than the chip mounting surface 102 formed by the upper surface of the uppermost ceramic layer 111 by the thickness of the ceramic layer 111 substantially. . Incidentally, in this example, the thickness of the uppermost ceramic layer 111 after firing is set to, for example, 0.25 mm, and a plane polishing allowance K, for example, of 0.1 mm is provided on the upper surface side.

The wiring board 1 of the present embodiment thus configured
01 indicates that the chip mounting surface 102 has its polishing allowance (0.1 m
m) Planar polishing can be performed in a subsequent step for K minutes. When the polishing amount K is polished, the electrode surface 103 also becomes the chip mounting surface 10.
At the same time, the upper surface of the group of the electrodes 103 is finished to be flush with the chip mounting surface 102 with a high degree of co-porousity according to the polishing accuracy. On the other hand, even if the mark 121 is polished in this manner, the mark 121 does not disappear because it is formed on the upper surface 112a of the second ceramic layer 112 from the top with a thickness of about 10 μm. Therefore, as will be described later, plating is performed in a later step, and this mark 121 is also used for positioning in subsequent flip chip connection or the like.
The reading of the data is not impaired.

As described above, in the wiring substrate 101 of the present embodiment, after firing, the chip mounting surface 102 can be polished by the polishing allowance K without erasing the mark 121, so that the electrode surface (group) 103 is baked. And the desired corporate collaborativeness can be secured. In addition, the polishing allowance K is appropriately determined according to the wiring board 101 so that the chip mounting surface 102 is cut off so as to take into account the deformation such as warpage, so that the entire electrode surface group is simultaneously polished. Just set it. Further, in this example, the mark 121 is provided thin so that the upper surface 122 thereof is lower than the chip mounting surface 102 even after the planar polishing, but the upper surface is polished at the time of the planar polishing, and the mark 121 is formed with the chip mounting surface 102 after the planar polishing. It is also possible to make it sufficiently thick so as to be flush.

The wiring substrate 1 thus polished in the plane as described above.
Thereafter, Ni plating and Au are applied to the metallized layer such as the upper end surface of the electrode 103 and the surface of the mark 121 as in the conventional case.
Plating. Then, the electrode surface is slightly raised from the chip mounting surface 102 by the plating thickness. The wiring board (finished product) 101 thus formed is mounted on its chip mounting surface 1.
02, the upper end surfaces of the electrodes (groups) 103 to 103 are planar-polished, so that the coplanarity is extremely high as compared with the coplanarity obtained by refiring like a conventional wiring board having a ceramic laminated structure. Wiring board 101 having the above-mentioned electrodes. Note that solder bumps are formed on each of the electrodes 103 in some cases.

Further, in the wiring substrate 101 having the ceramic laminated structure as in the present embodiment, in the production of the uppermost green sheet, a step of printing a metallized paste for capping the upper end surface of the via as in the conventional wiring substrate is performed. No need. That is, in this type of conventional wiring board, a capping process is required as a hole filling process to prevent the upper end surface (exposed front end surface) of the via from being dented and to prevent the occurrence of voids at the time of solder bonding with the bump of the chip. Was.
However, in the wiring board 101 of this example, the chip mounting surface 102
Is planarly polished and the upper end surface of the electrode 103 is also planarly polished, so that capping is not required. Further, in the case of the ceramic laminated structure like the wiring board 101 of the present example, dirt and foreign matter due to poor printing or firing of the metallized paste are simultaneously removed by planar polishing.
Therefore, the appearance defect of the chip mounting surface 102 is reduced, and the quality is expected to be improved accordingly.

Next, a method of manufacturing the above-described wiring board 101 having a ceramic laminated structure will be described with reference to FIG. 4, but this is basically the same as a conventionally known method of manufacturing a wiring board having a ceramic laminated structure. Only the differences (different steps) will be described. That is, the ceramic layer 11 immediately below the ceramic layer 111 forming the chip mounting surface 102
In the manufacture of the ceramic green sheet for forming the metallization 2, a metallized paste mainly composed of Mo (molybdenum) excellent in plating adherence is used as a mark metallized paste 121b at a planar position corresponding to the mark 121, Alternatively, a metallized paste containing W (tungsten) as a main component is screen-printed.

The ceramic mounting sheet 102, that is, the ceramic green sheet forming the uppermost ceramic layer 111, has a larger opening 123a at a planar position corresponding to the mark 121 so that the mark 121 is exposed. (A square in the previous example) is punched by punching or the like. The ceramic layer 111 forming the chip mounting surface 102 is formed of a green sheet having a thickness capable of holding a predetermined polishing allowance K. Then, like these green sheets for forming the other predetermined ceramic layers 113 to 115, a predetermined via hole is also printed and filled with a metallizing paste on these green sheets.

Thus, similarly to the conventional manufacturing method, a green sheet for forming the uppermost ceramic layer 111 and a green sheet for forming the ceramic layer 112 therebelow can be used.
A predetermined green sheet on which the metallized paste is printed is laminated and pressed, and then, for example, a metallized paste for a BGA electrode is printed on the back surface, and then cut into substrate units.
Then, by sintering in the same manner as in the related art, the flip-chip wiring substrate having the above-described marked ceramic laminated structure is manufactured.

FIG. 5 shows another embodiment.
Since there is basically no difference from the previous example, the same portions are denoted by the same reference numerals, and only different points will be described. That is, in this drawing, the mark 121 is formed on the upper surface 113a of the insulating material layer 113 which is one layer lower than the previous example, and the two insulating material layers 111, 112 is provided with an opening 123. In this case, the upper surface 122 of the mark 121 is lower than the previous example by the thickness of the second insulating layer 112 from the top.

In the present invention, the position of the mark (depth position) in the thickness direction of the substrate and the thickness of the mark itself are polished for each substrate in order to obtain the required coplanarity on the electrode surface. In consideration of the cost, it may be appropriately set within a range that does not disappear even if the surface polishing is performed. The polishing allowance may be set so that the warpage is eliminated by polishing, while taking into account the maximum allowable value of the warp given to the substrate.

In each of the above examples, the opening for exposing the mark is substantially square. However, the planar shape and size may be set according to the planar shape of the wiring board or the mark so as not to hinder reading. Good. The opening may be filled with a transparent resin as long as the reading of the mark is not hindered. That is, in the present invention, the mark is provided so as to be present below the chip mounting surface so that the mark does not disappear when the chip mounting surface is planarly polished, and can be read without any problem, for example, when connecting the chip. It just needs to be done.

In the above description, the description has been given of the wiring board having the ceramic laminated structure. However, the present invention can be similarly embodied also in the wiring board having the resin laminated structure. This is because, even in a multilayer wiring board having a resin laminated structure, deformation such as warpage occurs in the manufacturing process, and there is a similar problem to be solved. INDUSTRIAL APPLICABILITY The present invention can be widely applied to various types of flip-chip connection wiring boards such as BGA (ball grid array) and PGA (pin grid array).

[0032]

As is apparent from the above description, according to the wiring board of the present invention, the flip chip mounting surface can be polished by a predetermined amount without losing the mark in a later step. In other words, according to the wiring board of the present invention as set forth in claim 1, by setting an appropriate polishing allowance on the chip mounting surface and providing the mark so as to be present below the flip chip mounting surface by an appropriate amount, the mark is provided. While attached
The chip mounting surface can be polished flat without losing it. Therefore, the upper end surfaces of a large number of electrode groups existing on the chip mounting surface can have a high degree of corporate personality, similarly to the chip mounting surface.

Also, in the wiring board according to the present invention as set forth in claims 2 to 4, by setting an appropriate polishing allowance on the upper surface of the insulating material layer forming the flip chip mounting surface, the wiring board can be provided with the positioning mark. The chip mounting surface can be polished flat without losing it. Therefore, even in such a substrate, the upper end surfaces of a large number of electrode groups existing on the chip mounting surface can have a high degree of coplanarity similarly to the chip mounting surface.

According to the wiring substrate of the present invention, since the flip chip mounting surface is polished flat, a high degree of coplanarity is imparted to the electrode surface for bonding with the flip chip bump. Wiring board. Therefore, the reliability of connection with the bumps of the chip can be improved.

[Brief description of the drawings]

FIG. 1 is a partially cutaway side view of an embodiment of a wiring board according to the present invention.

FIG. 2 is an enlarged sectional view of a main part of FIG.

FIG. 3 is a plan view and a partially enlarged view of an embodiment of a wiring board according to the present invention.

FIG. 4 is a diagram illustrating a method of manufacturing the wiring board of FIG.

FIG. 5 is an enlarged sectional view of a main part showing another embodiment.

FIG. 6 is a plan view of a conventional wiring board.

FIG. 7 is a side view of a conventional wiring board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Wiring board 102 Chip mounting surface of wiring board 103 Electrode 111-115 Ceramic layer (insulating material layer) 121 Mark 122 Top surface of mark 123 Opening 201 Flip chip

Claims (5)

[Claims] 1. A wiring board comprising: a plurality of electrodes for flip-chip connection on a flip-chip mounting surface; and a mark readable on the flip-chip mounting surface. A wiring board, which is provided so as to exist below. 2. A wiring substrate having an insulating material laminated structure, comprising: a plurality of electrodes for flip-chip connection on a flip-chip mounting surface; and a mark readable on the flip-chip mounting surface. The mark is formed on the upper surface of the insulating material layer below the insulating material layer forming the flip chip mounting surface so that the upper surface is lower than the flip chip mounting surface, and the insulating material on which the mark is formed is formed. A wiring substrate, characterized in that an opening for exposing the mark is provided in the insulating material layer above the layer, and the mark is formed to be readable. 3. A wiring board having an insulating material laminated structure, wherein a plurality of electrodes for flip-chip connection are provided on a flip-chip mounting surface and a mark is readable on the flip-chip mounting surface. The mark is formed on the upper surface of the insulating material layer immediately below the insulating layer forming the flip chip mounting surface, and the flip chip mounting surface is formed so that the upper surface is lower than the flip chip mounting surface. A wiring board, characterized in that an opening for exposing the mark is provided in the insulating material layer so that the mark can be read. 4. The wiring board according to claim 2, wherein the opening is filled with a transparent resin. 5. The wiring board according to claim 1, wherein the flip chip mounting surface is polished flat without erasing the mark.