JPH1164442A - Jig for electronic component chip inspection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a jig capable of performing the electric inspection by a flip chip single body before loading to a wiring board, without disturbing repetitive use in the performance inspection of a flip chip. SOLUTION: Many electrodes 3 for the inspection for bringing the connection terminal of an electronic component chip F into contact are formed on an insulation substrate and the electrodes 3 for the inspection are connected to the separately provided electrodes 7 through internal conductor wiring. Hard Cr plating for which hardness is about Hv500-1,000 is applied to a surface for the electrodes 3 for the inspection and this jig for the inspection is attained. It is connected through the separately provided electrodes 7 to a prescribed inspection device, and the bump of the chip F is positioned to the respective electrodes 3 for the inspection, brought into press-contact and conducted. Thus, the electric inspection is performed by the chip single body before loading to the wiring board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jig for inspecting an electronic component chip, and more particularly to a jig for inspecting an electronic component chip, which is provided with a large number of external connection terminals (hereinafter, also referred to as connection terminals or simply terminals) on one main plane, and adopts a flip chip method. For inspections used when performing performance inspections (hereinafter also referred to as electrical inspections) of electronic component chips (hereinafter also referred to as flip chips or chips) such as ICs mounted and connected to a wiring board such as an IC package. The present invention relates to a jig (hereinafter, also simply referred to as a jig).

[0002]

2. Description of the Related Art In a wire bonding type IC chip, the electrical inspection can be performed without any problem by simultaneously contacting or pressing a probe to all connection terminals of the chip. This is because the terminal has a flat surface so that wire bonding can be performed. Also, TAB (Tape
In the case of Autonated Bonding) type chip,
After bonding to the AB tape, electrical inspection of the chip can be performed using the test pattern formed on the TAB tape. As described above, a chip other than a flip chip can perform a performance test on a single chip. Therefore, with these chips, pass / fail (measurement results) are determined by the chip alone,
Only the accepted products (good chips) can be mounted on a wiring board such as an IC package (hereinafter, also simply referred to as a package or a wiring board).

On the other hand, the electrical inspection of a flip chip has conventionally been carried out after mounting the chip on a package and joining it. In a flip chip, external connection terminals (electrodes) provided on one principal plane form bumps, and a large number of these are arranged in a plane such as in a grid, so that a large number of bumps are collectively probed. This is because it is difficult to assemble the probe as one device. In this way, probing cannot be performed on a flip chip like other chips, and performance measurement (pass / fail judgment) cannot be performed on a single chip. Therefore, after mounting and bonding the chip on a package, the package is connected to the printed circuit board. For example, an electrical connection is ensured by pressing an external electrode for use with an electrode of a test board constituting an inspection apparatus, and an electrical inspection is performed underneath. According to the electrical inspection after the mounting, the inspection is of high quality, but has the following problems.

[0004]

That is, if it is determined that the package is defective after being mounted on a package, the package is discarded in addition to the defective chip. Therefore, there is a problem that the mounting process and the package are wasted. It is also conceivable that the package is collected by removing the defective chip by re-flowing to remove the defective chip, and another chip is mounted on the collected package. However, this requires time and effort to remove the defective chip from the package by reflowing, and residues such as solder and gold from the previous bonding remain on the package pads. This also causes a reduction in the reliability of the device. In addition, if the defect determination is repeated, not only the mounting, bonding and removal of the chip need to be repeated, but such a problem becomes more remarkable.

On the other hand, in order to solve such a problem,
Use the same jig as the wiring board on which the chip to be inspected is mounted as a jig, and secure the continuity by abutting or pressing the terminals of the chip against the terminals of the wiring board without soldering. It is conceivable to perform an electrical test on the chip. However, for example, in the case of a ceramic package, its terminals are made of thick film metallized, and its surface is usually coated with soft Ni plating and soft Au plating, and its hardness is Hv (Vickers hardness) 50.
It is as low as about 200.

If the terminal of the chip is repeatedly contacted or pressed against the terminal on which such low-hardness soft plating is applied, the surface layer (plating) of the terminal is worn out early, and a small number of chips (several tens of There is a high risk that a conduction failure may occur at the stage of inspection of about several to several hundred pieces. On the other hand, the number of chips produced per month is on the order of one million. Therefore, in order to use the package itself as an inspection jig, it must be replaced frequently in the inspection process so as not to reduce the reliability of the inspection, but this will increase the cost and decrease the inspection efficiency. This is obvious and cannot be put to practical use.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the performance inspection of flip chips, and an object of the present invention is to provide an electronic inspection of a large number of chips without hindrance to mounting on a wiring board. An object of the present invention is to provide an electronic component chip inspection jig (hereinafter, also simply referred to as a jig) suitable for conducting an electrical inspection of a flip chip alone.

[0008]

In order to achieve the above object, an electronic component chip inspection jig according to the present invention comprises an inspection electrode for contacting a connection terminal of an electronic component chip for electrical inspection. A large number of electrodes are formed on one main plane while securing insulation, and each of the inspection electrodes is connected to another electrode via an internal conductor wiring. Hardness (Vickers hardness) is Hv on the surface
It is that hard plating of 500 or more is applied.
And here, for hard plating, hard Cr, hard Au,
Palladium and rhodium plating are exemplified.

In the above-mentioned inspection jig, the separate electrode is connected to each terminal of a test board constituting the chip inspection device by soldering or the like, and incorporated into the inspection device to constitute the electronic component chip inspection device. I do. Then, the position of each connection terminal (solder bump or the like) of the flip chip to be inspected is aligned with the inspection electrode of the jig so that the electrode and the terminal are pressed against each other with a predetermined force. In this way, the connection terminals of the chip and the test electrodes of the jig are brought into conduction,
The required electrical inspection can be performed on the flip chip.

Then, Hv500 is applied to the surface of the inspection electrode.
Hard plating of high hardness as described above is applied. On the other hand, the connection terminals of the chip are solder bumps, Au bumps, and the like, and the hardness thereof is at most Hv50 or less. Due to such a difference in hardness, even when a large number of chips are inspected and their connection terminals (eg, solder bumps) repeatedly contact the corresponding test electrodes of the jig, the test electrodes are substantially worn. No or trace. As a result, the jig according to the present invention can be used for inspection of a large number of chips of several tens of thousands without any practical problem.

Thus, according to the inspection jig of the present invention, various electrical inspections can be performed on a flip chip by itself. In addition, the jig according to the present invention can be constituted by substantially the same as the package on which the chip is mounted, and can be constituted (manufactured) by applying hard plating to its connection terminals, so that the jig itself can be easily manufactured. It is. Further, since the electrical inspection can be performed under exactly the same conditions as when the chip is mounted on a package, the quality of the inspection can be improved as in the related art.

In the above means, the inspection electrode is provided on one main plane of the insulating substrate, and the separate electrode (inter-interval) is provided on the other main plane of the insulating substrate. It is preferable that they are provided at intervals larger than the interval between the electrodes for use. This is because connection from the separately provided electrode to various inspection devices becomes easy.

The insulating substrate is a ceramic substrate,
Preferably, the surface forming the one main plane is flattened by polishing. This is because the connection can be made more reliable because the polishing can be flattened with high precision. Although it depends on the size of the substrate, the flatness is preferably 10 μm or less, and the surface roughness Ra is preferably 0.8 μm or less. In particular, the ceramic substrate is preferably a ceramic multilayer wiring substrate.
This is because the internal conductor wiring (also referred to as internal wiring) can be routed and taken out to another electrode for easy inspection in the substrate.

Further, in the above jig, a mark (a hole or a metallized layer) for positioning the chip may be formed on one main plane on which the inspection electrode is provided. If such a mark is provided, by reading the mark, the terminal of the chip can be positioned with respect to the test electrode of the jig, and thus the positioning can be performed in the same manner as when mounting the chip. In addition, it is appropriate that such a mark is provided in three or more places on the one main plane side of the jig where the inspection electrode is provided, near the outer periphery thereof.

[0015] In any of the above jigs, it is preferable that one end is provided with a through hole which is opened at a position near the center of the group of inspection electrodes on the one main plane. With this configuration, the electronic component chip is positioned at the time of inspection, and the chip can be sucked by evacuating from the opening at the other end of the through hole under the chip, thereby preventing movement of the chip during inspection. This is because fixing can be easily performed. In the through hole, when the jig is made of an insulating substrate, the opening at the other end is preferably a main plane opposite to the main plane on which the inspection electrode is provided. The opening position may be appropriately set according to the structure of the jig.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described.
This will be described in detail with reference to FIGS. 1 to 3
1 shows an embodiment of the jig 1 according to the present invention. This jig 1 is an LG on which a flip chip is mounted.
It has the same plate shape and laminated structure as the A type ceramic wiring board, and is configured as follows. However, in this example, as will be described in detail later, it is made by co-firing mainly alumina ceramic.

That is, in the jig 1 of this embodiment, the upper flat surface (one main plane) 2 is a mounting surface of the flip chip F to be inspected as shown in FIG. Insulation is ensured at the same fine pitch P1 and arrangement so that the inspection electrodes 3 and 3 face the respective connection terminals of the same chip F in plan view, and are vertically and horizontally placed on the surface 2 of the jig 1. Many are formed. The inspection electrode (group) 3 is connected to a lower surface (lower surface) 6 of the jig 1 via a via 4 mainly composed of a refractory metal such as W (tungsten) or Mo (molybdenum) and an internal conductor wiring 5. And are connected to separate electrodes 7 for connection of inspection devices, which are arranged at an interval P2 larger than the interval (pitch) P1 between the inspection electrodes 3. If the interval P2 between the electrodes 7, 7 is increased as in this example, connection and wiring become easier when the jig 1 is used in an inspection device for inspecting various electrical characteristics.

The jig 1 of this embodiment is formed by laminating and sintering a plurality of ceramic layers 11 to 14 (see FIG. 2), and as shown in FIG. An inspection electrode 3 formed at the upper end of each via 4 is formed on the upper surface 11 a of the ceramic layer 11. That is,
Although a detailed manufacturing method will be described later, in this example, the upper surface 11a of the uppermost ceramic layer 11 has a predetermined flatness (about 10 μm),
After being baked so as to have a surface roughness (Ra: 0.5 μm), the surface is polished, and an inspection electrode 3 having a predetermined planar shape (circular in this example) and a flat thickness is formed on each upper surface 11 a of each via 4. Have.

The outer diameter D1 of the inspection electrode 3 is, for example, 120 μm, and is set to be substantially the same as the diameter of the base end of the solder bump (terminal) T of the chip F to be inspected.
In addition, the inspection electrode 3 is formed as described later, and in this example, hard Cr plating is applied to the outermost surface in a thickness of 1 to 10 μm in this example, and the hardness is secured to Hv 500 to 1000. The thickness of the inspection electrode 3 (the upper surface 3 of the inspection electrode 3)
a to the upper surface 11a of the ceramic layer 11) is 5
It is set to about 20 μm.

A chip mounting area E indicated by a two-dot chain line in FIG. 1 where the chip F is mounted and overlapped is located near the center of the surface 2 of the jig 1 in the thickness direction of the jig 1. Two through holes 8 are provided (FIGS. 1 and 2).
reference). However, the diameter is about 1 to 2 mm. Further, in this example, a plurality of positioning marks (fiducial marks) 9 made of the same material as that of the inspection electrode 3 are provided on the surface 2 on which the flip chip is mounted (four locations in this example) at a position near the outer periphery of the surface 2. Is provided. As described above, the jig 1 of the present example is almost the same in material and structure as the ceramic LGA wiring board, except for the presence of the through holes 8 and the hard plating on the outermost surface of the inspection electrode 3. .

When a chip is inspected using the jig 1 of this embodiment, the external electrodes 7 of the jig 1 are connected to a predetermined test board 201 as shown in FIG. And a predetermined chip inspection device 210 including a relay 202, a semiconductor parameter analyzer 203, a controller 204, and the like.
The required electrical inspection can be performed by setting the flip chip F to be inspected on the jig 1 thereunder. In this example, the chip F mounted and set on the surface 2 of the jig 1 is evacuated through the through hole 8 as shown by an arrow V in FIG. As shown in the drawing, a suction pipe K is formed in the test board 201 at a position corresponding to the through hole 8. A seal (not shown) is interposed between the test board 201 and the outer peripheral portion of the lower surface 6 of the jig 1 to maintain airtightness.

In mounting the chip F on the jig 1 by assembling the jig 1 into the inspection apparatus as described above, the position of the four positioning marks 9 of the jig 1 is set. Is read. Based on this reading, the position of each test electrode 3 is detected, and the position of the chip F is corrected so that each bump T of the chip F faces the detected position, and is correctly set on the surface 2 of the jig 1 ( Mounting) so that each bump T comes into contact with the inspection electrode 3. Next, the chip F is evacuated through the through hole 8 as shown by an arrow V.
Then, the chip F is attracted to the jig 1 with a predetermined force P, and the tops (tips) of all the bumps T of the chip F are pressed against the respective test electrodes 3. Thus, conduction between the solder bump T of the chip F and the inspection electrode 3 of the jig 1 is ensured. As a result, the electrical inspection of the chip F is performed by a wire bonding type or a TA.
Like the B type, it can be performed alone before mounting on the wiring board via the jig 1 of this example.

At this time, in the jig 1 of the present embodiment, the surface of the inspection electrode 3 is coated with a hard Cr plating having a high hardness of 500 to 1000 Hv. A large number of individual chips can be inspected without any problem. In other words, the jig 1 of the present embodiment enables probing with the bump T without causing wear of the inspection electrode 3, so that an electrical inspection using a chip alone, which could not be realized conventionally, becomes possible. Dramatic improvement is achieved. In addition, since the jig 1 of the present embodiment can be formed by using the same package as the package on which the chip F is mounted and by performing additional processing, the electric jig 1 under the same conditions as when the chip is actually mounted is used. Inspection can be realized at low cost.

In this test, the top of the solder bump T of the chip F is slightly compressed and deformed by evacuation. However, as shown in FIG. Having a predetermined thickness Ta slightly smaller than the allowable minimum height of the solder bump T (or the height obtained by adding the allowable minimum height and the thickness of the inspection electrode 3) between the chip 2 and the chip F. A holding member (gap holding means) G may be interposed. That is, if the gap between the surface 2 of the jig 1 and the chip F is kept constant through such a gap holding member G, the chip F is placed (set) on the jig 1.
Even when the top of the bump T is compressed and deformed, the height of the bump is maintained by the presence of the gap holding member G.
It is prevented that the thickness becomes smaller than Ta. Incidentally, the deformation of the solder bump is appropriately in the range of 2 to 50% of its height. If the deformation is smaller than 2%, the contact pressure between the bump and the test electrode is reduced, and the contact resistance between the two is likely to be unstable. If it exceeds 50%, the deformation (crushing) is large, and the post-process is required. This is because there is a problem in connection with the package at the time.

In this embodiment, the jig 1 is provided with a through-hole 8 in order to secure electrical conduction between the inspection electrode 3 and the bump T, and the chip F is placed on the surface 2 of the jig 1 through the through-hole 8. Although suction and fixation are performed by evacuation, such a through hole 8 is not essential in the jig according to the present invention. That is, the electrical continuity can be ensured also by the weight of the chip F and the weight placed on the chip F. Further, in this embodiment, the positioning mark 9 is formed on the front surface 2 of the jig 1 in order to position the bump T of the chip F with respect to the inspection electrode 3 of the jig 1. Such a positioning mark 9 is not essential. Such positioning is performed so long as the bumps T of the chip properly correspond to the test electrodes 3 of the jig 1, and other appropriate means can be used. For example, a guide member (not shown) may be provided upright so as to circumscribe the chip mounting area E, and the chip may be positioned so that the side edge of the chip is inscribed therein.

Next, an example of a method of manufacturing such a jig 1 will be described. First, a ceramic substrate 10 as shown in FIG. 6 is manufactured in the same manner as in the case of manufacturing a ceramic laminated type LGA wiring substrate. A via hole is provided in a green sheet containing alumina as a main component, including the positions of test electrodes, filled with metallized ink containing tungsten and molybdenum as a main component, an electric circuit pattern is formed by a screen printing method, and further, a vacuum quote A through hole. A predetermined number of the green sheets subjected to the above processing are stacked and laminated. Then, the metallized ink is applied to the position of the electrode 7 on the lower surface 6 and then fired simultaneously at a predetermined temperature in a reducing atmosphere. Thus, a ceramic substrate 10 having the vias 4 for the inspection electrodes and the internal wiring 5 as shown in FIG. Since the ceramic substrate 10 is a multi-layer wiring substrate, it is easy to route the internal wiring 5, and the spacing P2
Can be easily connected to the electrode 7 for the inspection device whose size has been increased.

Next, a method of forming the inspection electrodes 3 and the positioning marks 9 on such a substrate 10 will be described. However, they differ in that the inspection electrode 3 is formed at the upper end of the via 4, whereas the positioning mark 9 is formed on the surface of the substrate 10 near the outer periphery irrespective of such a via. Except for the above, since they have the same cross-sectional structure and can be formed in the same process, only the formation of the inspection electrode will be described below. That is, as shown in FIG. 7A, the flatness (for example, 10 μm) and the surface roughness (Ra: 0.5 μm) required for the surface 11a of the uppermost ceramic layer 11 of the substrate 10 on which the inspection electrode is formed are required. Then, the end surface 4a of the via 4 is exposed on the substrate surface 11a. Ceramic substrate 1 formed by firing
0 is often slightly warped and has undulation, but the surface 11a of the ceramic substrate 10 is polished to be a flat surface, so that the inspection electrode can be formed on a flat surface having a high degree of flatness, and the bumps of the chip can be formed. Has good connectivity.

Thereafter, as shown in FIG. 7-B, Ti having good adhesion to the ceramic substrate 10 is sputtered to a thickness of about 0.2 μm on the entire surface 11a, and Cu is reduced to 0 μm. A Ti layer 51 and a Cu layer 52 are formed by sputtering to a thickness of about 0.5 μm. Next, a resist (photosensitive resin) 53 is applied thereon (see FIG. 7-C), and is exposed and developed to open an inspection electrode formation portion (see FIG. 7-D). At this time, the position for forming the positioning mark is also opened.

Next, Cu plating is applied to a thickness of 3 μm and Ni plating is applied to a thickness of about 1 μm on the inspection electrode portion (and the positioning mark portion) to form a Cu layer 54 and a Ni layer 55. Hardness (for example, Hv 500 to 1000)
And a Cr layer 56 is formed on the outermost surface as a hard plating layer.
E). Then, the resist 53 is peeled and removed (see FIG. 7F). Further, the Ti layer 5 on the substrate surface 11a
1. When the Cu layer 52 is removed by etching with a predetermined etching solution, as shown in FIG.
In this case, an inspection electrode (pad) 3 and a positioning mark (not shown) formed of each layer of Ti, Cu, Cu, Ni and hard Cr are formed.

In the above embodiment, when such a positioning mark is not provided and the required area (diameter) of the inspection electrode 3 is small, the substrate surface 11a is not used by such a method. The exposed via 4
The end surface 4a may be subjected to Ni plating directly after polishing of the surface 11a or without polishing, and hard Cr plating may be applied thereon to form an inspection electrode in which the surface is hard plated.

Incidentally, in the case where the Ni 4 plating or the hard Cr plating is directly applied to the end face 4a of the via 4 as described above, it is preferable to provide the positioning mark as follows. That is, when the substrate surface 11a is not polished, a metallizing paste for a positioning mark is printed on the upper surface of the green sheet forming the uppermost ceramic layer, and after the simultaneous firing, the same mark is simultaneously printed on the same mark as the inspection electrode. It is plated. Also, the substrate surface 11a
When polishing, the upper surface of the positioning mark is
0 so that the surface 11a is lower than the surface 11a.
Is printed on the upper surface of the ceramic layer (green sheet) below the ceramic layer 11 forming the mark, and the mark is exposed on the ceramic layer above the ceramic layer on which the mark is formed. An opening is provided, and lamination and firing are performed.
This is because the metallization for the mark does not disappear even if it is polished.

In the above embodiment, the hard Cr plating is applied as the hard plating on the surface of the inspection electrode 3, but the hard plating in the present invention is not limited to this. That is, Hv 500 or more is sufficient as long as the electrodes for inspection are not worn even when a large number of chips are inspected. In addition, each plating of palladium, rhodium, and hard Au is exemplified as a typical example. In addition, such hard plating may be applied after Ni plating in FIG. 7-E, then the resist 53 may be peeled off, and the Cu layer 52 and the Ti layer 51 on the surface may be removed by etching, but it is not limited thereto. Not something. When the insulating material forming the jig is resin and the inspection electrode is Cu, Ni plating and hard Cr plating may be applied thereon, or the base of the inspection electrode (C
u) may be directly plated with hard Cr. In addition,
Needless to say, a plurality of such hard platings may be applied. The thickness of the hard plating is preferably as large as possible, but may be appropriately set according to the type and hardness of the plating or the required wear resistance.

In the above description, a jig for inspecting a flip chip on which solder bumps are formed as connection terminals has been described. However, it can be obviously used as a jig for inspecting a chip on which Au bumps are formed. .
Since the shape and size of the bumps vary depending on the type and formation method of the bumps, the pitch and size of the test electrodes may be appropriately designed so that those of the bumps correspond properly.

In the above description, the material and structure of the jig are flat plates having the same ceramic multilayer wiring layer structure as that of the LGA wiring board. However, in the jig according to the present invention, the material, structure or shape is It is not limited to the above. It can be embodied as a material having an appropriate structure and shape using an appropriate insulating material (for example, resin) other than ceramic.
An appropriate material and structure may be selected so as to ensure required flatness and surface roughness. Further, the planar shape of the inspection electrode is not limited to a circle.

Further, an electrode for connecting a separate inspection device for connection with the inspection device in the jig is formed on the main plane opposite to the mounting surface of the chip to be inspected. Even when the jig has a flat plate shape, it can be led out to the side surface, and if the jig itself is made sufficiently large, it may be formed on the same surface as the inspection electrode formation surface. May be appropriately designed according to the test board of the inspection apparatus to which the jig is connected. And the form of the electrode for connection with the inspection device is LG
The electrodes (pads) were the same as those of the A-wiring board, but pins were soldered to such electrodes to have a structure similar to that of a PGA (pin grid array) wiring board, and a test board or the like for the inspection apparatus was used. The connection may be of a plug-in type.

In the above description, as an example of a flip chip inspection apparatus using the jig of the present invention, an apparatus for performing an inspection using a semiconductor parameter analyzer is illustrated. However, the jig of the present invention may be used for other apparatuses. Can be. Inspection of various electrical characteristics and logical operation of flip chip, etc.
Any device can be used as long as it is a device that electrically inspects the characteristics of a flip chip alone via bumps. The present invention is not limited to the above embodiment, and can be implemented with various design changes without departing from the spirit of the invention.

[0037]

As is apparent from the above description, the jig for inspecting electronic component chips according to the present invention does not hinder the electrical inspection of many chips. In addition, the electrical inspection can be performed on the flip chip alone before mounting on the wiring board. Therefore, while the inspection efficiency is significantly improved,
With the improvement of the package yield, the waste of the chip mounting process is eliminated, and the reliability of the IC device is expected to be improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration perspective view of an embodiment of an electronic component chip inspection jig according to the present invention.

FIG. 2 is an enlarged sectional view of FIG.

FIG. 3 is an enlarged view of a portion A in FIG. 2;

FIG. 4 is an explanatory view of a flip chip inspection apparatus using the electronic component chip inspection jig of FIGS.

FIG. 5 is a diagram in which a gap holding member is interposed between the surface of the jig and the chip.

FIG. 6 is a sectional view of a ceramic substrate forming the jig of FIG. 1;

FIG. 7 is a manufacturing process diagram of the jig of FIGS.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Jig for electronic component chip inspection 2 Surface (main plane) 3 Inspection electrode 4 Via 5 Internal conductor wiring 7 Separate electrode 8 Through hole 9 Positioning mark 10 Multilayer wiring substrate forming ceramic substrate 11a Surface of ceramic substrate F Flip chip T Flip chip solder bump (connection terminal) P1 Spacing between test electrodes P2 Spacing between separate electrodes

Claims (5)

[Claims] 1. A large number of test electrodes for contacting connection terminals thereof for performing an electric test of an electronic component chip are formed on one main plane while ensuring insulation. The test electrode is connected to a separate electrode via conductor wiring, and the surface of the test electrode has a hardness of Hv50.
A jig for inspecting an electronic component chip, wherein the jig is subjected to hard plating of 0 or more. 2. The inspection electrode is provided on one main plane of an insulating substrate, and the separate electrode is provided on the other main plane of the insulating substrate at a distance larger than a distance between the inspection electrodes. The electronic component chip inspection jig according to claim 1, wherein the jig is provided with: 3. The jig for inspecting an electronic component chip according to claim 2, wherein said insulating substrate comprises a ceramic multilayer wiring substrate. 4. The electronic component chip inspection device according to claim 1, wherein a positioning mark for the electronic component chip is formed on one principal plane on which the inspection electrode is provided. jig. 5. The device according to claim 1, wherein one end is provided with a through hole which is the one main plane and is opened at a position near the center of the test electrode group. Jig for electronic component chip inspection.