CN109545691B - Manufacturing method of ultrathin fan-out type packaging structure - Google Patents
Manufacturing method of ultrathin fan-out type packaging structure Download PDFInfo
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- CN109545691B CN109545691B CN201811366693.0A CN201811366693A CN109545691B CN 109545691 B CN109545691 B CN 109545691B CN 201811366693 A CN201811366693 A CN 201811366693A CN 109545691 B CN109545691 B CN 109545691B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4875—Connection or disconnection of other leads to or from bases or plates
Abstract
The invention discloses a manufacturing method of an ultrathin fan-out packaging structure, which comprises the following steps: temporarily bonding the copper foil to the carrier plate; forming an electroplating pattern on the upper surface of the copper foil by photoetching; electroplating to form a copper interconnection metal layer; removing the photoresist mask layer; forming a first dielectric layer on the outer surfaces of the copper foil and the copper interconnection metal layer, and photoetching to form a chip bonding pad opening; forming a first copper protective layer at the opening of the chip bonding pad; flip-chip bonding a chip to a chip bonding pad through a chip bonding structure; filling an underfill between the chip and the first dielectric layer; forming a plastic packaging layer; removing the carrier plate by detaching the key; etching to remove the copper foil; forming a second dielectric layer, and photoetching to form an external bonding pad opening; forming a second copper protective layer on the external bonding pad opening; forming an external solder ball; and dividing to form single chip packages.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a manufacturing method of an ultrathin fan-out type packaging structure.
Background
With the development and demand of multi-functionalization and miniaturization of electronic products, high-density semiconductor packaging technology is continuously applied to new-generation electronic products. In order to match the development of new generation electronic products, especially the development of products such as mobile phones, wireless products, intelligent wearing, internet of things and the like, the size of the package is developed towards the directions of higher density, higher speed, smaller size, lower cost and the like. With the adoption of the fan-out type packaging technology, a substrate is not needed, and a tested chip is directly interconnected to a PCB (printed circuit board) after being subjected to plastic packaging and manufacturing interconnection leads, so that the whole packaging body is thinner, and meanwhile, the cost of substrate materials is saved. The application of the large-board-Level Fan-Out Package (FOPLP) makes a rewiring layer on a substrate, greatly reduces the manufacturing cost, and is suitable for products with less pins and low precision requirements. The cost advantage is the main advantage of the large-board fan-out package, and how to further reduce the cost and simplify the manufacturing process is still a main direction of research.
The existing preparation method of the fan-out package of the die-last large board based on the substrate process mainly comprises the following steps: coating copper foils on the front surface and the back surface of the insulating layer carrier plate; drilling a hole on the insulating layer substrate coated with the copper foil; depositing copper layers on the side walls of the holes, and depositing copper layers on the surfaces of the copper foils on the two sides of the base material; laminating the photosensitive film on the surfaces of the two copper foils; exposing and developing to manufacture a double-layer circuit; removing the photosensitive film layer; coating a retainer mask on the front side and the back side; exposing and developing the Solder mask to expose the bonding pad; electroplating, nickel gold plating or OSP coating are carried out on the bonding pads on the front side and the back side, and the manufacturing of the double-sided substrate is finished; mounting a chip on a bonding pad on the A surface of the substrate, applying underfill between the chip and the substrate, and encapsulating the chip by a plastic package process; planting balls on a bonding pad on the B surface of the substrate; and cutting the whole packaging body, scribing and separating the single packaging body. The method needs to manufacture a double-sided substrate firstly, then carries out chip mounting, needs to carry out a temporary bonding carrier plate once when a first side is electroplated in the process, needs to firstly temporarily bond the carrier plate on the other side when a Top surface Solder Mask is manufactured, and then removes the first temporary bonding carrier plate, and the two temporary bonding processes have complex process flows, low mass production efficiency and relatively high cost.
Aiming at the problems of complex process flow, low volume production efficiency, relatively high cost and the like caused by the fact that two temporary bonding carrier plates are needed to carry out double-sided substrate manufacturing in the existing fan-out type packaging based on a substrate process die-last large plate, the invention provides a manufacturing method of an ultrathin fan-out type packaging structure.
Disclosure of Invention
Aiming at the problems of complex process flow, low volume production efficiency, relatively high cost and the like caused by the fact that a carrier plate needs to be temporarily bonded twice to manufacture a double-sided substrate in the conventional fan-out type packaging based on a die-last large plate of a substrate process, the invention provides a temporary bonding copper foil to the carrier plate according to one embodiment of the invention;
forming an electroplating pattern on the upper surface of the copper foil by photoetching;
electroplating to form a copper interconnection metal layer;
removing the photoresist mask layer;
forming a first dielectric layer on the outer surfaces of the copper foil and the copper interconnection metal layer, and photoetching to form a chip bonding pad opening;
forming a first copper protective layer at the opening of the chip bonding pad;
flip-chip bonding a chip to a chip bonding pad through a chip bonding structure;
filling an underfill between the chip and the first dielectric layer;
forming a plastic packaging layer;
removing the carrier plate by detaching the key;
etching to remove the copper foil;
forming a second dielectric layer, and photoetching to form an external bonding pad opening;
forming a second copper protective layer on the external bonding pad opening;
forming an external solder ball; and
and (4) dividing to form single chip packages.
In one embodiment of the invention, said temporary bonding of the copper foil to the carrier plate is by bonding the copper foil to the carrier plate by means of a temporary bonding material.
In one embodiment of the invention, the bonding material is a laser releasable bonding material.
In an embodiment of the present invention, the carrier is an organic substrate, a glass substrate, or a silicon substrate.
In one embodiment of the invention, the electroplated copper interconnect metal layer further comprises a chip pad, a redistribution wire and an external pad.
In one embodiment of the invention, the re-placement layout comprises N metal wiring layers, wherein N ≧ 2.
In one embodiment of the present invention, the first dielectric layer and/or the second dielectric layer is a solder resist layer.
In one embodiment of the present invention, the first copper protection layer and/or the second copper protection layer is a nickel layer or an Organic Solderability Preservative (OSP).
In one embodiment of the invention, the method for removing the copper foil by etching is a flash etching method.
The invention provides a manufacturing method of an ultrathin fan-out type packaging structure. The manufacturing method of the ultrathin fan-out type packaging structure realizes a fan-out packaging process based on a single temporary bonding process, reduces process steps, improves mass production efficiency and reduces process cost.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIG. 1 illustrates a cross-sectional view of an ultra-thin fan-out package structure 100 formed in accordance with an embodiment of the present invention.
Fig. 2A-2O are schematic cross-sectional views illustrating a process of forming such an ultra-thin fan-out package structure 100 according to an embodiment of the invention.
Fig. 3 illustrates a flow diagram for forming such an ultra-thin fan-out package structure 100, according to one embodiment of the invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a manufacturing method of an ultrathin fan-out type packaging structure. The manufacturing method of the ultrathin fan-out type packaging structure realizes a fan-out packaging process based on a single temporary bonding process, reduces process steps, improves mass production efficiency and reduces process cost.
An ultra-thin fan-out package structure according to an embodiment of the present invention is described in detail below with reference to fig. 1. FIG. 1 illustrates a cross-sectional view of an ultra-thin fan-out package structure 100 formed in accordance with an embodiment of the present invention. As shown in fig. 1, the ultra-thin fan-out package structure 100 further includes a first dielectric layer 101, a copper interconnection metal layer 102, a first copper passivation layer 103, a chip 104, a chip bonding structure 105, an underfill 106, a molding layer 107, a second dielectric layer 108, a second copper passivation layer 109, and external solder balls 110.
The first dielectric layer 101 is a solder resist cut-off material and needs to meet both insulation and mechanical performance requirements. In one embodiment of the present invention, the first dielectric layer 101 may be an organic substrate, a ceramic substrate, a solder resist green oil layer, or the like.
The upper surface of the copper interconnect metal layer 102 is covered by a first dielectric layer 101. In one embodiment of the present invention, copper interconnect metal layer 102 further includes fan-out interconnect lines (not shown), die pads (not shown), and external pads (not shown). In one embodiment of the present invention, the through interconnect metal layer 102 further includes multiple layers of re-routing lines and implements a fan-out function.
The first copper passivation layer 103 is located at the upper outer drain opening of the copper interconnect metal layer 102. The first copper protective layer 103 prevents oxidation of the outer copper metal, thereby causing a welding defect. In one embodiment of the present invention, the first copper protective layer 103 is a nickel layer or an Organic Solderability Preservative (OSP).
The chip 104 is flip-chip bonded to the first copper protective layer 103 on the copper interconnect metal layer 102 by a chip bonding structure 105. Die 104 is bonded to copper interconnect metal layer 102 by die bond structure 105 to form an electrical and/or signal connection. In one embodiment of the present invention, the die attach structure 105 is a bump, such as a lead-free solder ball, a Copper Pillar (Copper Pillar), or the like.
The molding layer 107 is located on the upper surface of the first dielectric layer 101, and covers the chip 104, so as to perform the insulation and mechanical protection functions on the chip and the package structure.
The second dielectric layer 108 is disposed on the lower surfaces of the first dielectric layer 101 and the copper interconnection metal layer 102, and an external pad opening is formed at an external pad of the copper interconnection metal layer 102.
The second copper passivation layer 109 is disposed at the external pad opening of the copper interconnect metal layer 102. The second copper protective layer 109 functions similarly to the first copper protective layer 103, and also prevents oxidation of the outer copper metal, thereby causing a welding defect. In one embodiment of the present invention, the second copper protective layer 109 is a nickel layer or an Organic Solderability Preservative (OSP).
The process of forming such an ultra-thin fan-out package structure 100 is described in detail below with reference to fig. 2A-2O and fig. 3. FIGS. 2A-2O are schematic cross-sectional views illustrating a process of forming such an ultra-thin fan-out package structure 100 according to one embodiment of the invention; fig. 3 illustrates a flow diagram 300 for forming such an ultra-thin fan-out package structure 100, according to one embodiment of the invention.
First, in step 301, as shown in fig. 2A, a copper foil 203 is temporarily bonded onto a carrier board 201 by a temporary bonding material 202. The carrier 201 may be an organic substrate, a glass substrate, a silicon substrate, etc., and plays a role in mechanical support and rigid protection; temporary bonding material 202 may be a releasable bonding adhesive, such as a laser releasable bonding adhesive or the like. In one embodiment of the present invention, the bonding structure is formed by coating a layer of temporary bonding material 202 on the carrier 201 and then pressing the copper foil 203.
Next, in step 302, as shown in fig. 2B, a plating pattern 204 is formed on the upper surface of the copper foil 203 by photolithography. The specific steps further include forming a photoresist layer, exposing, and developing to form the plating pattern 204, wherein the undeveloped photoresist 204 becomes a mask layer of the subsequent plating process, and the position where the photoresist is removed by developing forms a plating window.
Then, in step 303, copper interconnect metal layer 205 is formed by electroplating, as shown in fig. 2C. In one embodiment of the present invention, the copper interconnect metal layer 205 further comprises fan-out interconnect lines (not shown), die pads (not shown), and external pads (not shown). In one embodiment of the present invention, the through interconnect metal layer 205 further includes multiple layers of re-routing lines and implements a fan-out function.
Next, in step 304, the photoresist mask layer 204 is removed, as shown in FIG. 2D.
Then, in step 305, as shown in fig. 2E, a first dielectric layer 206 is formed on the surfaces of the copper foil 203 and the copper interconnection metal layer 205, and a pad opening is formed by photolithography. The first dielectric layer 206 is a solder resist cut-off material and needs to meet both insulation and mechanical performance requirements. In one embodiment of the present invention, the first dielectric layer 206 may be an organic substrate, a ceramic substrate, a solder resist green layer, or the like. Specific formation processes may include coating, deposition, lamination, and the like. In one embodiment of the present invention, a solder resist layer is formed by coating, and then exposed and developed to form pads necessary for bonding to a chip.
Next, at step 306, as shown in fig. 2F, a first copper protection layer 207 is formed at the pad opening. The first copper protective layer 207 can prevent oxidation of the outer copper metal, thereby causing a welding defect. In one embodiment of the present invention, the first copper protective layer 207 is a nickel layer or an Organic Solderability Preservative (OSP).
Then, at step 307, as shown in fig. 2G, the die 208 is flip-chip bonded to the die pad by the die bonding structure 209. Die 208 is bonded to form an electrical and/or signal connection with copper interconnect metal layer 205 through die bond structure 209. In one embodiment of the present invention, the die attach structure 209 is a bump, such as a lead-free solder ball, a Copper Pillar (Copper Pillar), or the like.
Next, in step 308, as shown in fig. 2H, underfill 210 is filled between chip 208 and first dielectric layer 206. After filling, the underfill 210 fills the gap between the die 208 and the first dielectric layer 206, and serves as an insulation and mechanical protection for the solder structure 209.
Then, in step 309, as shown in fig. 2I, a molding layer 211 is formed. The molding compound layer 211 is located on the upper surfaces of the first dielectric layer 206 and the chip 208, and covers the chip 208, thereby playing a role in insulating and mechanically protecting the chip 208 and the package structure.
Next, at step 310, as shown in fig. 2J, the bonding is released and the carrier plate 201 and the temporary bonding material 202 are removed. In one embodiment of the present invention, the temporary bonding material 202 is a laser debonding bonding material, the carrier 201 is a transparent material, and debonding is achieved by irradiating laser onto the back surface of the carrier 201 facing the temporary bonding material 202.
Then, in step 311, the copper foil 203 is etched away, as shown in FIG. 2K. In general, wet etching is commonly used, and in order to prevent over-etching defects, a flash etching method can be used to obtain a better etching removal effect.
Next, at step 312, as shown in fig. 2L, a second dielectric layer 212 is formed and an external bonding pad opening is formed by photolithography. The second dielectric layer 212 is also a solder resist cut-off material and needs to meet both insulation and mechanical performance requirements. In one embodiment of the present invention, the second dielectric layer 212 is a solder resist green oil layer or the like. In one embodiment of the present invention, the external connection pad is formed by coating the second dielectric layer 212, and then exposing and developing.
Then, in step 313, as shown in fig. 2M, a second copper protective layer 213 is formed in the landing pad opening. The second copper capping layer 213, like the first copper capping layer 207, can prevent oxidation of the outer copper metal, thereby causing a welding defect. In one embodiment of the present invention, the second copper protection layer 213 is a nickel layer or an Organic Solderability Preservative (OSP).
Next, at step 314, as shown in fig. 2N, external solder balls 214 are formed. The external solder balls 214 are electrically interconnected with the second copper passivation layer 213, which is an external electrical and/or signal interconnection interface of the overall package structure. In one embodiment of the present invention, the external solder balls 214 may be formed by electroplating, ball-planting, or the like.
Finally, in step 315, the individual chip packages are singulated and formed, as shown in fig. 2O.
According to the manufacturing method of the ultrathin fan-out type packaging structure, the carrier plate is temporarily bonded on one surface of the substrate, circuit interconnection is completed on the other surface of the substrate, bonding pads are manufactured, chip mounting and plastic packaging are carried out, then bonding is removed, and then circuit interconnection leakage, ball mounting, cutting and other processes are carried out to complete fan-out packaging. The manufacturing method of the ultrathin fan-out type packaging structure realizes a fan-out packaging process based on a single temporary bonding process, reduces process steps, improves mass production efficiency and reduces process cost.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (8)
1. A method for manufacturing an ultrathin fan-out package structure comprises the following steps:
temporarily bonding the copper foil to the carrier plate;
forming an electroplating pattern on the upper surface of the copper foil by photoetching, wherein the electroplating pattern is formed by forming a photoresist layer, exposing and developing, the undeveloped photoresist becomes a mask layer of a subsequent electroplating process, and an electroplating window is formed at the position where the photoresist is removed by developing;
electroplating to form a copper interconnection metal layer, wherein the copper interconnection metal layer further comprises a chip bonding pad, a re-layout wiring and an external bonding pad;
removing the photoresist mask layer;
forming a first dielectric layer on the outer surfaces of the copper foil and the copper interconnection metal layer, and photoetching to form a chip bonding pad opening, wherein the first dielectric layer is a solder resist cut-off material;
forming a first copper protective layer at the opening of the chip bonding pad;
flip-chip bonding a chip to a chip bonding pad through a chip bonding structure;
filling an underfill between the chip and the first dielectric layer;
forming a plastic packaging layer;
removing the carrier plate by detaching the key;
etching to remove the copper foil;
forming a second dielectric layer, and photoetching to form an external bonding pad opening;
forming a second copper protective layer on the external bonding pad opening;
forming an external solder ball; and
and (4) dividing to form single chip packages.
2. The method of manufacturing an ultra-thin fan-out package structure of claim 1, wherein the temporarily bonding the copper foil to a carrier is by temporarily bonding the copper foil to the carrier with a temporary bonding material.
3. The method of manufacturing an ultra-thin fan-out package structure of claim 2, wherein the bonding material is a laser releasable bonding material.
4. The method of claim 1, wherein the carrier is an organic substrate, a glass substrate, or a silicon substrate.
5. The method of claim 1, wherein the re-routing comprises N metal routing layers, where N ≧ 2.
6. The method of manufacturing an ultra-thin fan-out package structure of claim 1, wherein the first dielectric layer and/or the second dielectric layer is a solder resist layer.
7. The method of manufacturing an ultra-thin fan-out package structure of claim 1, wherein the first copper protective layer and/or the second copper protective layer is a nickel layer or an organic soldermask OSP.
8. The method of manufacturing an ultra-thin fan-out package structure of claim 1, wherein the etching to remove the copper foil is a flash etching process.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005244033A (en) * | 2004-02-27 | 2005-09-08 | Torex Semiconductor Ltd | Electrode package and semiconductor device |
| US7939935B2 (en) * | 2006-05-22 | 2011-05-10 | Hitachi Cable Ltd. | Electronic device substrate, electronic device and methods for fabricating the same |
| CN103489855A (en) * | 2013-09-30 | 2014-01-01 | 南通富士通微电子股份有限公司 | Wafer packaging structure |
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| JP4558413B2 (en) * | 2004-08-25 | 2010-10-06 | 新光電気工業株式会社 | Substrate, semiconductor device, substrate manufacturing method, and semiconductor device manufacturing method |
| CN104851816A (en) * | 2015-04-13 | 2015-08-19 | 华进半导体封装先导技术研发中心有限公司 | Method for packaging multiple chips in high density |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005244033A (en) * | 2004-02-27 | 2005-09-08 | Torex Semiconductor Ltd | Electrode package and semiconductor device |
| US7939935B2 (en) * | 2006-05-22 | 2011-05-10 | Hitachi Cable Ltd. | Electronic device substrate, electronic device and methods for fabricating the same |
| CN103489855A (en) * | 2013-09-30 | 2014-01-01 | 南通富士通微电子股份有限公司 | Wafer packaging structure |
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