CN216288317U

CN216288317U - Packaging mechanism

Info

Publication number: CN216288317U
Application number: CN202121921866.8U
Authority: CN
Inventors: 朱凯; 谷新; 缪桦
Original assignee: Shennan Circuit Co Ltd
Current assignee: Shennan Circuit Co Ltd
Priority date: 2021-08-16
Filing date: 2021-08-16
Publication date: 2022-04-12
Anticipated expiration: 2031-08-16

Abstract

The application discloses packaging mechanism includes: a conductive circuit; the first solder mask is attached to one side of the conductive circuits and is filled in gaps among the conductive circuits, and at least one hole is formed in the first solder mask; the chip is arranged on one side, away from the conducting circuit, of the first solder mask layer, and the chip through holes are electrically connected with the conducting circuit; the insulating layer covers the chip and fills a gap between the chip and the first solder mask layer; and the second solder mask layer is arranged on one side of the conductive circuit, which is far away from the first solder mask layer. Through above-mentioned structure, this application can obtain thickness thinner, and the encapsulation volume is littleer, the more portable packaging mechanism of structure.

Description

Packaging mechanism

Technical Field

The application relates to the technical field of packaging mechanisms, in particular to a packaging mechanism.

Background

Packaging is an important link in semiconductor manufacturing processes, provides electrical interconnection, mechanical support, heat dissipation and environmental protection for bare chips, and is one of the early conditions for realizing electrical functions of integrated circuit elements. Generally, a bare chip is packaged without separating from a package substrate, the package substrate is a carrier of the bare chip, and a molding compound layer encapsulates the bare chip onto the package substrate to form the whole packaging mechanism.

At present, the packaging mechanism is developing towards the direction of high-density packaging and high-precision packaging, and the requirements on the transmission loss, the line width and the like of the packaging mechanism are increasing in various industries.

And the traditional packaging mechanism is difficult to meet the increasingly strict preparation requirements.

SUMMERY OF THE UTILITY MODEL

The application provides a packaging mechanism to realize high-density, high accuracy encapsulation of packaging mechanism.

In order to solve the above technical problem, the present application provides a packaging mechanism, including: a conductive circuit; the first solder mask is attached to one side of the conductive circuits and is filled in gaps among the conductive circuits, and at least one hole is formed in the first solder mask; the chip is arranged on one side, away from the conducting circuit, of the first solder mask layer, and the chip through holes are electrically connected with the conducting circuit; the insulating layer covers the chip and fills a gap between the chip and the first solder mask layer; and the second solder mask layer is arranged on one side of the conductive circuit, which is far away from the first solder mask layer.

The chip comprises a chip body and at least one bonding pad salient point, wherein the chip body is electrically connected with the at least one bonding pad salient point respectively; and at least one pad bump is correspondingly penetrated through at least one hole on the first solder mask layer and is welded with the conductive circuit.

The insulating layer covers the chip and fills the gaps among the chip, the pad bumps and the first solder mask layer.

Wherein, a surface treatment layer is attached to the position of one side of the conductive circuit corresponding to the at least one hole; and the surface treatment layer is arranged between the conductive circuit and the bonding pad salient point.

Wherein, the width range of the conducting circuit is 1-20 microns.

Wherein the thickness of the first solder mask layer is in the range of 5-50 microns.

Wherein, packaging mechanism still includes: at least one bottom circuit layer; at least one bottom layer circuit layer is arranged between the conductive circuit and the second solder mask layer in a laminating mode.

Wherein, packaging mechanism still includes: at least one top circuit layer and a third solder mask layer; at least one top circuit layer is arranged on one side of the insulating layer far away from the chip; the third solder mask layer is attached to one side, away from the insulating layer, of the at least one circuit layer.

Wherein, packaging mechanism still includes: metallized through holes and/or metallized blind holes; the metallized through holes are used for being electrically connected with the circuit layers, and the metallized blind holes are used for being electrically connected with at least two circuit layers.

Wherein, packaging mechanism still includes: one or more of a resistor, a capacitor, an inductor, a passive component, and a functional semiconductor device.

The beneficial effect of this application is: be different from prior art's condition, this application can be through insulating layer parcel plastic-sealed chip, and then utilize first solder mask and insulating layer to get up the conductive circuit except that contacting other sides of second solder mask one side are protected to reduce the influence that the conductive circuit probably received, thereby improve the meticulous degree and the reliability of conductive circuit, and then improve the quality and the reliability of packaging mechanism, realize the high density, the high accuracy encapsulation of packaging mechanism. And this application directly wraps up the conducting wire through first soldermask layer, and then carries out insulating layer plastic envelope, has saved the dielectric layer for the thickness of final finished product packaging mechanism is thinner, and the encapsulation volume is littleer, and the structure is lighter, and the dielectric transmission loss is also littleer.

Drawings

FIG. 1 is a schematic flow chart diagram illustrating one embodiment of a method for making a packaging mechanism provided herein;

FIG. 2 is a schematic flow chart diagram of another embodiment of a method of making a packaging mechanism provided herein;

fig. 3a is a schematic structural diagram of an embodiment of the separable supporting layer obtained in step S21;

FIG. 3b is a structural diagram illustrating the conductive traces formed in step S22 according to an embodiment;

FIG. 3c is a schematic structural diagram of an embodiment of the solder mask windowing in step S23;

FIG. 3d is a schematic structural diagram of the last embodiment after the step S24 of plastic encapsulation;

FIG. 4 is a schematic structural diagram of an embodiment of the packaging mechanism of the present application;

FIG. 5 is a schematic structural view of another embodiment of the packaging mechanism of the present application;

fig. 6 is a schematic structural view of a further embodiment of the packaging mechanism of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring further to fig. 1, fig. 1 is a schematic flow chart illustrating a manufacturing method of a packaging mechanism according to an embodiment of the present disclosure.

Step S11: and obtaining the separable supporting layer.

And obtaining the separable supporting layer. In this embodiment, the separable supporting layer may include a separable supporting layer made of a supporting material having good thermal stability, high flatness, high mechanical strength, and low breakage.

The separable supporting layer can realize the separable characteristic through a release material or a separable copper foil or an adhesive material.

Step S12: electroplating the first preset position of the separable supporting layer to form a conductive circuit at the first preset position.

Electroplating the first preset position of the separable supporting layer to form a required conductive circuit at the first preset position. The first preset position is a position where a conducting circuit needs to be prepared, and the specific line type can be set based on actual conditions.

In a specific application scenario, the conductive line may be formed at the first preset position by performing electroless copper plating at the first preset position of the separable supporting layer, and then performing electroplating at the first preset position after the electroless copper plating. In another specific application scenario, a groove pattern may be prepared at a first preset position of the separable supporting layer by exposure and development, and then electroplating is performed based on the groove pattern, so as to form a conductive line at the first preset position. In another specific application scenario, a resist film may be attached to other positions of the separable supporting layer except the first preset position, and then the entire side of the separable supporting layer where the first preset position is located may be plated, so as to form a conductive line at the first preset position, and so on. The forming method of the conductive line is not limited in this embodiment.

The step is to directly carry out electroplating on the separable supporting layer, and the separable supporting layer is used as a strength support to obtain the conductive circuit, so that the conductive circuit in the step can be any line width based on the preparation requirement.

Step S13: and preparing a first solder mask layer on one side of the conductive circuit, which is far away from the separable supporting layer, and exposing part of the conductive circuit.

And preparing a first solder mask layer on one side of the conductive circuit, which is far away from the separable supporting layer, and exposing part of the conductive circuit.

In a specific application scenario, the first solder resist layer can be covered on the whole board on the side, away from the separable supporting layer, of the conductive circuit, and then windowing is performed on the corresponding position of the conductive circuit, which needs to be partially exposed, so that the partial conductive circuit is exposed, and part of the first solder resist layer is reserved to cover the rest conductive circuit.

In another specific application scenario, after windowing the corresponding position of the conductive circuit on the first solder resist layer, which is partially exposed, the conductive circuit is attached to the side of the conductive circuit, which is far away from the separable supporting layer, so that the partial conductive circuit is exposed, and the remaining conductive circuit is covered by the first solder resist layer.

Step S14: and electrically connecting the chip with the exposed part of the conductive circuit, and plastically packaging the chip to form the insulating layer.

In this embodiment, the exposed portion of the conductive traces needs to be electrically connected to the chip, so as to communicate the chip with the conductive traces.

And electrically connecting the chip with the exposed part of the conductive circuit, then plastically packaging the chip to form an insulating layer, and wrapping and plastically packaging the chip through the insulating layer.

The plastic package in the step can complete the chip plastic package and the manufacturing of the interconnection line of the packaging mechanism, thereby shortening the production chain of the packaging mechanism and improving the preparation efficiency of the packaging mechanism. The interconnection line of the traditional packaging mechanism needs to have certain mechanical supporting capacity when facing transportation and chip packaging, therefore, the interconnection line of the traditional packaging mechanism needs to have certain thickness, the supporting capacity of the interconnection line of the traditional packaging mechanism is guaranteed through a dielectric layer, but the thickness of the packaging mechanism is increased, and the preparation process is increased. In the embodiment, the chip plastic package and the interconnection circuit of the packaging mechanism are completed together, so that the requirement of the supporting capacity in the preparation process of the packaging mechanism is avoided, the thickness of the plate is reduced, the preparation flow is simplified, and the preparation efficiency is improved.

Step S15: and removing the separable supporting layer, and preparing a second solder mask layer at a second preset position on one side of the conductive circuit, which is far away from the first solder mask layer.

After the chip is wrapped by the insulating layer and is subjected to plastic packaging, the separable supporting layer is removed, and a second solder mask is prepared at one side of the conductive circuit far away from the first solder mask, namely a second preset position on the side where the original separable supporting layer is located.

When the separable supporting layer is removed, a corresponding removing mode can be adopted based on the type of the separable supporting layer. In a specific application scenario, when the separable supporting layer is a peelable copper foil, the peelable copper foil can be removed by etching. Because the other surfaces of the conducting circuit except the side contacted with the strippable copper foil are wrapped by the first solder mask layer and the insulating layer, the side surface of the conducting circuit can not be eroded by etching liquid when the strippable copper foil is etched, and the line width of the conducting circuit can not be influenced. Therefore, the conductive line in the packaging mechanism of the present embodiment may have any line width, including a hyperfine line.

In another specific application scenario, when the separable support layer is an adhesive support layer, the adhesive support layer can be removed by tearing. Because other faces of the conducting circuit at this moment except the side in contact with the adhesive supporting layer are wrapped by the first solder mask layer and the insulating layer, when the adhesive supporting layer is torn, the side face of the conducting circuit cannot be torn, and the line width of the conducting circuit cannot be influenced. Therefore, the conductive line in the packaging mechanism of the present embodiment may have any line width, including a hyperfine line.

In a specific application scenario, the second solder mask layer can be covered on the whole board on one side of the conductive circuit far away from the first solder mask layer, and then windowing is performed on all positions except the second preset position, so that part of the conductive circuit is exposed, and the conductive circuit at the second preset position is covered through the second solder mask layer.

In another specific application scenario, after windowing is performed on the second solder mask layer at positions corresponding to all positions except the second preset position, the second solder mask layer is attached to one side, far away from the first solder mask layer, of the conductive circuit, so that part of the conductive circuit is exposed, and the conductive circuit at the second preset position is covered by the second solder mask layer.

All positions, except the second preset position, on one side, away from the first solder mask layer, of the conductive circuit can be positions for ball planting or welding, and the conductive circuit exposed at all positions except the second preset position is electrically connected with a mother board of a printed circuit board, other elements or other devices, so that the packaging mechanism is electrically connected with other devices.

And preparing a second solder mask layer at a second preset position on one side of the conductive circuit, which is far away from the first solder mask layer, so as to obtain the final packaging mechanism. The packaging mechanism of the present embodiment may include a fan-out packaging mechanism or other packaging mechanisms.

By the method, the manufacturing method of the packaging mechanism of the embodiment uses the separable supporting layer as a temporary carrier for manufacturing the conductive circuit, after the conductive circuit with any line width is manufactured on the separable supporting layer, a part of the conductive circuit is covered by the first solder resist layer, and after the exposed part of the conductive circuit is connected with the chip, the plastic-packaged chip is wrapped by the insulating layer, and then the other sides of the conductive circuit except the side contacting with the separable supporting layer are protected by the first solder resist layer and the insulating layer, so that the influence possibly suffered by the conductive circuit when the separable supporting layer is removed is reduced, the fineness and the reliability of the conductive circuit are improved, and the quality and the reliability of the packaging mechanism are improved. In addition, in the embodiment, the first solder mask layer is directly used for wrapping the conductive circuit, then the insulating layer is used for plastic packaging, and then the chip plastic packaging and the manufacturing of the interconnection circuit of the packaging mechanism are synchronously completed, so that the production steps of the packaging mechanism are reduced, the preparation efficiency of the packaging mechanism is improved, and the insulating layer replaces the dielectric layer to enable the thickness of the final finished product packaging mechanism to be thinner, the packaging volume to be smaller, the structure to be lighter and the dielectric transmission loss to be smaller. On the basis, the packaging mechanism containing the chip can be further used as a packaging core board to process lamination lines on two sides of the packaging core board, so that a packaging mechanism finished product with higher wiring density is obtained.

Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a manufacturing method of a packaging mechanism according to another embodiment of the present disclosure.

Step S21: and obtaining the separable supporting layer.

And obtaining the separable supporting layer. The separable supporting layer comprises a strippable copper layer and a carrier layer which are stacked and attached. And the carrier layer further comprises a copper foil layer and a dielectric layer. The carrier layer is used for strength support in the preparation of the packaging mechanism, the copper foil layer is used for stripping the copper layer to be easily stripped, and the stripped copper layer is used as a seed layer for the preparation of the conductive circuit.

The thickness of the strippable copper layer ranges from 1.0 to 3.0 micrometers, specifically may be 1.0 micrometer, 1.5 micrometers, 2.0 micrometers, 3.0 micrometers, and the like, and may be specifically set based on actual requirements, which is not limited herein. The thickness of the carrier layer is in a range of 0.2-2.0 mm, and specifically may be 0.2 mm, 0.5 mm, 0.8 mm, 1.0 mm, 1.6 mm, 1.9 mm, 2.0 mm, and the like, and specifically may also be set based on actual requirements, which is not limited herein.

In a particular application scenario, the opposite sides of the strippable copper layer may be smooth to facilitate stripping.

When the packaging mechanism is prepared by adopting the strippable copper layer and the carrier layer as the separable supporting layer, the production line of the packaging mechanism is not required to be rebuilt, and the production line can be carried out in the conventional preparation process of the packaging mechanism, so that the production resource is saved.

Referring to fig. 3a, fig. 3a is a schematic structural diagram of an embodiment of the separable supporting layer obtained in step S21.

The separable support layer 10 of the present embodiment includes a peelable copper layer 11 and a carrier layer 12 that are laminated and attached to each other. The carrier layer 12 may further include a copper foil layer (not shown) and a dielectric layer (not shown) to ensure the strength of the carrier layer 12, reduce the influence of thermal expansion on the separable supporting layer 10, and further improve the precision of the conductive traces prepared on the separable supporting layer 10.

Step S22: electroplating is carried out on a first preset position of the strippable copper layer of the separable supporting layer so as to form a conductive circuit at the first preset position.

After the separable supporting layer is obtained, electroplating is carried out on a first preset position of the strippable copper layer of the separable supporting layer so as to form a conductive circuit at the first preset position.

In a specific application scenario, a photosensitive resist layer can be prepared on one side, away from a carrier layer, of a strippable copper layer, and then exposure and development treatment are sequentially performed on one side, provided with the photosensitive resist layer, of the strippable copper layer, so that a groove pattern is prepared at a first preset position, pattern electroplating is performed on the groove pattern at the first preset position, a conductive circuit is formed at the first preset position, and the photosensitive resist layer is removed after the conductive circuit is prepared at the first preset position.

The type of the photoresist layer material of the embodiment may include a photoresist type or a photoresist induced type material, and the photoresist layer may be prepared to a side of the strippable copper layer away from the carrier layer by attaching a dry film, dip coating, spray coating or spin coating a wet film.

In addition, during exposure and development, different mask schemes may be adopted in this embodiment based on the material type of the photosensitive resist layer, a trench pattern is produced at the first preset position through exposure or photolithography and development in sequence, and then the trench pattern at the first preset position is subjected to pattern electroplating to form a conductive circuit at the first preset position.

The line width of the conductive circuit of this embodiment may be any line width, including the hyperfine line width: 1-20 microns. The conductive circuit is made of one or more of copper, silver, gold, nickel, tin, palladium, cobalt, ruthenium and molybdenum.

Referring to fig. 3b, fig. 3b is a schematic structural diagram of the embodiment after the conductive lines are formed in step S22.

This step provides the conductive tracks 13 at first predetermined locations on the side of the peelable copper layer 11 remote from the carrier layer 12.

The conductive tracks 13 are arranged in abutment with the side of the peelable copper layer 11 remote from the carrier layer 12.

Step S23: the whole solder mask is prepared to one side of the conducting circuit far away from the separable supporting layer in an attaching, dip-coating, spraying or spin-coating mode, and windowing processing is carried out on the solder mask to form a first solder mask.

After the conducting circuit is prepared on one side of the strippable copper layer, the solder mask can be prepared to one side of the conducting circuit, which is far away from the separable supporting layer, in an attaching, dip-coating, spray-coating or spin-coating mode, and then the solder mask is subjected to windowing treatment to expose part of the conducting circuit and form a first solder mask. The part of the conductive circuit exposed in the step is used for electrically connecting with the chip. In this embodiment, the exposed portion of the conductive traces can be used for subsequent chip mounting.

Before the solder mask is not windowed, the solder mask covers the whole conductive circuit and fills all gaps between the conductive circuit and the strippable copper layer of the separable supporting layer. The solder mask is then windowed to form at least one hole in the solder mask, resulting in a first solder mask layer to expose a portion of the conductive line through the at least one hole. And the conducting circuit which is not exposed is still covered and protected by the first solder mask layer.

The solder mask of the embodiment may be any one of a dry solder mask film and a wet solder mask film, so that the first solder mask layers of different material types are prepared according to different solder mask films. And the thickness of the first solder mask layer ranges from 5 to 50 micrometers, specifically may be 5 micrometers, 10 micrometers, 20 micrometers, 30 micrometers, 45 micrometers, 50 micrometers, and the like, and may be specifically set based on actual requirements.

When the solder mask is subjected to windowing treatment, the solder mask can be windowed by respectively adopting modes of exposure development, laser ablation or plasma etching and the like based on different material types of the solder mask so as to expose part of the conducting circuit. For example: when the first solder mask layer is prepared from the solder mask dry film, the solder mask can be windowed in a laser ablation mode; when the first solder resist layer is made of a solder resist wet film, the solder resist film may be windowed or the like by means of plasma etching, and is not particularly limited herein.

In a specific application scenario, when the solder mask is windowed, windowing can be performed based on the size of a pad bump of a chip to be mounted subsequently, so that the size of at least one hole is matched with the size of the pad bump, and the pad bump is ensured to be connected with a conductive circuit through the hole.

In a specific application scenario, after a first solder mask layer is obtained by windowing a solder mask and exposing a part of a conductive circuit, a surface treatment layer is manufactured on the exposed part of the conductive circuit so as to improve the chip mounting quality. Specifically, the surface treatment layer of the embodiment includes one or more of a silver layer, a nickel layer, a palladium layer, a gold layer, a tin layer, and an organic metal compound layer, and may be specifically selected based on the chip type and the mounting requirements.

Referring to fig. 3c, fig. 3c is a schematic structural diagram of an embodiment after the solder mask is windowed in step S23.

The first solder resist layer 14 of the present embodiment fills all the voids between the conductive line 13 and the strippable copper layer 11. The first solder mask layer 14 is formed with at least one hole 141, and the conductive trace 13 exposes a portion of the conductive trace through the at least one hole 141 for subsequent electrical connection with other components.

And the carrier layer 12 serves as a carrier for supporting its preparation during the formation of the first solder mask layer 14.

Step S24: and welding the pad salient points on the chip and the exposed part of the conductive circuit by reflow soldering, and plastically packaging the chip by a plastic packaging material to form an insulating layer around the chip.

After part of the conductive circuit is exposed, the pad salient points on the chip and the exposed part of the conductive circuit can be welded in a reflow soldering mode, so that the chip and the conductive circuit are electrically connected. After the electric connection, the chip is subjected to plastic package through a plastic package material so as to form an insulating layer around the chip, and the chip is electrically connected with the conductive circuit, so that when the insulating layer is formed around the chip, the chip and the whole mechanism can be subjected to plastic package simultaneously. The thickness value of the finally formed insulating layer is greater than or equal to the height difference between the side, away from the conductive circuit, of the chip and the side, away from the conductive circuit, of the first solder mask layer, so that the whole chip can be conveniently subjected to plastic package.

In a specific application scenario, the chip and the conductive circuit may be mounted by a chip mounter, and then the pad bumps of the chip are soldered on the exposed conductive circuit by passing through the holes on the first solder resist layer respectively and correspondingly by reflow soldering. After welding, the pad salient points of the chip are embedded into the first solder mask layer.

The chip of the present embodiment includes a flip chip or other chips. The plastic package material of the present embodiment may include an epoxy plastic package material or other insulating plastic package materials, and the plastic package material may be a liquid, powder, granule, or sheet plastic package material. The plastic packaging method of this embodiment may include compression molding or vacuum film pasting, and may be specifically selected based on the type of the plastic packaging material, which is not limited herein.

The material of the insulating layer in this embodiment may include an organic resin and a silica filler, and the weight ratio of silica in the insulating layer ranges from 1 to 95%, specifically may be 1%, 20%, 50%, 62%, 75%, 80%, 90%, 95%, and the like, and may be specifically set based on the actual situation, which is not limited herein.

In other embodiments, the bonding between the pad bumps and the conductive traces of the chip may be performed by wave soldering, and the specific bonding manner is not limited herein.

Referring to fig. 3d, fig. 3d is a schematic structural diagram of the embodiment after the step S24 of plastic packaging.

The chip 15 of the embodiment is provided with a plurality of pad bumps 151, wherein each pad bump 151 penetrates through a hole in the first solder mask layer 14 to be electrically connected with the conductive circuit 13, the insulating layer 16 is arranged around the chip 15, the insulating layer 16 wraps the chip 15 and fills gaps among the chip 15, the first solder mask layer 14 and the pad bumps 151, and the packaging and plastic encapsulation of the whole plate are completed.

Step S25: and removing the separable supporting layer to expose one side of the conducting circuit far away from the first solder mask layer, preparing the whole solder mask plate to one side of the conducting circuit far away from the first solder mask layer in an attaching, dip-coating, spraying or spin-coating mode, and windowing the position on the solder mask except the second preset position to form a second solder mask layer.

After plastic package is completed, the carrier layer of the conducting circuit layer far away from the insulating layer is removed. In particular, the carrier layer of the detachable support layer can be peeled off by a plate separator. And then removing the remaining strippable copper layer by etching to expose one side of the conductive circuit far away from the first solder mask layer. At this moment, the other surfaces of the conductive circuit except the side in contact with the strippable copper layer are wrapped by the first solder mask layer, so that the etching solution cannot etch the side surface of the conductive circuit during etching, and the line width of the conductive circuit is influenced. That is, the problem of side etching of the conductive line is completely avoided during etching, so that the conductive line with any line width, including the ultra-fine conductive line, can be prepared and obtained in the embodiment.

After the whole separable supporting layer is removed, one side, away from the first solder mask, of the conducting circuit is exposed, and a second solder mask is prepared at a second preset position on one side, away from the first solder mask, of the conducting circuit.

In a specific application scenario, the solder mask can be prepared on the whole board on the side of the conducting circuit far away from the first solder mask layer, and then the solder mask is windowed, so that all positions of the side of the conducting circuit far away from the first solder mask layer except the second preset position are exposed, and the second solder mask layer is obtained.

In another specific application scenario, after windowing is performed on the solder mask at positions corresponding to all positions except the second preset position, the solder mask is attached to one side, far away from the first solder mask layer, of the conductive circuit, so that part of the conductive circuit is exposed, and the conductive circuit at the second preset position is covered by the second solder mask layer.

After the window is opened, the position, which is not covered by the second solder mask layer, of one side, away from the first solder mask layer, of the conductive circuit is used for ball planting or is used for being electrically connected with other equipment.

The material, preparation method, windowing method, etc. of the second solder mask layer in this step are the same as those of the first solder mask layer, and please refer to the foregoing, which is not described herein again.

In a specific application scenario, after the solder mask is windowed, a surface treatment layer can be prepared at a position where the conducting circuit is not covered by the solder mask, so as to improve the quality of subsequent mounting, welding or electrical connection of the conducting circuit. The material and the preparation method of the surface treatment layer in this step are the same as those of the surface treatment layer in step S23, and please refer to the foregoing, which is not described herein again.

Through the steps, the preparation method of the packaging mechanism of the embodiment adopts the strippable copper layer as a temporary carrier for preparing the conductive circuit, improves the precision and the reliability of the conductive circuit by utilizing the stability and the mechanical strength of the strippable copper layer, covers a part of the conductive circuit through the first solder resist layer after the conductive circuit with any line width is prepared on the strippable copper layer, and wraps the chip through the insulating layer after the exposed part of the conductive circuit is connected with the chip, so that the other sides of the conductive circuit except the side contacting with the separable supporting layer are protected by the first solder resist layer and the insulating layer, thereby reducing the influence possibly suffered by the conductive circuit when the separable supporting layer is removed, improving the fineness and the reliability of the conductive circuit, and further improving the quality and the reliability of the packaging mechanism. In addition, in the embodiment, the first solder mask layer is directly used for wrapping the conductive circuit, so that the insulating layer plastic package is carried out, the chip plastic package and the packaging mechanism plastic package are carried out synchronously, the production steps are reduced, the dielectric layer is omitted, the thickness of the final finished product packaging mechanism is thinner, the packaging volume is smaller, the structure is lighter, and when the packaging mechanism is a fan-out packaging mechanism, the plate is thinner, the fan-out circuit of the chip is shorter, and the dielectric transmission loss is also smaller. The manufacturing method of the packaging mechanism of the embodiment shortens the production supply chain of the packaging mechanism, has relatively low cost and relatively high production efficiency, is completely compatible with the conventional packaging mechanism processing equipment, and has wide applicability and strong popularization.

In other embodiments, after the separable supporting layer is removed, at least one bottom circuit layer may be prepared on a side of the conductive circuit away from the first solder resist layer by a lamination method, and then a second solder resist layer may be prepared on a second predetermined position on a side of the at least one bottom circuit layer away from the first solder resist layer. The specific steps of preparing the second solder mask layer at the second predetermined position in this embodiment are the same as those in the previous embodiments, and please refer to the foregoing description, which is not repeated herein.

In a specific application scenario, the bottom insulating layer and the copper layer can be pressed on one side of the conductive circuit, which is far away from the first solder mask layer, then the first layer of bottom conductive circuit is manufactured by adopting a method of film pasting, exposure, development, etching and film removing, and then the steps are repeated, and finally at least one layer of bottom circuit layer is obtained by layer-by-layer manufacturing. After all the bottom circuit layers are manufactured, a second solder mask layer and a surface treatment layer are prepared at the relevant positions of the bottom circuit layer at the outermost side, so that the positions for ball planting or electric connection with other elements or equipment are exposed. In another specific application scenario, all the insulating layers and the copper layers can be overlapped and placed to form at least one bottom circuit layer through one-time pressing.

The specific number of bottom circuit layers may be determined based on actual requirements, for example: 3 layers, 8 layers, 10 layers, etc., without limitation. In a specific application scenario, the number of at least one bottom wiring layer may range from 1 to 20.

In other embodiments, after the chip is molded, at least one top circuit layer may be formed on a side of the insulating layer away from the conductive circuit by a lamination method, and a third solder resist layer may be formed on a side of the at least one top circuit layer away from the insulating layer.

In a specific application scenario, a copper layer can be prepared on one side of the insulating layer far away from the conducting circuit by adopting a pressing, chemical copper plating, titanium/copper sputtering or electroplating mode, then a first top layer circuit layer is prepared on the copper layer by adopting a film pasting, exposure, development, etching and film removing method, and then the top layer circuit layer is prepared above the first top layer circuit layer by layer. In another specific application scenario, all the top insulating layers and the top copper layers may be overlapped on the insulating layer, and at least one top circuit layer is formed by one-time pressing.

The specific number of top circuit layers may be determined based on actual requirements, for example: 3 layers, 8 layers, 10 layers, etc., without limitation. In a specific application scenario, the number of at least one top layer line layer may range from 1 to 20.

When the packaging mechanism needs to prepare at least one bottom layer circuit layer, at least one top layer circuit layer and related structures, the at least one bottom layer circuit layer and related structures can be prepared first, and then the at least one top layer circuit layer and related structures can be prepared; or at least one top layer circuit layer and related structures thereof can be prepared first, and then at least one bottom layer circuit layer and related structures thereof can be prepared; can also be prepared simultaneously. When at least one layer of top layer circuit layer and related structures thereof are prepared firstly and at least one layer of bottom layer circuit layer and related structures thereof are prepared secondly, the risk of cracks generated on the insulating layer when the carrier layers of the strippable copper layers are separated can be reduced, and when at least one layer of bottom layer circuit layer and related structures thereof are prepared firstly and at least one layer of top layer circuit layer and related structures thereof are prepared secondly, a finer bottom layer circuit layer can be manufactured.

In other embodiments, the conduction between the circuit layers can be realized by preparing a metallized through hole and/or a metallized blind hole between at least one bottom circuit layer and/or at least one top circuit layer.

In a specific application scenario, when at least one bottom circuit layer is prepared, a bottom insulating layer and a copper layer can be pressed on one side of a conducting circuit, which is far away from a chip, first, blind holes and/or through holes are manufactured on the bottom insulating layer and the copper layer by adopting a laser or plasma method, metallization of the blind holes and/or the through holes is realized by further adopting chemical copper plating and/or electroplating to realize interlayer interconnection of the bottom circuit layer, then, a first bottom circuit layer is manufactured on the copper layer by adopting a film pasting, exposing, developing, etching and film removing method, and then the steps are repeated, and finally, at least one bottom circuit layer is obtained by layer-by-layer manufacturing. In another specific application scenario, when at least one bottom circuit layer is prepared, an ABF material can be attached to one side of a conductive circuit, which is far away from a first solder mask layer, in a vacuum manner to obtain a bottom insulating layer, then blind holes and/or through holes are prepared on the bottom insulating layer by adopting a laser or plasma method, then metallization of the blind holes and/or the through holes is realized by adopting a chemical copper plating or titanium/copper sputtering or electroplating method, a copper layer is formed on the bottom insulating layer, then a first bottom conductive circuit is prepared on the copper layer by adopting a film attaching, exposing, developing, pattern electroplating, film removing and quick etching method, and then the above steps are repeated, and finally at least one bottom circuit layer is obtained by layer-by layer preparation. In another specific application scenario, when at least one bottom circuit layer is prepared, a photosensitive material can be attached to one side of the conductive circuit, which is far away from the first solder mask layer, in a vacuum manner, then the blind hole is prepared by adopting an exposure method, then the photosensitive material is cured to obtain a bottom insulating layer, further the metallization of the blind hole is realized by adopting a chemical copper plating or titanium/copper sputtering or electroplating method, a copper layer is formed on the bottom insulating layer, then the first bottom conductive circuit layer is prepared on the copper layer by adopting a film pasting, exposure, development, pattern electroplating, film stripping and quick etching method, and then the steps are repeated, and finally at least one bottom circuit layer is prepared layer by layer. In another specific application scenario, at least one bottom circuit layer can be manufactured layer by comprehensively using the three methods.

In a specific application scenario, when at least one top circuit layer is prepared, a blind hole or a through hole may be prepared on an insulating layer by using a laser or plasma method, metallization of the blind hole and/or the through hole is further realized by using a chemical copper plating or titanium/copper sputtering method, a copper layer is formed on one side of the insulating layer away from a chip, the blind hole and/or the through hole is filled with electroplated copper, the copper layer of the insulating layer is thickened, or the copper layer of the insulating layer and the metallization layer of the wall of the blind hole and/or the through hole are thickened by the electroplated copper, and the blind hole and/or the through hole is filled with a resin plug hole. And then the first top circuit layer is manufactured by adopting the methods of film pasting, exposure, development, etching and film stripping. And then manufacturing the rest top layer circuit layers above the first top layer circuit layer by layer. The method for fabricating the remaining top circuit layer by layer is similar to the method for fabricating the remaining bottom circuit layer by layer, and please refer to the foregoing text, which is not repeated herein.

And after all the top circuit layers are prepared, preparing a third solder mask layer on one side of the topmost circuit layer, which is far away from the chip. In a specific application scenario, a third solder mask layer may be prepared on the side of the topmost circuit layer away from the chip, and then the third solder mask layer of the whole board is windowed to expose a portion of the topmost circuit layer for ball mounting, electrical connection with other components or devices, or printing of solder paste or flux.

The material and the preparation method of the third solder mask layer are the same as those of the second solder mask layer and the first solder mask layer in the foregoing embodiments, and please refer to the foregoing, which is not described herein again.

In other embodiments, before the chip is subjected to plastic package, a conductive circuit or a peelable copper foil is used as a basis, a conductive copper column is manufactured on the conductive blind hole and/or the through hole in a manner of adhering a dry film, exposing, developing, electroplating the copper column and removing the film, then the chip and the conductive copper column are subjected to plastic package, and the insulating layer is polished to a specified thickness, so that the top of the conductive copper column is exposed, other circuit layers are conveniently conducted, and interlayer interconnection among the circuit layers is realized.

In other embodiments, when the first solder mask layer is prepared, in addition to windowing based on the pad bumps of the chip, windowing may be performed based on the positions of the metallized blind holes to obtain the predetermined holes in the first solder mask layer, so as to expose part of the conductive traces through the predetermined holes. And then after preparing the insulating layer, the position based on the preset hole of first solder mask carries out drilling to the insulating layer, obtains the through-hole on the insulating layer, and then carries out the metallization to it, realizes the intercommunication of electric line and top layer circuit layer, and then each circuit layer about the intercommunication insulating layer.

In other embodiments, after the top circuit layer and/or the bottom circuit layer are prepared by the packaging mechanism, a through hole may be prepared on the whole board, and then the through hole is plated with copper chemically and/or with copper electrically for metallization, thereby realizing interlayer interconnection of the circuit layers. In the embodiment, whether the through hole needs resin plug hole is limited, specifically, if the through hole is subsequently used for plugging and mounting a component, the resin plug hole is not needed; resin plugging is required if no components are required to be mounted or if metallization is required at one end of the through hole for component mounting.

Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of a packaging mechanism of the present application.

The packaging mechanism 100 of the embodiment includes a conductive circuit 13, a first solder resist layer 14, a chip 15, an insulating layer 16, and a second solder resist layer 17. The first solder mask layer 14 is attached to one side of the conductive traces 13 and fills gaps between the conductive traces 13, and at least one hole 141 is formed in the first solder mask layer 14 and used for exposing a part of the conductive traces 13. The chip 15 is arranged on one side of the first solder mask layer 14 away from the conductive circuit 13, and the chip 15 is provided with at least one hole 141 through which it is electrically connected with the conductive circuit 13; the insulating layer 16 covers the chip 15 and fills a gap between the chip 15 and the first solder resist layer 14, so as to plastically mold the chip 15, and the second solder resist layer 17 is disposed on a side of the conductive circuit 13 away from the first solder resist layer 14. Wherein at least one hole 141 extends through the first solder mask layer 14.

That is, the side of the conductive line 13 close to the second solder resist layer 17 is coplanar with the side of the second solder resist layer 17 close to the conductive line 13. The first solder mask layer 14 is positioned on one side of the conductive circuit 13 far away from the second solder mask layer 17 and wraps the conductive circuit 13 therein, and one side of the first solder mask layer 14 close to the second solder mask layer 17 is coplanar with one side of the conductive circuit 13 close to the second solder mask layer 17.

The insulating layer 16 is positioned on the side of the chip 15 far away from the conductive circuit 13 and wraps the chip 15 and the first solder mask layer 14 therein, and the side of the insulating layer 16 close to the first solder mask layer 14 is coplanar with the side of the first solder mask layer 14 close to the insulating layer 16.

Through the structure, the packaging mechanism of the embodiment can wrap the plastic package chip through the insulating layer, and then other sides of the conductive circuit except the side contacting the second solder mask are protected by utilizing the first solder mask and the insulating layer, so that the influence possibly received by the conductive circuit is reduced, the fineness and the reliability of the conductive circuit are improved, and the quality and the reliability of the packaging mechanism are improved. In addition, in the embodiment, the first solder mask layer is directly used for wrapping the conducting circuit, so that the insulating layer is subjected to plastic package, a dielectric layer is omitted, the thickness of the final finished product packaging mechanism is thinner, the packaging volume is smaller, the structure is lighter, and when the packaging mechanism is a fan-out type packaging mechanism, the plate is thinner, the circuit for fan-out of the chip is shorter, and the dielectric transmission loss is also smaller.

In other embodiments, the insulating layer 16 on the side of the chip 15 away from the conductive trace 13 may only encapsulate the chip 15 therein, with the side of the insulating layer 16 near the conductive trace 13 being coplanar with the side of the first solder resist layer 14 near the second solder resist layer 17.

In other embodiments, the chip 15 includes a chip body 152 and at least one pad bump 151. And the chip body 152 is electrically connected to at least one pad bump 151, respectively. And at least one pad bump 151 correspondingly penetrates through at least one hole 141 on the first solder mask layer 14 and is soldered with the conductive circuit 13, so as to conduct the chip body 152 and the conductive circuit 13.

The chip 15 may comprise a flip chip or other chip.

In other embodiments, the insulating layer 16 covers the chip 15 and fills the gap between the chip 15, the pad bumps 151 and the first solder mask layer 14, thereby completing the plastic encapsulation between the chip 15 and the conductive traces 13, and further encapsulating the whole board.

In other embodiments, a surface treatment layer (not shown) is attached to a position corresponding to the at least one hole 141 on one side of the conductive trace 13, and the surface treatment layer is disposed between the conductive trace 13 and the pad bumps 151, so as to improve the quality of the chip 15 attached to the exposed conductive trace 13 through the pad bumps 151.

The surface treatment layer comprises one or more of a silver layer, a nickel layer, a palladium layer, a gold layer, a tin layer and an organic metal compound layer, and can be selected based on actual requirements.

In other embodiments, the line width of the conductive line 13 is in a range of 1-20 μm, i.e. the conductive line 13 may be a hyperfine conductive line, such as: 1 micron, 5 microns, 8 microns, 10 microns, 13 microns, 16 microns, 20 microns and the like, and the specific value can be selected based on actual requirements.

In other embodiments, the conductive traces 13 include one or more of copper traces, silver traces, gold traces, nickel traces, tin traces, palladium traces, cobalt traces, ruthenium traces, and molybdenum traces, which can be selected based on actual requirements.

The conductive traces 13 may be used to fan out the pins of the chip 15 and also to solder with the pad bumps 151 of the chip 15 to conduct the chip 15.

In other embodiments, the line width range of the conductive line 13 may be any width range.

In other embodiments, the thickness of the first solder mask layer 14 is in the range of 5-50 microns. Specifically, the particle size may be 5 micrometers, 10 micrometers, 13 micrometers, 20 micrometers, 24 micrometers, 26 micrometers, 28 micrometers, 30 micrometers, 35 micrometers, 36 micrometers, 39 micrometers, 42 micrometers, 46 micrometers, 50 micrometers, or the like. The thickness of the first solder mask layer 14 is greater than the thickness of the conductive traces 13, so as to entirely cover and protect the conductive traces 13 and fill the gaps between the conductive traces 13.

In other embodiments, at least one through groove 171 is formed in the second solder resist layer 17, and the at least one through groove 171 exposes a part of the surface of the conductive trace 13 on the side away from the first solder resist layer 14. The partial surface may be used for ball-planting on the conductive trace 13, and further for soldering the packaging mechanism 100 with a printed circuit board, other components or other devices.

The second solder mask layer 17 is used for protecting the conductive circuit 13 from oxidation, corrosion, scratching, electrical insulation, and moisture during transportation, storage, and use of the packaging mechanism 100, and for solder-resisting when the packaging mechanism 100 is soldered to a printed circuit board, other components, or other devices.

In other embodiments, the insulating layer 16 may include an organic resin layer and a silicon dioxide layer, and the proportion of the silicon dioxide layer in the insulating layer 16 is in a range of 1-95%, specifically 1%, 20%, 50%, 62%, 75%, 80%, 90%, 95%, and the like, and may be specifically set based on actual situations, which is not limited herein.

The thickness of the insulating layer 16 is greater than or equal to the height difference between the side of the chip 15 far away from the conductive circuit 13 and the side of the first solder mask layer 14 far away from the conductive circuit 13, so that the whole chip 15 can be subjected to plastic molding.

Referring to fig. 5, fig. 5 is a schematic structural diagram of another embodiment of the packaging mechanism of the present application. In the packaging mechanism of the present embodiment, the connection relationship, the position structure, the thickness range, the composition, and the like between the conductive circuit, the first solder resist layer, the chip, the solder bump, and the insulating layer are the same as those in the foregoing embodiments, and please refer to the foregoing text, which is not described herein again.

In this embodiment, the packaging mechanism 200 further includes: at least one bottom wiring layer 220 and/or at least one top wiring layer 219.

At least one bottom circuit layer 220 is stacked between the conductive circuit 213 and the second solder resist layer 217. Specifically, each of the bottom circuit layers 220 includes bottom conductive traces 2201, a bottom insulating layer 2203, and at least one interconnect hole 2202. At least one interconnect hole 2202 is connected to the conductive layer on a side near the chip, the interconnect hole 2202 is connected to the bottom conductive line 2201 on a side away from the chip, and the bottom insulating layer 2203 fills a gap between the conductive layer and the bottom conductive line 2201. The conductive layer here includes other bottom conductive traces 2201 or conductive traces 213. The interconnect holes 2202 may be metalized holes or metal pillars, and may specifically include through holes or blind holes.

A second solder mask layer 217 is attached to a second preset position on one side of the whole at least one bottom circuit layer 220 far away from the chip. Specifically, a second solder resist layer 217 is attached to a second preset position on one side, away from the chip, of the bottom conductive trace 2201 of the at least one bottom trace layer 220 farthest from the chip. The bottom conductive trace 2201 is not covered by the second solder resist layer 217 and is used to solder the packaging mechanism 200 to a motherboard of a printed circuit, other component, or other device.

And at least one top wiring layer 219 is disposed on a side of the insulating layer away from the chip. Specifically, a first top circuit layer 226 is disposed on a side of the insulating layer away from the chip, and at least one top circuit layer 219 is disposed on a side of the first top circuit layer 226 away from the chip.

Each of the top circuit layers 219 includes a top conductive line, a top insulating layer, and at least one interconnection hole, and the specific arrangement manner thereof is similar to that of the bottom circuit layer 220.

And a third solder mask layer 218 is attached to a third preset position on one side of the whole at least one top layer circuit layer 219 far away from the chip. Specifically, a third solder resist layer 218 is attached to a third predetermined position on a side of the top conductive trace layer 219 farthest from the chip, away from the chip. The top conductive traces are not covered by the third solder mask 218 and are used for soldering passive components or various chips and modules.

In other embodiments, the packaging mechanism 200 further comprises: a metallized via 222 and/or a metallized blind via 223. The metallized through hole 222 penetrates through the entire packaging mechanism 200 and can be communicated with all circuit layers or part of the circuit layers, and the metallized blind hole 223 is arranged inside the packaging mechanism 200 and is communicated with part of the circuit.

The metallized blind holes 223 can communicate with any circuit layer based on actual requirements.

The blind metallization hole 223 of the present embodiment includes a blind metal hole 2231 and a conductive copper pillar 2241. The metal blind vias 2231 and the conductive copper posts 2241 may communicate the bottom wiring layer 220 with the top wiring layer 219. In other embodiments, the metal blind vias 2231 and the conductive copper pillars 2241 may be located between at least one bottom wiring layer 220 or at least one top wiring layer 219.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a packaging mechanism according to another embodiment of the present application. In the packaging mechanism of the present embodiment, the connection relationship, the position structure, the thickness range, the composition, and the like between at least one bottom layer circuit layer, at least one top layer circuit layer, the plated through hole, the conductive circuit, the first solder resist layer, the chip, the solder bump, and the insulating layer are the same as those in the foregoing embodiments, and thus, the details are not repeated herein.

The packaging mechanism 300 of the present embodiment further comprises one or more of a resistor 303, a capacitor 304, an inductor 305, a passive element 302, and a functional semiconductor device 301. The resistor 303, the capacitor 304 and the inductor 305 may be embedded in the bottom circuit layer in a thin film form, and contact with the bottom circuit layer to be conducted; the top circuit layer may further include a passive element 302 and a functional semiconductor device 301, wherein the passive element 302 may include one or more of a resistor, a capacitor, and an inductor; the functional semiconductor device 301 may include one or more of a memory device, a power device, a logic device, an optoelectronic device, an analog device, a discrete device; in an embodiment, the functional semiconductor device 301 is interconnected with the top wiring layer by leads 306.

Through the structure, the packaging mechanism of the embodiment saves the existence of the dielectric layer through the arrangement of the conducting circuit, the chip and the insulating layer, further can obtain the packaging mechanism with thinner thickness and smaller packaging volume, improves the portability and the applicable range of the packaging mechanism, reduces the transmission loss of the dielectric in the packaging mechanism due to the removal of the dielectric layer, further develops the three-dimensional packaging of the packaging mechanism through at least one bottom layer circuit layer, at least one top layer circuit layer, the metalized through hole and/or the blind hole and other elements, and further improves the performance and the universality of the packaging mechanism.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A packaging mechanism, comprising:

a conductive circuit;

the first solder mask is attached to one side of the conductive circuits and fills gaps among the conductive circuits, and at least one hole is formed in the first solder mask;

the chip is arranged on one side, away from the conducting circuit, of the first solder mask layer, and the chip penetrates through the hole to be electrically connected with the conducting circuit;

the insulating layer covers the chip and fills a gap between the chip and the first solder mask layer;

and the second solder mask layer is arranged on one side of the conducting circuit, which is far away from the first solder mask layer.

2. The packaging mechanism of claim 1, wherein the chip comprises a chip body and at least one pad bump, the chip body is electrically connected to the at least one pad bump respectively;

and the at least one pad salient point correspondingly penetrates through at least one hole on the first solder mask layer and is welded with the conductive circuit.

3. The packaging mechanism of claim 2,

the insulating layer covers the chip and fills the gap among the chip, the pad salient point and the first solder mask layer.

4. The packaging mechanism of claim 2,

a surface treatment layer is attached to the position, corresponding to the at least one hole, of one side of the conductive circuit;

and the surface treatment layer is arranged between the conductive circuit and the bonding pad salient point.

5. The packaging mechanism of claim 1,

the width of the conductive circuit ranges from 1 micron to 20 microns.

6. The packaging mechanism of claim 1,

the thickness of the first solder mask layer ranges from 5 to 50 microns.

7. The packaging mechanism of claim 1, further comprising: at least one bottom circuit layer;

and at least one bottom layer circuit layer is arranged between the conductive circuit and the second solder mask layer in a laminating manner.

8. A packaging mechanism according to claim 1 or 7, further comprising: at least one top circuit layer and a third solder mask layer;

at least one top layer circuit layer is arranged on one side of the insulating layer far away from the chip;

the third solder mask layer is attached to one side, away from the insulating layer, of the at least one circuit layer.

9. The packaging mechanism of claim 8, further comprising: metallized through holes and/or metallized blind holes;

the metallized through holes are used for being electrically connected with the circuit layers, and the metallized blind holes are used for being electrically connected with at least two circuit layers.

10. The packaging mechanism of claim 8, further comprising: one or more of a resistor, a capacitor, an inductor, a passive component, and a functional semiconductor device.