DE69325749D1 - Gestapelte Mehrchip-Module und Verfahren zur Herstellung - Google Patents

Gestapelte Mehrchip-Module und Verfahren zur Herstellung

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Publication number
DE69325749D1
DE69325749D1 DE69325749T DE69325749T DE69325749D1 DE 69325749 D1 DE69325749 D1 DE 69325749D1 DE 69325749 T DE69325749 T DE 69325749T DE 69325749 T DE69325749 T DE 69325749T DE 69325749 D1 DE69325749 D1 DE 69325749D1
Authority
DE
Germany
Prior art keywords
manufacturing processes
chip modules
stacked multi
stacked
modules
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69325749T
Other languages
English (en)
Other versions
DE69325749T2 (de
Inventor
Hem P Takiar
Peng-Cheng Lin
Luu T Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69325749D1 publication Critical patent/DE69325749D1/de
Publication of DE69325749T2 publication Critical patent/DE69325749T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
DE69325749T 1992-05-22 1993-05-17 Gestapelte Mehrchip-Module und Verfahren zur Herstellung Expired - Lifetime DE69325749T2 (de)

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Application Number Priority Date Filing Date Title
US07/887,774 US5422435A (en) 1992-05-22 1992-05-22 Stacked multi-chip modules and method of manufacturing

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EP (1) EP0575051B1 (de)
JP (1) JP3356821B2 (de)
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US5502289A (en) 1996-03-26
US5422435A (en) 1995-06-06
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KR930024145A (ko) 1993-12-22
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