DE69318771D1 - Multichip-Modul und Verfahren zu seiner Herstellung - Google Patents

Multichip-Modul und Verfahren zu seiner Herstellung

Info

Publication number
DE69318771D1
DE69318771D1 DE69318771T DE69318771T DE69318771D1 DE 69318771 D1 DE69318771 D1 DE 69318771D1 DE 69318771 T DE69318771 T DE 69318771T DE 69318771 T DE69318771 T DE 69318771T DE 69318771 D1 DE69318771 D1 DE 69318771D1
Authority
DE
Germany
Prior art keywords
manufacture
multichip module
multichip
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69318771T
Other languages
English (en)
Other versions
DE69318771T2 (de
Inventor
Wen-Chou Vincent Wang
William T Chou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/927,151 external-priority patent/US5382827A/en
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69318771D1 publication Critical patent/DE69318771D1/de
Publication of DE69318771T2 publication Critical patent/DE69318771T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69318771T 1992-08-07 1993-08-09 Multichip-Modul und Verfahren zu seiner Herstellung Expired - Fee Related DE69318771T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/927,151 US5382827A (en) 1992-08-07 1992-08-07 Functional substrates for packaging semiconductor chips
US08/097,039 US5475262A (en) 1992-08-07 1993-07-27 Functional substrates for packaging semiconductor chips

Publications (2)

Publication Number Publication Date
DE69318771D1 true DE69318771D1 (de) 1998-07-02
DE69318771T2 DE69318771T2 (de) 1998-09-24

Family

ID=26792405

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69318771T Expired - Fee Related DE69318771T2 (de) 1992-08-07 1993-08-09 Multichip-Modul und Verfahren zu seiner Herstellung

Country Status (4)

Country Link
US (1) US5475262A (de)
EP (1) EP0582315B1 (de)
JP (1) JP3247503B2 (de)
DE (1) DE69318771T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2288286A (en) * 1994-03-30 1995-10-11 Plessey Semiconductors Ltd Ball grid array arrangement
US5726621A (en) * 1994-09-12 1998-03-10 Cooper Industries, Inc. Ceramic chip fuses with multiple current carrying elements and a method for making the same
KR0158765B1 (ko) * 1994-09-21 1999-02-01 모리사다 요이치 반도체 집적회로
US5678057A (en) * 1995-06-07 1997-10-14 Lsi Logic Corporation Multi-Chip-Module (MCM) microcircuit including multiple processors and Advanced Programmable Interrupt Controller (APIC)
US5929474A (en) * 1997-03-10 1999-07-27 Motorola, Inc. Active matrix OED array
US7321485B2 (en) 1997-04-08 2008-01-22 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
US7336468B2 (en) 1997-04-08 2008-02-26 X2Y Attenuators, Llc Arrangement for energy conditioning
US6075427A (en) * 1998-01-23 2000-06-13 Lucent Technologies Inc. MCM with high Q overlapping resonator
US6849480B1 (en) 1999-05-07 2005-02-01 Seagate Technology Llc Surface mount IC stacking method and device
US6232667B1 (en) 1999-06-29 2001-05-15 International Business Machines Corporation Technique for underfilling stacked chips on a cavity MLC module
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6710255B2 (en) * 2001-03-30 2004-03-23 Intel Corporation Printed circuit board having buried intersignal capacitance and method of making
DE10141877B4 (de) * 2001-08-28 2007-02-08 Infineon Technologies Ag Halbleiterbauteil und Konvertereinrichtung
GB2385984B (en) * 2001-11-07 2006-06-28 Micron Technology Inc Semiconductor package assembly and method for electrically isolating modules
JP2003298006A (ja) * 2002-03-29 2003-10-17 Seiko Epson Corp 半導体装置および電気光学装置
US20040189333A1 (en) * 2003-01-10 2004-09-30 Stephan Dobritz Carrier for receiving and electrically contacting individually separated dies
GB2439862A (en) 2005-03-01 2008-01-09 X2Y Attenuators Llc Conditioner with coplanar conductors
KR100963814B1 (ko) * 2005-10-07 2010-06-16 주식회사 코미코 파티클 제거 방법 및 장치, 및 이를 포함하는 파티클 측정방법 및 장치
KR100914552B1 (ko) 2005-07-25 2009-09-02 삼성전자주식회사 반도체 메모리 장치 및 이를 구비하는 메모리 모듈
US8264846B2 (en) 2006-12-14 2012-09-11 Intel Corporation Ceramic package substrate with recessed device
KR101107659B1 (ko) * 2010-02-05 2012-01-20 주식회사 하이닉스반도체 반도체 패키지
US20190206786A1 (en) * 2017-12-28 2019-07-04 Intel Corporation Thin film passive devices integrated in a package substrate

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1112992A (en) * 1964-08-18 1968-05-08 Texas Instruments Inc Three-dimensional integrated circuits and methods of making same
US4649417A (en) * 1983-09-22 1987-03-10 International Business Machines Corporation Multiple voltage integrated circuit packaging substrate
US5082802A (en) * 1985-11-12 1992-01-21 Texas Instruments Incorporated Method of making a memory device by packaging two integrated circuit dies in one package
US4945399A (en) * 1986-09-30 1990-07-31 International Business Machines Corporation Electronic package with integrated distributed decoupling capacitors
JPS63131560A (ja) * 1986-11-17 1988-06-03 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション チップ接続構造体
JPS63258046A (ja) * 1987-04-15 1988-10-25 Toshiba Corp 半導体集積回路装置
JP2790640B2 (ja) * 1989-01-14 1998-08-27 ティーディーケイ株式会社 混成集積回路部品の構造
US5055907A (en) * 1989-01-25 1991-10-08 Mosaic, Inc. Extended integration semiconductor structure with wiring layers
US5013687A (en) * 1989-07-27 1991-05-07 Grumman Aerospace Corporation Framed chip hybrid stacked layer assembly
JPH0378290A (ja) * 1989-08-21 1991-04-03 Hitachi Ltd 多層配線基板
US4991000A (en) * 1989-08-31 1991-02-05 Bone Robert L Vertically interconnected integrated circuit chip system
US5032896A (en) * 1989-08-31 1991-07-16 Hughes Aircraft Company 3-D integrated circuit assembly employing discrete chips

Also Published As

Publication number Publication date
US5475262A (en) 1995-12-12
EP0582315A1 (de) 1994-02-09
DE69318771T2 (de) 1998-09-24
EP0582315B1 (de) 1998-05-27
JPH06163809A (ja) 1994-06-10
JP3247503B2 (ja) 2002-01-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee